Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334617
H. Fu, Shi-Yu Huang, D. Kwai, Yung-Fa Chou
A latent defect in a power-delivery TSVs in a 3D IC could cause power glitches under a heavy workload in the field and thereby leading to timing failure. In order to catch these defects before they actually strikes, on-line ring-oscillator based VDD-drop monitoring schemes have been proposed previously. However, these methods have not taken into account the effect of the temperature, which could affect their accuracy in the final VDD prediction. In this paper, we present a temperature-aware test method for power-delivery TSVs, with several features - including a process-calibration scheme and a temperature-aware worst-case VDD prediction scheme. Based on the these schemes, the pass-or-fail decision on the quality of a power-TSV can be made more accurately.
{"title":"Temperature-aware online testing of power-delivery TSVs","authors":"H. Fu, Shi-Yu Huang, D. Kwai, Yung-Fa Chou","doi":"10.1109/3DIC.2015.7334617","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334617","url":null,"abstract":"A latent defect in a power-delivery TSVs in a 3D IC could cause power glitches under a heavy workload in the field and thereby leading to timing failure. In order to catch these defects before they actually strikes, on-line ring-oscillator based VDD-drop monitoring schemes have been proposed previously. However, these methods have not taken into account the effect of the temperature, which could affect their accuracy in the final VDD prediction. In this paper, we present a temperature-aware test method for power-delivery TSVs, with several features - including a process-calibration scheme and a temperature-aware worst-case VDD prediction scheme. Based on the these schemes, the pass-or-fail decision on the quality of a power-TSV can be made more accurately.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116856749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334566
C. Lam
Microprocessors designed with von Neumann architecture are hitting the power and performance limits as silicon CMOS continues to scale the critical dimensions of the circuit components towards single digit nanometer size limit. Multi-core processor, parallel processing without increasing operating frequency of the cores, was introduced in the early 2000 to extend the power and performance scaling, keeping Moore's Law viable. Evolution has provided us with the most efficient parallel processing architecture: the biological brain. In this talk, we shall examine what we can do with little that we know about how the brain works to design machines to mimic the brain's memory.
{"title":"Neuromorphic semiconductor memory","authors":"C. Lam","doi":"10.1109/3DIC.2015.7334566","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334566","url":null,"abstract":"Microprocessors designed with von Neumann architecture are hitting the power and performance limits as silicon CMOS continues to scale the critical dimensions of the circuit components towards single digit nanometer size limit. Multi-core processor, parallel processing without increasing operating frequency of the cores, was introduced in the early 2000 to extend the power and performance scaling, keeping Moore's Law viable. Evolution has provided us with the most efficient parallel processing architecture: the biological brain. In this talk, we shall examine what we can do with little that we know about how the brain works to design machines to mimic the brain's memory.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114889410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334608
K. Sueoka, A. Horibe, T. Aoki, S. Kohara, K. Toriyama, H. Mori, Y. Orii
A low-cost assembly method is necessary for widespread use of 3D silicon integration. We have been proposing a vertical Si integration process, called Vertical integration after Stacking (ViaS), intended to lower costs, lower stress, and increase yields. The ViaS process uses a polymer insulator and a solder filling technique instead of a SiO2 insulator and Cu plating. Different from conventional processes, each vertical electrical conductor is continuous from the bottom to the top through the silicon stack and the conductor is surrounded with polymer insulators with a low-Young's modulus. As a result, this ViaS process will greatly decrease the stress in vertical conductors and silicon substrates and increase reliability. In this paper, we present prototyped Si stacks with the ViaS process and the analyzed results on their stress characteristics. The results obtained show significant stress reductions at vertical connections between the layers, which would increase the reliability. These features of 3D stacks by the ViaS process will significantly contribute to expanding the range of 3D-integrated device applications.
{"title":"Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration","authors":"K. Sueoka, A. Horibe, T. Aoki, S. Kohara, K. Toriyama, H. Mori, Y. Orii","doi":"10.1109/3DIC.2015.7334608","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334608","url":null,"abstract":"A low-cost assembly method is necessary for widespread use of 3D silicon integration. We have been proposing a vertical Si integration process, called Vertical integration after Stacking (ViaS), intended to lower costs, lower stress, and increase yields. The ViaS process uses a polymer insulator and a solder filling technique instead of a SiO2 insulator and Cu plating. Different from conventional processes, each vertical electrical conductor is continuous from the bottom to the top through the silicon stack and the conductor is surrounded with polymer insulators with a low-Young's modulus. As a result, this ViaS process will greatly decrease the stress in vertical conductors and silicon substrates and increase reliability. In this paper, we present prototyped Si stacks with the ViaS process and the analyzed results on their stress characteristics. The results obtained show significant stress reductions at vertical connections between the layers, which would increase the reliability. These features of 3D stacks by the ViaS process will significantly contribute to expanding the range of 3D-integrated device applications.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128468679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334569
Hiroaki Ikeda, S. Sekine, Ryuji Kimura, Koichi Shimokawa, K. Okada, H. Shindo, T. Ooi, Rei Tamaki, Makoto Nagata
This paper discloses that Nano-Function materials make TSV structure by printing technologies without CVD/PVD/Plating. For isolation layer forming, two types of TSV pattern had been examined. For metal fill, we adopted conductive paste or alloy plate contains nanomized alloys (Cu, Sn and additives) to fill via by less than 250°C condition. Re-melting temperature of the alloy is more than 300°C.
{"title":"Nano-Function materials for TSV technologies","authors":"Hiroaki Ikeda, S. Sekine, Ryuji Kimura, Koichi Shimokawa, K. Okada, H. Shindo, T. Ooi, Rei Tamaki, Makoto Nagata","doi":"10.1109/3DIC.2015.7334569","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334569","url":null,"abstract":"This paper discloses that Nano-Function materials make TSV structure by printing technologies without CVD/PVD/Plating. For isolation layer forming, two types of TSV pattern had been examined. For metal fill, we adopted conductive paste or alloy plate contains nanomized alloys (Cu, Sn and additives) to fill via by less than 250°C condition. Re-melting temperature of the alloy is more than 300°C.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128998392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334579
M. Murugesan, J. Bea, H. Hashimoto, K. Lee, M. Koyanagi, T. Fukushima, Tetsu Tanaka
3D-LSI chip containing through-silicon-via (TSV, diameters ranging from 5 μm to 30 μm) with two different dielectric liners has been investigated for thermo-mechanical stress (TMS) in Si via micro-Raman spectroscopy and micro-X-ray diffraction analysis. Both the micro-Raman and micro-X-ray diffraction results revealed that the low-k CVD-grown dielectric polyimide (PI) liner tremendously reduces the TMS in the vicinal Si as well as the Si sandwiched between TSVs. It can be explained that the observed smaller TMS values for TSVs with PI is owing to the partial accommodation of the expanded Cu during thermal cycling by the low modulus, soft PI.
{"title":"Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study","authors":"M. Murugesan, J. Bea, H. Hashimoto, K. Lee, M. Koyanagi, T. Fukushima, Tetsu Tanaka","doi":"10.1109/3DIC.2015.7334579","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334579","url":null,"abstract":"3D-LSI chip containing through-silicon-via (TSV, diameters ranging from 5 μm to 30 μm) with two different dielectric liners has been investigated for thermo-mechanical stress (TMS) in Si via micro-Raman spectroscopy and micro-X-ray diffraction analysis. Both the micro-Raman and micro-X-ray diffraction results revealed that the low-k CVD-grown dielectric polyimide (PI) liner tremendously reduces the TMS in the vicinal Si as well as the Si sandwiched between TSVs. It can be explained that the observed smaller TMS values for TSVs with PI is owing to the partial accommodation of the expanded Cu during thermal cycling by the low modulus, soft PI.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129001966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334616
T. R. Harris, Eric J. Wyers, Lee Wang, S. Graham, G. Pavlidis, P. Franzon, W. R. Davis
Integration of materials such as GaN, InP, SiGe, and Si is a natural extension of the 3D-IC perspective and provides a unique solution for high performance circuits. In this approach, application of a component is no longer dependent on semiconductor material selection. In this paper, preliminary results are presented which examine the thermal performance of the technology. A thermal analysis prototype solution in Mentor Graphics™ Calibre® provides surface heat maps based on IC layout, material property, and geometric configuration files. Chiplets are connected by heterogeneous interconnect (HIC). Differences in thermal performance of GaN and InP chiplets are explored by varying the number of HICs. Two methods for building up the model of a test chip are compared. One method uses custom scripts to place discrete blocks in the model to represent HICs, while the other uses thermal material properties extracted from the layout. Measurements presented confirm simulated results.
{"title":"Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks","authors":"T. R. Harris, Eric J. Wyers, Lee Wang, S. Graham, G. Pavlidis, P. Franzon, W. R. Davis","doi":"10.1109/3DIC.2015.7334616","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334616","url":null,"abstract":"Integration of materials such as GaN, InP, SiGe, and Si is a natural extension of the 3D-IC perspective and provides a unique solution for high performance circuits. In this approach, application of a component is no longer dependent on semiconductor material selection. In this paper, preliminary results are presented which examine the thermal performance of the technology. A thermal analysis prototype solution in Mentor Graphics™ Calibre® provides surface heat maps based on IC layout, material property, and geometric configuration files. Chiplets are connected by heterogeneous interconnect (HIC). Differences in thermal performance of GaN and InP chiplets are explored by varying the number of HICs. Two methods for building up the model of a test chip are compared. One method uses custom scripts to place discrete blocks in the model to represent HICs, while the other uses thermal material properties extracted from the layout. Measurements presented confirm simulated results.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129184140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334615
G. Refai-Ahmed, Ivor Barber, Anthony Torza, Brian Philofsky
Silicon Interconnect Technology (SSIT) enables superior feature integration beyond what is possible in monolithic technology with only a Moore's Law feature shrink as well as heterogeneous feature integration of disparate dice (e.g. memories, RF DAC/ADCs, optical interfaces, customer ASICs etc.). In a Telecom environment, this superior feature density enables new applications, but also presents higher thermal density to the Thermal Engineer. To properly utilize these benefits, a Thermal Engineer must take a holistic approach to thermal architecture that simultaneously addresses system goals of Cost, Performance, Weight, Size, Power and Performance. This paper will discuss the critical parameters which impact thermal architecture, followed by Challenges in Indoor and Outdoor Telecom Systems from device and system perspectives and finally will show the impact of combining network utilization and heterogeneous load in the user's environment.
{"title":"A holistic view of chip-level thermal architecture from heterogeneous stacked dice to system level in telecoms applications","authors":"G. Refai-Ahmed, Ivor Barber, Anthony Torza, Brian Philofsky","doi":"10.1109/3DIC.2015.7334615","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334615","url":null,"abstract":"Silicon Interconnect Technology (SSIT) enables superior feature integration beyond what is possible in monolithic technology with only a Moore's Law feature shrink as well as heterogeneous feature integration of disparate dice (e.g. memories, RF DAC/ADCs, optical interfaces, customer ASICs etc.). In a Telecom environment, this superior feature density enables new applications, but also presents higher thermal density to the Thermal Engineer. To properly utilize these benefits, a Thermal Engineer must take a holistic approach to thermal architecture that simultaneously addresses system goals of Cost, Performance, Weight, Size, Power and Performance. This paper will discuss the critical parameters which impact thermal architecture, followed by Challenges in Indoor and Outdoor Telecom Systems from device and system perspectives and finally will show the impact of combining network utilization and heterogeneous load in the user's environment.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115753636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334568
Yangyang Yan, Yingtao Ding, Qianwen Chen, Kang-wook Lee, T. Fukushima, M. Koyanagi
In this paper, by combining conventional spin coating method with vacuum treatment, a relatively simple and feasible process technique referred to as vacuum-assisted spin coating technique was proposed to get uniform polyimide liner along sidewalls of high aspect ratio Through-Silicon-Vias (TSVs) for three-dimensional (3D) integration applications. Details about the proposed technique were illustrated and test structures of silicon blind vias with diameter of about 6μm and depth of about 51μm were successfully sidewall coated with polyimide liner with step coverage around 30% utilizing the technique proposed. For thermal reliability investigations of the cured polyimide liner, X-ray photoelectron spectroscopy (XPS) analysis was performed to get the chemical state information of the cured polyimide liner. Also, planar metal-insulator-semiconductor (MIS) capacitor which involves polyimide as insulator was built to investigate electrical properties of polyimide liner formed. Electrical characteristics such as capacitance-voltage(C-V) curve and leakage current under biased voltage up to 20V were measured. All these results showed the potential of the technique proposed to be applied to high aspect ratio TSVs for 3D integration.
{"title":"Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications","authors":"Yangyang Yan, Yingtao Ding, Qianwen Chen, Kang-wook Lee, T. Fukushima, M. Koyanagi","doi":"10.1109/3DIC.2015.7334568","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334568","url":null,"abstract":"In this paper, by combining conventional spin coating method with vacuum treatment, a relatively simple and feasible process technique referred to as vacuum-assisted spin coating technique was proposed to get uniform polyimide liner along sidewalls of high aspect ratio Through-Silicon-Vias (TSVs) for three-dimensional (3D) integration applications. Details about the proposed technique were illustrated and test structures of silicon blind vias with diameter of about 6μm and depth of about 51μm were successfully sidewall coated with polyimide liner with step coverage around 30% utilizing the technique proposed. For thermal reliability investigations of the cured polyimide liner, X-ray photoelectron spectroscopy (XPS) analysis was performed to get the chemical state information of the cured polyimide liner. Also, planar metal-insulator-semiconductor (MIS) capacitor which involves polyimide as insulator was built to investigate electrical properties of polyimide liner formed. Electrical characteristics such as capacitance-voltage(C-V) curve and leakage current under biased voltage up to 20V were measured. All these results showed the potential of the technique proposed to be applied to high aspect ratio TSVs for 3D integration.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"155-156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114384399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334471
K. Lee, C. Nagai, A. Nakamura, Hiroki Aizawa, J. Bea, M. Koyanagi, H. Hashiguchi, T. Fukushima, Tanaka Tanaka
High yield reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology is proposed for ultra-high density 2.5D/3D integration applications. New mCoW hybrid bonding technology use shallow-recess oxide structure, electro-less plated capping layers, and thin glue adhesive layer below 1um to avoid the issues of current standard CoW bonding technology. Multi numbers of TEG die with 7mm × 23mm size are simultaneously aligned with high accuracy around 1um using chip self-assembly technology and thermal-compression bonded by in batch. In the TEG chip, totally 684,000 electrode daisy chain comprising of 3μm diameter/6um pitch tiny Cu electrodes are well intact joined by new reconfigured mCoW hybrid bonding technology.
{"title":"Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers","authors":"K. Lee, C. Nagai, A. Nakamura, Hiroki Aizawa, J. Bea, M. Koyanagi, H. Hashiguchi, T. Fukushima, Tanaka Tanaka","doi":"10.1109/3DIC.2015.7334471","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334471","url":null,"abstract":"High yield reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology is proposed for ultra-high density 2.5D/3D integration applications. New mCoW hybrid bonding technology use shallow-recess oxide structure, electro-less plated capping layers, and thin glue adhesive layer below 1um to avoid the issues of current standard CoW bonding technology. Multi numbers of TEG die with 7mm × 23mm size are simultaneously aligned with high accuracy around 1um using chip self-assembly technology and thermal-compression bonded by in batch. In the TEG chip, totally 684,000 electrode daisy chain comprising of 3μm diameter/6um pitch tiny Cu electrodes are well intact joined by new reconfigured mCoW hybrid bonding technology.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114747927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334577
N. Asahi, Y. Miyamoto, M. Nimura, Y. Mizutani, Y. Arai
The evaluation result of 4 layer stacked IC which was bonded using thermal compression bonder (TCB) is reported. The throughput can be remarkably improved because chips of multi-layer can be pre bonded by using non-conductive film (NCF) which is pre-applied adhesive and can be thermally pressed at a time. To realize this process, we stacked the 4 chips having through silicon via (TSV) on a Si substrate and evaluated the connectibility. As the evaluation after bonding, wettability of a solder by cross-section observation and a void in NCF layer by constant depth mode scanning acoustic microscope (C-SAM) observation were confirmed. As a result, it was confirmed that the voidless and good solder joints were possible by reducing the temperature difference in a stacking direction. For the evaluation, we used the TEG of 6 mm × 6 mm × 0.05 mm size which has more than 15,000 bumps of 12 μm height and 15 μm diameter. It was also demonstrated that gang bonding for a plurality of pre bonded chips formed on a substrate was possible by using the novel bonding attachment which accepts the thicknesses difference of 5 μm.
报道了采用热压缩粘结剂(TCB)粘结的4层堆叠集成电路的评价结果。采用预涂胶、一次性热压的非导电膜(NCF)对多层芯片进行预粘接，可显著提高芯片的吞吐量。为了实现这一过程，我们将4个具有通硅孔(TSV)的芯片堆叠在硅衬底上，并评估了可连接性。作为焊后的评价，通过截面观察证实了焊料的润湿性，通过恒深模式扫描声显微镜(C-SAM)观察证实了NCF层中存在空洞。结果表明，通过减小堆焊方向上的温差，可以得到无空洞、良好的焊点。为了进行评价，我们使用了尺寸为6 mm × 6 mm × 0.05 mm的TEG，该TEG具有超过15,000个高度为12 μm，直径为15 μm的凸起。实验还表明，采用该新型键合附件，可以实现在衬底上形成的多个预键合芯片的键合，其厚度差为5 μm。
{"title":"High productivity thermal compression bonding for 3D-IC","authors":"N. Asahi, Y. Miyamoto, M. Nimura, Y. Mizutani, Y. Arai","doi":"10.1109/3DIC.2015.7334577","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334577","url":null,"abstract":"The evaluation result of 4 layer stacked IC which was bonded using thermal compression bonder (TCB) is reported. The throughput can be remarkably improved because chips of multi-layer can be pre bonded by using non-conductive film (NCF) which is pre-applied adhesive and can be thermally pressed at a time. To realize this process, we stacked the 4 chips having through silicon via (TSV) on a Si substrate and evaluated the connectibility. As the evaluation after bonding, wettability of a solder by cross-section observation and a void in NCF layer by constant depth mode scanning acoustic microscope (C-SAM) observation were confirmed. As a result, it was confirmed that the voidless and good solder joints were possible by reducing the temperature difference in a stacking direction. For the evaluation, we used the TEG of 6 mm × 6 mm × 0.05 mm size which has more than 15,000 bumps of 12 μm height and 15 μm diameter. It was also demonstrated that gang bonding for a plurality of pre bonded chips formed on a substrate was possible by using the novel bonding attachment which accepts the thicknesses difference of 5 μm.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126256665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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