Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334609
K. Ohta, Atsushi Hirate, Yuto Miyachi, Tomohiro Shimizu, S. Shingubara
For realizing high aspect ratio TSV with a low cost, the all-wet process using electroless barrier and seed layers prior to Cu electroplated fill is one of the key technology. However, improvement of adhesion property of electroless plated Cu seed layers on the barrier layer has been intensively required. In this study, we studied displacement plating of Cu on electroless CoWB barrier layer in an acidic bath. It is confirmed that the displacement plated Cu film has a high adhesion strength which is enough to pass CMP process.
{"title":"All-wet TSV filling with highly adhesive displacement plated Cu seed layer","authors":"K. Ohta, Atsushi Hirate, Yuto Miyachi, Tomohiro Shimizu, S. Shingubara","doi":"10.1109/3DIC.2015.7334609","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334609","url":null,"abstract":"For realizing high aspect ratio TSV with a low cost, the all-wet process using electroless barrier and seed layers prior to Cu electroplated fill is one of the key technology. However, improvement of adhesion property of electroless plated Cu seed layers on the barrier layer has been intensively required. In this study, we studied displacement plating of Cu on electroless CoWB barrier layer in an acidic bath. It is confirmed that the displacement plated Cu film has a high adhesion strength which is enough to pass CMP process.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116052900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334596
H. Kino, H. Hashiguchi, S. Tanikawa, Y. Sugawara, Shunsuke Ikegaya, T. Fukushima, M. Koyanagi, Tetsu Tanaka
Three-dimensional IC (3D IC) has attracted much attention as a promising method to enhance IC performance. Recently, great interests in mechanical reliability are increasing among 3D IC researchers for production of 3D IC. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive called underfill material. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE difference induces local bending stress in thinned IC chips. This local bending stress would affect transistor reliability in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we present design guideline of microbump layout which can suppress the local bending stress in 3D-stacked several thin IC chips.
{"title":"Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC","authors":"H. Kino, H. Hashiguchi, S. Tanikawa, Y. Sugawara, Shunsuke Ikegaya, T. Fukushima, M. Koyanagi, Tetsu Tanaka","doi":"10.1109/3DIC.2015.7334596","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334596","url":null,"abstract":"Three-dimensional IC (3D IC) has attracted much attention as a promising method to enhance IC performance. Recently, great interests in mechanical reliability are increasing among 3D IC researchers for production of 3D IC. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive called underfill material. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE difference induces local bending stress in thinned IC chips. This local bending stress would affect transistor reliability in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we present design guideline of microbump layout which can suppress the local bending stress in 3D-stacked several thin IC chips.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124231575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334563
Mostafizur Rahman, S. Khasanvis, Jiajun Shi, Mingyu Li, C. A. Moritz
Continuous scaling of CMOS to sub-20nm technologies is proving to be challenging as MOSFETs are reaching fundamental limits and interconnection bottleneck is dominating IC power and performance. Migrating to fine-grained 3-D, to advance scaling, has been elusive due to incompatibility of CMOS in 3-D. We propose a new 3-D IC fabric, called Skybridge that addresses device, circuit, connectivity, heat management and manufacturing requirements in integrated 3D compatible manner. Our bottom-up evaluations accounting for material structures, manufacturing process, device, and circuit parasitics, reveal 60.5x density, and 16.5x performance/Watts benefits compared to CMOS for a 16-bit CLA. Experimental demonstration of the core device concept and key manufacturing steps mitigate technology risks.
{"title":"Fine-grained 3-D integrated circuit fabric using vertical nanowires","authors":"Mostafizur Rahman, S. Khasanvis, Jiajun Shi, Mingyu Li, C. A. Moritz","doi":"10.1109/3DIC.2015.7334563","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334563","url":null,"abstract":"Continuous scaling of CMOS to sub-20nm technologies is proving to be challenging as MOSFETs are reaching fundamental limits and interconnection bottleneck is dominating IC power and performance. Migrating to fine-grained 3-D, to advance scaling, has been elusive due to incompatibility of CMOS in 3-D. We propose a new 3-D IC fabric, called Skybridge that addresses device, circuit, connectivity, heat management and manufacturing requirements in integrated 3D compatible manner. Our bottom-up evaluations accounting for material structures, manufacturing process, device, and circuit parasitics, reveal 60.5x density, and 16.5x performance/Watts benefits compared to CMOS for a 16-bit CLA. Experimental demonstration of the core device concept and key manufacturing steps mitigate technology risks.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125275823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334574
G. Pillonnet, Nicolas Jeanniot, P. Vivet
With 3D technologies, the in-package solution allows integrated, efficient and granular power supplies to be designed for multi-core processors. As the converter design obtains few benefits from the scaling, 3DIC allows the best technology to be chosen i.e. one which suits the DC-DC converter design. This paper evaluates the achievable power efficiency between on-die and in-package converters using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM, vertical capacitor) layers. Based on the same load power consumption, on-die and in-package switched capacitor converters achieve 65% and 78% efficiency, respectively, in a 1mm2 silicon area. An additional high density capacitance layer (100nF/mm2) improves efficiency by more than 20 points in 65nm for the same surface which emphasizes the need for dedicated technology for better power management integration. This paper shows that in-package power management is a key alternative for fully-integrated, dense and efficient power supplies.
{"title":"3D ICs: An opportunity for fully-integrated, dense and efficient power supplies","authors":"G. Pillonnet, Nicolas Jeanniot, P. Vivet","doi":"10.1109/3DIC.2015.7334574","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334574","url":null,"abstract":"With 3D technologies, the in-package solution allows integrated, efficient and granular power supplies to be designed for multi-core processors. As the converter design obtains few benefits from the scaling, 3DIC allows the best technology to be chosen i.e. one which suits the DC-DC converter design. This paper evaluates the achievable power efficiency between on-die and in-package converters using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM, vertical capacitor) layers. Based on the same load power consumption, on-die and in-package switched capacitor converters achieve 65% and 78% efficiency, respectively, in a 1mm2 silicon area. An additional high density capacitance layer (100nF/mm2) improves efficiency by more than 20 points in 65nm for the same surface which emphasizes the need for dedicated technology for better power management integration. This paper shows that in-package power management is a key alternative for fully-integrated, dense and efficient power supplies.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"716 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127155127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334553
A. Jouve, Y. Sinquin, A. Garnier, M. Daval, P. Chausse, M. Argoud, N. Allouti, L. Baud, J. Dechamp, R. Franiatte, S. Chéramy, H. Kato, K. Kondo
This paper is dedicated to the full integration of innovative silicon-based material for Wafer-Level molding of silicon interposer wafers. This technology can be used in the frame of silicon packages where the silicon interposer is either reported on P-BGA or directly assembled on board. Interest of such material, is the rapid Wafer-Level lamination process and die planarization which can facilitate interposer realization. In a first part of the article, we have evaluated the compatibility of this material with the whole interposer flow by having a focus on filling capacities as well as induced deformation on 300mm wafers. Secondly, we have generated electrical test vehicles in order to verify the impact of such material on environmental and mechanical reliability.
{"title":"Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvement","authors":"A. Jouve, Y. Sinquin, A. Garnier, M. Daval, P. Chausse, M. Argoud, N. Allouti, L. Baud, J. Dechamp, R. Franiatte, S. Chéramy, H. Kato, K. Kondo","doi":"10.1109/3DIC.2015.7334553","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334553","url":null,"abstract":"This paper is dedicated to the full integration of innovative silicon-based material for Wafer-Level molding of silicon interposer wafers. This technology can be used in the frame of silicon packages where the silicon interposer is either reported on P-BGA or directly assembled on board. Interest of such material, is the rapid Wafer-Level lamination process and die planarization which can facilitate interposer realization. In a first part of the article, we have evaluated the compatibility of this material with the whole interposer flow by having a focus on filling capacities as well as induced deformation on 300mm wafers. Secondly, we have generated electrical test vehicles in order to verify the impact of such material on environmental and mechanical reliability.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121716006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334573
Chuei-Tang Wang, J. Hsieh, V. Chang, E. Yeh, F. Kuo, Hsu-Hsien Chen, Chih-Hua Chen, H. Chen, Ying-Ta Lu, C. Jou, H. Tsai, C. S. Liu, Doug C. H. Yu
An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of -53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO, respectively, compared with those in RF SoC system. The InFO technology provides a novel solution for RF system integration.
{"title":"Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology","authors":"Chuei-Tang Wang, J. Hsieh, V. Chang, E. Yeh, F. Kuo, Hsu-Hsien Chen, Chih-Hua Chen, H. Chen, Ying-Ta Lu, C. Jou, H. Tsai, C. S. Liu, Doug C. H. Yu","doi":"10.1109/3DIC.2015.7334573","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334573","url":null,"abstract":"An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of -53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO, respectively, compared with those in RF SoC system. The InFO technology provides a novel solution for RF system integration.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115265512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334467
V. Rao
The document was not made available for publication as part of the conference proceedings.
该文件没有作为会议记录的一部分提供出版。
{"title":"IME's capabilities and programs in 2.5D/3DIC","authors":"V. Rao","doi":"10.1109/3DIC.2015.7334467","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334467","url":null,"abstract":"The document was not made available for publication as part of the conference proceedings.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130389077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/CICC.2015.7338401
P. Franzon, E. Rotenberg, James Tuck, W. R. Davis, Huiyang Zhou, J. Schabel, Zhenqian Zhang, J. B. Dwiel, E. Forbes, Joonmoo Huh, M. Tshibangu, S. Lipa
3DIC technology refers to stacking and interconnecting chips and substrates (“interposers”) with Through Silicon Vias (TSVs). Industry is gearing up for widespread introduction of this technology with the 22 nm node. We have been pursuing a range of approaches to enable low power computing. As well as 3DIC these include heterogeneous computing, powered optimized SIMD units, optimized memory hierarchies, and MPI with post-silicon customized interconnect. Heterogeneous computing refers to the concept of building a mix of CPUs and memories that in turn enable in-situ tuning of the compute load to the compute resources. We introduce the concept of Fast Thread Migration using 3DIC technologies. We present the design of a power optimized SIMD unit in which over half of the power is employed in the FP units. A parallel computer is built using an MPI paradigm. Codes are analyzed so that the MPI interconnect can be power optimized post-silicon. Emerging 3D memories have potential to be employed as Level 2 and Level 3 caches, and this is explored using the Tezzaron 3D memory. As scaling and power optimization occurs, the main memory increasingly dominates the power consumption. Possible extensions to Cortical Processing are discussed.
{"title":"Computing in 3D","authors":"P. Franzon, E. Rotenberg, James Tuck, W. R. Davis, Huiyang Zhou, J. Schabel, Zhenqian Zhang, J. B. Dwiel, E. Forbes, Joonmoo Huh, M. Tshibangu, S. Lipa","doi":"10.1109/CICC.2015.7338401","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338401","url":null,"abstract":"3DIC technology refers to stacking and interconnecting chips and substrates (“interposers”) with Through Silicon Vias (TSVs). Industry is gearing up for widespread introduction of this technology with the 22 nm node. We have been pursuing a range of approaches to enable low power computing. As well as 3DIC these include heterogeneous computing, powered optimized SIMD units, optimized memory hierarchies, and MPI with post-silicon customized interconnect. Heterogeneous computing refers to the concept of building a mix of CPUs and memories that in turn enable in-situ tuning of the compute load to the compute resources. We introduce the concept of Fast Thread Migration using 3DIC technologies. We present the design of a power optimized SIMD unit in which over half of the power is employed in the FP units. A parallel computer is built using an MPI paradigm. Codes are analyzed so that the MPI interconnect can be power optimized post-silicon. Emerging 3D memories have potential to be employed as Level 2 and Level 3 caches, and this is explored using the Tezzaron 3D memory. As scaling and power optimization occurs, the main memory increasingly dominates the power consumption. Possible extensions to Cortical Processing are discussed.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131975611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334463
E. Beyne
The document was not made available for publication as part of the conference proceedings.
该文件没有作为会议记录的一部分提供出版。
{"title":"3D system integration research at IMEC","authors":"E. Beyne","doi":"10.1109/3DIC.2015.7334463","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334463","url":null,"abstract":"The document was not made available for publication as part of the conference proceedings.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134337916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334592
Kosuke Nanbara, Akihiro Odoriba, M. Hashizume, H. Yotsuyanagi, Shyue-Kung Lu
In this paper, an electrical interconnect test method and a built-in test circuit are proposed to detect and locate open defects in a 3D stacked IC made of dies, in which ESD protection circuits are not embedded. The test method is based on quiescent supply current that is made flow through the interconnect to be tested only in the tests. Feasibility of the tests is evaluated by Spice simulation. The simulation results show that open defects in a 3D stacked IC not embedding ESD protection circuits are detected by the test method, like in the tests of ICs embedding ESD protection circuits.
{"title":"Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit","authors":"Kosuke Nanbara, Akihiro Odoriba, M. Hashizume, H. Yotsuyanagi, Shyue-Kung Lu","doi":"10.1109/3DIC.2015.7334592","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334592","url":null,"abstract":"In this paper, an electrical interconnect test method and a built-in test circuit are proposed to detect and locate open defects in a 3D stacked IC made of dies, in which ESD protection circuits are not embedded. The test method is based on quiescent supply current that is made flow through the interconnect to be tested only in the tests. Feasibility of the tests is evaluated by Spice simulation. The simulation results show that open defects in a 3D stacked IC not embedding ESD protection circuits are detected by the test method, like in the tests of ICs embedding ESD protection circuits.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131344890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：