Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236006
Nourhan El Beheiry, M. E. Sharkawy, M. Lotfy, S. Elnoubi
Compressed video bitstream is sensitive to channel errors that may severely degrade the reconstructed pictures. Error concealment techniques implemented at decoders are effective approaches to reduce the impact of errors. They mask the effect of missing blocks by using the spatial or/and temporal correlation to create image or video of subjectively acceptable quality.
{"title":"An adaptive fast and efficient spatial error concealment technique for block-based video coding systems","authors":"Nourhan El Beheiry, M. E. Sharkawy, M. Lotfy, S. Elnoubi","doi":"10.1109/MWSCAS.2009.5236006","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236006","url":null,"abstract":"Compressed video bitstream is sensitive to channel errors that may severely degrade the reconstructed pictures. Error concealment techniques implemented at decoders are effective approaches to reduce the impact of errors. They mask the effect of missing blocks by using the spatial or/and temporal correlation to create image or video of subjectively acceptable quality.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"8 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116777242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235944
S. Subash, Md. Sajjad Rahaman, M. Chowdhury
In current literature various equivalent circuit models and reduction techniques have been demonstrated to study the behavior and performance of carbon nano tubes (CNTs). However, most of these methods are very complex and predominantly use SPICE/HSPICE simulations resulting in high computational time. This paper presents a compact modeling approach for CNT interconnects. Results both in the time domain and frequency domain are provided using a Fourier series approach for the analysis of CNT interconnects. The results obtained are compared against other conventional methods. The percentage error in delay for both single walled CNT (SWCNT) and multi-walled CNT (MWCNT) interconnects is found to be less than 5% and the percentage error in overshoot estimation for both types of CNTs is also under 8%.
{"title":"Compact model for carbon nanotubes interconnects using fourier series analysis","authors":"S. Subash, Md. Sajjad Rahaman, M. Chowdhury","doi":"10.1109/MWSCAS.2009.5235944","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235944","url":null,"abstract":"In current literature various equivalent circuit models and reduction techniques have been demonstrated to study the behavior and performance of carbon nano tubes (CNTs). However, most of these methods are very complex and predominantly use SPICE/HSPICE simulations resulting in high computational time. This paper presents a compact modeling approach for CNT interconnects. Results both in the time domain and frequency domain are provided using a Fourier series approach for the analysis of CNT interconnects. The results obtained are compared against other conventional methods. The percentage error in delay for both single walled CNT (SWCNT) and multi-walled CNT (MWCNT) interconnects is found to be less than 5% and the percentage error in overshoot estimation for both types of CNTs is also under 8%.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125638607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235990
O. Starostenko, R. Contreras Gomez, V. Alarcón-Aquino, O. Sergiyenko
This paper presents the analysis of emerging data exchange technologies used for integration of mobile devices to image-based learning process of second language. Particularly, the design of portable personal spaces providing mobile access to multimedia documents based on XML technologies and creation of generic interfaces for learning environments have been carried out. For image-based languages learning that implies the image processing, recognition, and retrieval Two Segment Turning function has been proposed and analyzed for possible adoption in applications assisted by mobile devices. The evaluation of designed prototype of image-based language learning system for interpretation of Japanese kanji and Mayan glyphs on mobile devices is discussed in this paper. Additionally the performance of proposed approaches used in content-based image retrieval is evaluated for their possible integration within mobile learning environments.
{"title":"CBIR for image-based language learning within mobile environment","authors":"O. Starostenko, R. Contreras Gomez, V. Alarcón-Aquino, O. Sergiyenko","doi":"10.1109/MWSCAS.2009.5235990","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235990","url":null,"abstract":"This paper presents the analysis of emerging data exchange technologies used for integration of mobile devices to image-based learning process of second language. Particularly, the design of portable personal spaces providing mobile access to multimedia documents based on XML technologies and creation of generic interfaces for learning environments have been carried out. For image-based languages learning that implies the image processing, recognition, and retrieval Two Segment Turning function has been proposed and analyzed for possible adoption in applications assisted by mobile devices. The evaluation of designed prototype of image-based language learning system for interpretation of Japanese kanji and Mayan glyphs on mobile devices is discussed in this paper. Additionally the performance of proposed approaches used in content-based image retrieval is evaluated for their possible integration within mobile learning environments.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131603262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236022
S. Vijay
In recent times, we have seen that shift-and-add operations have replaced multiplication for efficient hardware implementation to achieve reduction in hardware and power. Previously, researchers have proposed methods combining architectural transformations and shift-and-add decompositions for hardware optimizations. In this paper, a highly efficient common subexpression elimination (CSE) algorithm based on the binary representation of the system matrices to optimize the hardware requirements in linear Digital Signal Processing (DSP) synthesis is proposed. The algorithm chooses the maximum number of frequently occurring subexpressions to eliminate redundant computations and hence reduces the number of adders required to implement the multiplications in the state space model. Design examples of systems show that the proposed method offers a hardware reduction of around 22% over the previously best known method [11].
{"title":"Low-complexity implementation of state-space structures in linear DSP synthesis","authors":"S. Vijay","doi":"10.1109/MWSCAS.2009.5236022","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236022","url":null,"abstract":"In recent times, we have seen that shift-and-add operations have replaced multiplication for efficient hardware implementation to achieve reduction in hardware and power. Previously, researchers have proposed methods combining architectural transformations and shift-and-add decompositions for hardware optimizations. In this paper, a highly efficient common subexpression elimination (CSE) algorithm based on the binary representation of the system matrices to optimize the hardware requirements in linear Digital Signal Processing (DSP) synthesis is proposed. The algorithm chooses the maximum number of frequently occurring subexpressions to eliminate redundant computations and hence reduces the number of adders required to implement the multiplications in the state space model. Design examples of systems show that the proposed method offers a hardware reduction of around 22% over the previously best known method [11].","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132931064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235998
M. Karunaratne, B. Oomann
We applied a BIST soft repair scheme to embedded memories using redundant data columns. We obtained yield and defect data from commercial silicon parts, and explored possible yield improvements with only a single bit repair. We implemented it on a chip with 90 memories and process margins were changed to obtain split lots to validate the repair scheme.
{"title":"Yield gain with memory BISR — a case study","authors":"M. Karunaratne, B. Oomann","doi":"10.1109/MWSCAS.2009.5235998","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235998","url":null,"abstract":"We applied a BIST soft repair scheme to embedded memories using redundant data columns. We obtained yield and defect data from commercial silicon parts, and explored possible yield improvements with only a single bit repair. We implemented it on a chip with 90 memories and process margins were changed to obtain split lots to validate the repair scheme.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134152701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236097
A. Munoz, Cyrus D. Cantrell
The key problem in a parallel system is how to distribute the work load to the components of the system in order to get optimal resource utilization, maximize throughput, and minimize response time. The sliding-window (SW) switch is a highly parallel architecture that uses an array of memory-modules to store and process data packets in high speed-networks and Internets. In this paper, we study two key aspects in the design of a high-speed router/switch using the SW switch architecture. The effect of the memory-configuration and the memory-bandwidth in the performance of the SW switch architecture is investigated under bursty-traffic conditions.
{"title":"Memory-configuration and memory-bandwidth in the sliding-window (SW) switch architecture","authors":"A. Munoz, Cyrus D. Cantrell","doi":"10.1109/MWSCAS.2009.5236097","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236097","url":null,"abstract":"The key problem in a parallel system is how to distribute the work load to the components of the system in order to get optimal resource utilization, maximize throughput, and minimize response time. The sliding-window (SW) switch is a highly parallel architecture that uses an array of memory-modules to store and process data packets in high speed-networks and Internets. In this paper, we study two key aspects in the design of a high-speed router/switch using the SW switch architecture. The effect of the memory-configuration and the memory-bandwidth in the performance of the SW switch architecture is investigated under bursty-traffic conditions.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134417449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236053
Tsan-Jieh Chen, H. Chiueh, H. Tsai, Chin-Fong Chiu
high resolution image combination and processing plays an important role in today's satellites' remote sensing applications. This paper presents an image recombination and processing circuitries (ICAI) for one-dimensional multi-strip CMOS image sensors. The proposed system take advantage of the satellites' linear moving property to control the expose time of CMOS image sensor and provides the realtime ability to continuous generate 12,000 × N high-resolution image for space remote sensing applications. The ICAI chip contains an image sensor control logics, image combiner, and host interface, one-dimensional pixel is combined to form a two-dimensional image by proposed circuitry. A prototype chip of ICAI was designed and fabricated with TSMC 0.18 µm CMOS 1P6M technology. The die size is 2.91 mm by 2.91 mm, and the power consumption is 20 mW operating at 8MHz under a 1.8 V supply voltage.
高分辨率图像的组合与处理在当今卫星遥感应用中发挥着重要作用。提出了一种用于一维多条带CMOS图像传感器的图像重组与处理电路(ICAI)。该系统利用卫星的线性运动特性来控制CMOS图像传感器的曝光时间，为空间遥感应用提供连续生成12000 × N高分辨率图像的实时能力。ICAI芯片包含图像传感器控制逻辑、图像合并器和主机接口，通过所提出的电路将一维像素组合成二维图像。采用台积电0.18µm CMOS 1P6M工艺设计制作了ICAI原型芯片。芯片尺寸为2.91 mm × 2.91 mm，功耗为20mw，工作频率为8MHz，电源电压为1.8 V。
{"title":"An image combiner and acquisition interface for space remote sensing applications","authors":"Tsan-Jieh Chen, H. Chiueh, H. Tsai, Chin-Fong Chiu","doi":"10.1109/MWSCAS.2009.5236053","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236053","url":null,"abstract":"high resolution image combination and processing plays an important role in today's satellites' remote sensing applications. This paper presents an image recombination and processing circuitries (ICAI) for one-dimensional multi-strip CMOS image sensors. The proposed system take advantage of the satellites' linear moving property to control the expose time of CMOS image sensor and provides the realtime ability to continuous generate 12,000 × N high-resolution image for space remote sensing applications. The ICAI chip contains an image sensor control logics, image combiner, and host interface, one-dimensional pixel is combined to form a two-dimensional image by proposed circuitry. A prototype chip of ICAI was designed and fabricated with TSMC 0.18 µm CMOS 1P6M technology. The die size is 2.91 mm by 2.91 mm, and the power consumption is 20 mW operating at 8MHz under a 1.8 V supply voltage.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131857048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235918
Huey Chian Foong, M. T. Tan, Yuanjin Zheng
This paper presents the design of a supply and process-insensitive 12-bit Digital Pulse Width Modulator (DPWM) for digital DC-DC converters. The DPWM is realized by a counter and a ring oscillator-multiplexer segmented tapped delay line. The ring oscillator of the tapped delay line is made insensitive to supply and process variation by biasing the differential delay cells with a supply-insensitive replica bias circuit. Simulation results show that the variation of the switching frequency of the DPWM at 1.03MHz is 0.4% for supply voltage variation between 1.5V and 2.5V and 0.95% over the temperature range from −40°C to 90°C. Monte-Carlo simulation was also performed to account for the effect of mismatch between the transistors of the ring oscillator. The worst case delay of the delay cells is 0.87% for ±5% (3-σ) mismatch.
{"title":"A supply and process-insensitive 12-bit DPWM for digital DC-DC converters","authors":"Huey Chian Foong, M. T. Tan, Yuanjin Zheng","doi":"10.1109/MWSCAS.2009.5235918","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235918","url":null,"abstract":"This paper presents the design of a supply and process-insensitive 12-bit Digital Pulse Width Modulator (DPWM) for digital DC-DC converters. The DPWM is realized by a counter and a ring oscillator-multiplexer segmented tapped delay line. The ring oscillator of the tapped delay line is made insensitive to supply and process variation by biasing the differential delay cells with a supply-insensitive replica bias circuit. Simulation results show that the variation of the switching frequency of the DPWM at 1.03MHz is 0.4% for supply voltage variation between 1.5V and 2.5V and 0.95% over the temperature range from −40°C to 90°C. Monte-Carlo simulation was also performed to account for the effect of mismatch between the transistors of the ring oscillator. The worst case delay of the delay cells is 0.87% for ±5% (3-σ) mismatch.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132156103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235879
B. Carvajal-Gámez, F. Gallegos-Funes, J. López-Bonilla
When we talk about steganographic algorithms, it is imperative to study the quality of the image hosting and image retrieval, and is also necessary to consider the robustness of the algorithm. This paper presents the experimental results obtained by applying a steganographic algorithm to RGB images. The measures used are qualitative and quantitative related to the multichannel of Human Vision System. When this algorithm is employed we see that the numerical calculations performed by the computer cause errors and alterations in the images chosen, so we applied a scaling factor depending on the number of bits of the image to adjust these errors.
{"title":"Energy adjustment RGB images in steganography applications","authors":"B. Carvajal-Gámez, F. Gallegos-Funes, J. López-Bonilla","doi":"10.1109/MWSCAS.2009.5235879","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235879","url":null,"abstract":"When we talk about steganographic algorithms, it is imperative to study the quality of the image hosting and image retrieval, and is also necessary to consider the robustness of the algorithm. This paper presents the experimental results obtained by applying a steganographic algorithm to RGB images. The measures used are qualitative and quantitative related to the multichannel of Human Vision System. When this algorithm is employed we see that the numerical calculations performed by the computer cause errors and alterations in the images chosen, so we applied a scaling factor depending on the number of bits of the image to adjust these errors.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132384897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236009
J. Avalos, Daniel Espinobarro, J. Velazquez, J. Sanchez
In this paper we present an implementation of a digital adaptive filter on the digital signal processor TMS320C6713, using a variant of the LMS algorithm, which consists in error codification, thus the speed of convergence is increased and the complexity of design for its implementation in digital adaptive filters is reduced, because the resulting codified error is composed of integer values. The LMS Algorithm with codified error (ECLMS), was tested in an environmental noise canceller and the results demonstrate an increase in the convergence speed, and a reduction of processing time.
{"title":"Adaptive noise canceller using LMS algorithm with codified error in a DSP","authors":"J. Avalos, Daniel Espinobarro, J. Velazquez, J. Sanchez","doi":"10.1109/MWSCAS.2009.5236009","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236009","url":null,"abstract":"In this paper we present an implementation of a digital adaptive filter on the digital signal processor TMS320C6713, using a variant of the LMS algorithm, which consists in error codification, thus the speed of convergence is increased and the complexity of design for its implementation in digital adaptive filters is reduced, because the resulting codified error is composed of integer values. The LMS Algorithm with codified error (ECLMS), was tested in an environmental noise canceller and the results demonstrate an increase in the convergence speed, and a reduction of processing time.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133845453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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