Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236006
Nourhan El Beheiry, M. E. Sharkawy, M. Lotfy, S. Elnoubi
Compressed video bitstream is sensitive to channel errors that may severely degrade the reconstructed pictures. Error concealment techniques implemented at decoders are effective approaches to reduce the impact of errors. They mask the effect of missing blocks by using the spatial or/and temporal correlation to create image or video of subjectively acceptable quality.
{"title":"An adaptive fast and efficient spatial error concealment technique for block-based video coding systems","authors":"Nourhan El Beheiry, M. E. Sharkawy, M. Lotfy, S. Elnoubi","doi":"10.1109/MWSCAS.2009.5236006","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236006","url":null,"abstract":"Compressed video bitstream is sensitive to channel errors that may severely degrade the reconstructed pictures. Error concealment techniques implemented at decoders are effective approaches to reduce the impact of errors. They mask the effect of missing blocks by using the spatial or/and temporal correlation to create image or video of subjectively acceptable quality.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"8 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116777242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235944
S. Subash, Md. Sajjad Rahaman, M. Chowdhury
In current literature various equivalent circuit models and reduction techniques have been demonstrated to study the behavior and performance of carbon nano tubes (CNTs). However, most of these methods are very complex and predominantly use SPICE/HSPICE simulations resulting in high computational time. This paper presents a compact modeling approach for CNT interconnects. Results both in the time domain and frequency domain are provided using a Fourier series approach for the analysis of CNT interconnects. The results obtained are compared against other conventional methods. The percentage error in delay for both single walled CNT (SWCNT) and multi-walled CNT (MWCNT) interconnects is found to be less than 5% and the percentage error in overshoot estimation for both types of CNTs is also under 8%.
{"title":"Compact model for carbon nanotubes interconnects using fourier series analysis","authors":"S. Subash, Md. Sajjad Rahaman, M. Chowdhury","doi":"10.1109/MWSCAS.2009.5235944","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235944","url":null,"abstract":"In current literature various equivalent circuit models and reduction techniques have been demonstrated to study the behavior and performance of carbon nano tubes (CNTs). However, most of these methods are very complex and predominantly use SPICE/HSPICE simulations resulting in high computational time. This paper presents a compact modeling approach for CNT interconnects. Results both in the time domain and frequency domain are provided using a Fourier series approach for the analysis of CNT interconnects. The results obtained are compared against other conventional methods. The percentage error in delay for both single walled CNT (SWCNT) and multi-walled CNT (MWCNT) interconnects is found to be less than 5% and the percentage error in overshoot estimation for both types of CNTs is also under 8%.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125638607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235990
O. Starostenko, R. Contreras Gomez, V. Alarcón-Aquino, O. Sergiyenko
This paper presents the analysis of emerging data exchange technologies used for integration of mobile devices to image-based learning process of second language. Particularly, the design of portable personal spaces providing mobile access to multimedia documents based on XML technologies and creation of generic interfaces for learning environments have been carried out. For image-based languages learning that implies the image processing, recognition, and retrieval Two Segment Turning function has been proposed and analyzed for possible adoption in applications assisted by mobile devices. The evaluation of designed prototype of image-based language learning system for interpretation of Japanese kanji and Mayan glyphs on mobile devices is discussed in this paper. Additionally the performance of proposed approaches used in content-based image retrieval is evaluated for their possible integration within mobile learning environments.
{"title":"CBIR for image-based language learning within mobile environment","authors":"O. Starostenko, R. Contreras Gomez, V. Alarcón-Aquino, O. Sergiyenko","doi":"10.1109/MWSCAS.2009.5235990","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235990","url":null,"abstract":"This paper presents the analysis of emerging data exchange technologies used for integration of mobile devices to image-based learning process of second language. Particularly, the design of portable personal spaces providing mobile access to multimedia documents based on XML technologies and creation of generic interfaces for learning environments have been carried out. For image-based languages learning that implies the image processing, recognition, and retrieval Two Segment Turning function has been proposed and analyzed for possible adoption in applications assisted by mobile devices. The evaluation of designed prototype of image-based language learning system for interpretation of Japanese kanji and Mayan glyphs on mobile devices is discussed in this paper. Additionally the performance of proposed approaches used in content-based image retrieval is evaluated for their possible integration within mobile learning environments.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131603262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236022
S. Vijay
In recent times, we have seen that shift-and-add operations have replaced multiplication for efficient hardware implementation to achieve reduction in hardware and power. Previously, researchers have proposed methods combining architectural transformations and shift-and-add decompositions for hardware optimizations. In this paper, a highly efficient common subexpression elimination (CSE) algorithm based on the binary representation of the system matrices to optimize the hardware requirements in linear Digital Signal Processing (DSP) synthesis is proposed. The algorithm chooses the maximum number of frequently occurring subexpressions to eliminate redundant computations and hence reduces the number of adders required to implement the multiplications in the state space model. Design examples of systems show that the proposed method offers a hardware reduction of around 22% over the previously best known method [11].
{"title":"Low-complexity implementation of state-space structures in linear DSP synthesis","authors":"S. Vijay","doi":"10.1109/MWSCAS.2009.5236022","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236022","url":null,"abstract":"In recent times, we have seen that shift-and-add operations have replaced multiplication for efficient hardware implementation to achieve reduction in hardware and power. Previously, researchers have proposed methods combining architectural transformations and shift-and-add decompositions for hardware optimizations. In this paper, a highly efficient common subexpression elimination (CSE) algorithm based on the binary representation of the system matrices to optimize the hardware requirements in linear Digital Signal Processing (DSP) synthesis is proposed. The algorithm chooses the maximum number of frequently occurring subexpressions to eliminate redundant computations and hence reduces the number of adders required to implement the multiplications in the state space model. Design examples of systems show that the proposed method offers a hardware reduction of around 22% over the previously best known method [11].","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132931064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236120
W. Kao, Chih-Chao Wei, Jen-Jui Liu, Pei-Yung Hsiao
Skilled cardiologists probe heart sounds by electronic stethoscope through human ears, but interpretation of heart sounds is a very special skill which is quite difficult to teach in a structured way. Because of this reason, automatic heart sound analysis in computer systems would be very helpful for medical staff. This paper presents a complete heart sound analysis system covering from the segmentation of beat cycles to the final determination of heart conditions. The kernels of heart beat cycle segmentation and recognition are based on autocorrelation, short-time Fourier transform, and support vector machines. The experiments are done by a public heart sound database released by Texas Heart Institute. A very promising recognition rate has been achieved.
{"title":"Automatic heart sound analysis with short-time Fourier transform and support vector machines","authors":"W. Kao, Chih-Chao Wei, Jen-Jui Liu, Pei-Yung Hsiao","doi":"10.1109/MWSCAS.2009.5236120","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236120","url":null,"abstract":"Skilled cardiologists probe heart sounds by electronic stethoscope through human ears, but interpretation of heart sounds is a very special skill which is quite difficult to teach in a structured way. Because of this reason, automatic heart sound analysis in computer systems would be very helpful for medical staff. This paper presents a complete heart sound analysis system covering from the segmentation of beat cycles to the final determination of heart conditions. The kernels of heart beat cycle segmentation and recognition are based on autocorrelation, short-time Fourier transform, and support vector machines. The experiments are done by a public heart sound database released by Texas Heart Institute. A very promising recognition rate has been achieved.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"365 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114057167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236074
K. Layton, D. Comer
A pipelined analog to digital converter (ADC) architecture is introduced for VT +2Vdsat supply voltage operation. The pipeline stage amplifier uses an active bootstrapped gain enhancement technique to produce greater than 70dB of gain in a single stage amplifier without a full cascode to maximize output swing. Low-voltage sampling is achieved with reset-amplifier based switching. The pipeline architecture is used to design and implement a 10-bit fully differential ADC in an 0.35µ CMOS process. The fabricated ADC achieves greater than 9 effective number of bits (ENOB) at supply voltages as low as 0.64V with a process VT + 2Vdsat of 0.85V by using a bulk-source driven threshold lowering technique. The converter achieves 8.84 ENOB at sampling rates as high as 1MSPS with a 0.875V supply voltage.
{"title":"A pipelined ADC architecture for low-voltage CMOS applications","authors":"K. Layton, D. Comer","doi":"10.1109/MWSCAS.2009.5236074","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236074","url":null,"abstract":"A pipelined analog to digital converter (ADC) architecture is introduced for VT +2Vdsat supply voltage operation. The pipeline stage amplifier uses an active bootstrapped gain enhancement technique to produce greater than 70dB of gain in a single stage amplifier without a full cascode to maximize output swing. Low-voltage sampling is achieved with reset-amplifier based switching. The pipeline architecture is used to design and implement a 10-bit fully differential ADC in an 0.35µ CMOS process. The fabricated ADC achieves greater than 9 effective number of bits (ENOB) at supply voltages as low as 0.64V with a process VT + 2Vdsat of 0.85V by using a bulk-source driven threshold lowering technique. The converter achieves 8.84 ENOB at sampling rates as high as 1MSPS with a 0.875V supply voltage.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114561116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236034
Yi-Jung Wang, Chih-Chi Chang, Guo-Zua Wu, O. Chen
During decoding the bit stream of a block, only a block type selecting from 4×4, 4×8, 8×4 and 8×8 is employed to do the inverse integer transform of VC-1. Accordingly, the hardware architectures of 4×4, 4×8, 8×4 and 8×8 inverse integer transforms can be integrated to reduce hardware cost. In this work, a low-complexity integrated hardware architecture is proposed to realize these four inverse integer transforms. First, the one-dimensional transform operations associated with 4 and 8 points are analyzed to find out the common parts. Second, the transform multiplications are decomposed into multiple additions and shifting operations due to the fixed transform coefficients. The one-dimensional transform architecture that integrates adders and shifters of 4-point and 8-point operations with multiplexers and registers is developed at a regular data-flow manner. Finally, four 4×4, two 4×8, two 8×4 and one 8x8 transforms can be individually computed in the proposed integrated one-dimensional transform architecture under 16 clock cycles. As compared to the conventional architecture which implements 4-point and 8-point inverse integer transforms separately, the proposed architecture consumes less hardware cost to accomplish the inverse integer transform(s) of a block at a specific throughput rate.
{"title":"Low-complexity integrated architecture of 4×4, 4×8, 8×4 and 8×8 inverse integer transforms of VC-1","authors":"Yi-Jung Wang, Chih-Chi Chang, Guo-Zua Wu, O. Chen","doi":"10.1109/MWSCAS.2009.5236034","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236034","url":null,"abstract":"During decoding the bit stream of a block, only a block type selecting from 4×4, 4×8, 8×4 and 8×8 is employed to do the inverse integer transform of VC-1. Accordingly, the hardware architectures of 4×4, 4×8, 8×4 and 8×8 inverse integer transforms can be integrated to reduce hardware cost. In this work, a low-complexity integrated hardware architecture is proposed to realize these four inverse integer transforms. First, the one-dimensional transform operations associated with 4 and 8 points are analyzed to find out the common parts. Second, the transform multiplications are decomposed into multiple additions and shifting operations due to the fixed transform coefficients. The one-dimensional transform architecture that integrates adders and shifters of 4-point and 8-point operations with multiplexers and registers is developed at a regular data-flow manner. Finally, four 4×4, two 4×8, two 8×4 and one 8x8 transforms can be individually computed in the proposed integrated one-dimensional transform architecture under 16 clock cycles. As compared to the conventional architecture which implements 4-point and 8-point inverse integer transforms separately, the proposed architecture consumes less hardware cost to accomplish the inverse integer transform(s) of a block at a specific throughput rate.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"33 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113981015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236134
S. Mahmoud
A new low voltage low power fully differential CMOS four-quadrant analog multiplier based on the operation of MOS transistors in saturation region is given. The proposed four-quadrant voltage-mode multiplier was confirmed by using PSPICE simulation and 0.25µm CMOS technology and found to have good linearity with wide input dynamic range. The static power consumption is 0.326 mW, the input voltage range is ±0.75 V from ±1V supply, the bandwidth is 16MHz at 1KΩ//10pF load, the output referred noise voltage is less than 10 nV/√Hz in 1KΩ, and the maximum linearity error is less than 1 % at ±0.5 V input voltage.
{"title":"Low voltage low power wide range fully differential CMOS four-quadrant analog multiplier","authors":"S. Mahmoud","doi":"10.1109/MWSCAS.2009.5236134","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236134","url":null,"abstract":"A new low voltage low power fully differential CMOS four-quadrant analog multiplier based on the operation of MOS transistors in saturation region is given. The proposed four-quadrant voltage-mode multiplier was confirmed by using PSPICE simulation and 0.25µm CMOS technology and found to have good linearity with wide input dynamic range. The static power consumption is 0.326 mW, the input voltage range is ±0.75 V from ±1V supply, the bandwidth is 16MHz at 1KΩ//10pF load, the output referred noise voltage is less than 10 nV/√Hz in 1KΩ, and the maximum linearity error is less than 1 % at ±0.5 V input voltage.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123858343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236118
D. Robles-Camarillo, L. Nino-de-Rivera, H. Quiroz-Mercado, M. J. Lopez-Miranda
The present work proposes a portable electronic waveform generator for transcorneal electrical stimulation (TES). The waveform model is generated into a digital processor, and is based on a healthy eye's multi-focal electroretinogram (MF-ERG) response. The stimulation protocol proposed in this paper is qualitatively different from the one reported by others like Inomata et. al. [1, 2]. Results show an improvement in patient's visual acuity and increased electrical B wave response in standard electroretinogram (ERG) tests, when TES is applied in patients suffering low vision (LV) produced by central retinal artery occlusion (CRAO).
{"title":"Portable transcorneal electrical stimulator system, applied on electrotherapy for low vision patients","authors":"D. Robles-Camarillo, L. Nino-de-Rivera, H. Quiroz-Mercado, M. J. Lopez-Miranda","doi":"10.1109/MWSCAS.2009.5236118","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236118","url":null,"abstract":"The present work proposes a portable electronic waveform generator for transcorneal electrical stimulation (TES). The waveform model is generated into a digital processor, and is based on a healthy eye's multi-focal electroretinogram (MF-ERG) response. The stimulation protocol proposed in this paper is qualitatively different from the one reported by others like Inomata et. al. [1, 2]. Results show an improvement in patient's visual acuity and increased electrical B wave response in standard electroretinogram (ERG) tests, when TES is applied in patients suffering low vision (LV) produced by central retinal artery occlusion (CRAO).","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126284964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236080
H. San, Haruo Kobayashi
This paper proposes a new realization technique of image rejection function by noise-coupling architecture, which is used for a complex bandpass ΔΣAD modulator. The complex bandpass ΔΣAD modulator processes just input I and Q signals, not image signals, and the AD conversion can be realized with low power dissipation. It realizes an asymmetric noise-shaped spectra, which is desirable for such low-IF receiver applications. However, the performance of the complex bandpass ΔΣAD modulator suffers from the mismatch between internal analog I and Q paths. I/Q path mismatch causes an image signal, and the quantization noise of the mirror image band aliases into the desired signal band, which degrades the SQNDR (Signal to Quantization Noise and Distortion Ratio) of the modulator. In our proposed modulator architecture, an extra notch for image rejection is realized by noise-coupled topology. We just add some passive capacitors and switches to the modulator; the additional integrator circuit composed of an operation amplifier in the conventional image rejection realization is not necessary. Therefore, the performance of the complex modulator can be effectively raised without additional power dissipation. We have performed simulation with MATLAB to confirm the validity of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of image-rejection effectively, and improve the SQNDR of the complex bandpass ΔΣAD modulator.
针对复杂带通ΔΣAD调制器，提出了一种利用噪声耦合结构实现图像抑制函数的新技术。复杂带通ΔΣAD调制器只处理输入I和Q信号，不处理图像信号，可以以低功耗实现AD转换。它实现了非对称噪声形光谱，这是这种低中频接收器应用所需要的。然而，复杂带通ΔΣAD调制器的性能受到内部模拟I和Q路径不匹配的影响。I/Q路径失配导致图像信号，镜像频带的量化噪声混叠到期望的信号频带，降低了调制器的SQNDR (signal to quanti量化噪声和失真比)。在我们提出的调制器结构中，一个额外的陷波是通过噪声耦合拓扑来实现的。我们只是在调制器中加入一些无源电容器和开关;在传统的图像抑制实现中，不需要额外的由运算放大器组成的积分器电路。因此，可以有效地提高复合调制器的性能，而无需额外的功耗。我们用MATLAB进行了仿真，以验证所提出架构的有效性。仿真结果表明，该结构能够有效地实现图像抑制，提高了复杂带通ΔΣAD调制器的SQNDR。
{"title":"Complex bandpass ΔΣAD modulator with noise-coupled image rejection","authors":"H. San, Haruo Kobayashi","doi":"10.1109/MWSCAS.2009.5236080","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236080","url":null,"abstract":"This paper proposes a new realization technique of image rejection function by noise-coupling architecture, which is used for a complex bandpass ΔΣAD modulator. The complex bandpass ΔΣAD modulator processes just input I and Q signals, not image signals, and the AD conversion can be realized with low power dissipation. It realizes an asymmetric noise-shaped spectra, which is desirable for such low-IF receiver applications. However, the performance of the complex bandpass ΔΣAD modulator suffers from the mismatch between internal analog I and Q paths. I/Q path mismatch causes an image signal, and the quantization noise of the mirror image band aliases into the desired signal band, which degrades the SQNDR (Signal to Quantization Noise and Distortion Ratio) of the modulator. In our proposed modulator architecture, an extra notch for image rejection is realized by noise-coupled topology. We just add some passive capacitors and switches to the modulator; the additional integrator circuit composed of an operation amplifier in the conventional image rejection realization is not necessary. Therefore, the performance of the complex modulator can be effectively raised without additional power dissipation. We have performed simulation with MATLAB to confirm the validity of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of image-rejection effectively, and improve the SQNDR of the complex bandpass ΔΣAD modulator.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125892792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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