Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236119
Fan Xiong, N. Rafla
This paper focuses on the application of Virtual Reconfigurable Circuit (VRC) design methodology and intrinsic evolution for the design of small sequential circuits and their implementation on a single programmable chip with an embedded hardcore processor. The evolutionary algorithm is developed in software that runs on the embedded processor. Fitness function is calculated using hardware architecture and is used to guide the evolution process. This new method is applied to the development of a 3-bit sequence detector and the evolved architecture is implemented on a Xilinxtm Virtex-II pro device. Simulations were run on the evolved architecture and on the same circuit designed using conventional Hardware Descriptive Language (HDL). Both designs showed the same functional behavior. Synthesis results show that the new method can be used in successfully implementing small sequential circuits on a reconfigurable hardware environment.
{"title":"On-chip intrinsic evolution methodology for sequential logic circuit design","authors":"Fan Xiong, N. Rafla","doi":"10.1109/MWSCAS.2009.5236119","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236119","url":null,"abstract":"This paper focuses on the application of Virtual Reconfigurable Circuit (VRC) design methodology and intrinsic evolution for the design of small sequential circuits and their implementation on a single programmable chip with an embedded hardcore processor. The evolutionary algorithm is developed in software that runs on the embedded processor. Fitness function is calculated using hardware architecture and is used to guide the evolution process. This new method is applied to the development of a 3-bit sequence detector and the evolved architecture is implemented on a Xilinxtm Virtex-II pro device. Simulations were run on the evolved architecture and on the same circuit designed using conventional Hardware Descriptive Language (HDL). Both designs showed the same functional behavior. Synthesis results show that the new method can be used in successfully implementing small sequential circuits on a reconfigurable hardware environment.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127287242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235948
Swaran R. Singh, K. Moez
Wireless sensor networks are emerging as a compelling solution for a diverse range of data gathering applications. The constituent sensor nodes in these networks typically run on unreplenishable battery supplies, thereby placing energy at a premium. Ultra-low power content addressable memory is required to implement the routing caches for many network protocols used in wireless sensor networks. This paper investigates several circuit techniques for reducing leakage currents in content addressable memories on a 90nm process. Simulations show that leakage currents in a 4kbit memory array can by reduced by a factor of 168x relative to a conventional, unoptimized design.
{"title":"Ultra low leakage 90nm content addressable memory design for wireless sensor network applications","authors":"Swaran R. Singh, K. Moez","doi":"10.1109/MWSCAS.2009.5235948","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235948","url":null,"abstract":"Wireless sensor networks are emerging as a compelling solution for a diverse range of data gathering applications. The constituent sensor nodes in these networks typically run on unreplenishable battery supplies, thereby placing energy at a premium. Ultra-low power content addressable memory is required to implement the routing caches for many network protocols used in wireless sensor networks. This paper investigates several circuit techniques for reducing leakage currents in content addressable memories on a 90nm process. Simulations show that leakage currents in a 4kbit memory array can by reduced by a factor of 168x relative to a conventional, unoptimized design.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127400425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236071
Bibhudatta Sahoo, B. Razavi
A simulator for comprehensive analysis of pipelined A/D converters has been developed in MATLAB and compiled to an executable that can be run on various platforms. The simulator accepts user-specified parameters such as resolution per stage, number of stages, input and clock frequencies, input amplitude, op amp nonlinearity, capacitor mismatch, comparator offset, and clock jitter. The tool then provides the simulated performance in the form of residue plots, differential and integral nonlinearity profiles, output spectrum, and input-referred thermal noise. Compared with Cadence's Spectre, the proposed simulator runs several orders of magnitude faster while incurring a small error.
{"title":"A fast simulator for pipelined A/D converters","authors":"Bibhudatta Sahoo, B. Razavi","doi":"10.1109/MWSCAS.2009.5236071","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236071","url":null,"abstract":"A simulator for comprehensive analysis of pipelined A/D converters has been developed in MATLAB and compiled to an executable that can be run on various platforms. The simulator accepts user-specified parameters such as resolution per stage, number of stages, input and clock frequencies, input amplitude, op amp nonlinearity, capacitor mismatch, comparator offset, and clock jitter. The tool then provides the simulated performance in the form of residue plots, differential and integral nonlinearity profiles, output spectrum, and input-referred thermal noise. Compared with Cadence's Spectre, the proposed simulator runs several orders of magnitude faster while incurring a small error.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127234262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235902
Á. Miranda, F. A. Serrano, R. Vázquez-Medina, M. Cruz‐Irisson
A semi-empirical nearest-neighbor tight-binding approach, that reproduces the indirect band gaps of Si and Ge crystalline, has been applied to study the electronic band dispersion relation of Si and Ge nanowires (NWs). The NWs are modeling by free standing, infinitely long and homogeneous NWs cross sections with the wire axis along the zaxis. The calculations show that Si NWs keeps the indirect bandgap while Ge NWs changes into the direct bandgap when the wire cross-section becomes smaller. Also, the band gap enhancement of Si NWs showing to quantum confinement effects is generally larger than that of similar-sized Ge NWs, confirming the larger quantum confinement effects in Si than in Ge when they are confined in two dimensions.
{"title":"Nanoelectronic properties of Si and Ge: A semi-empirical approximation","authors":"Á. Miranda, F. A. Serrano, R. Vázquez-Medina, M. Cruz‐Irisson","doi":"10.1109/MWSCAS.2009.5235902","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235902","url":null,"abstract":"A semi-empirical nearest-neighbor tight-binding approach, that reproduces the indirect band gaps of Si and Ge crystalline, has been applied to study the electronic band dispersion relation of Si and Ge nanowires (NWs). The NWs are modeling by free standing, infinitely long and homogeneous NWs cross sections with the wire axis along the zaxis. The calculations show that Si NWs keeps the indirect bandgap while Ge NWs changes into the direct bandgap when the wire cross-section becomes smaller. Also, the band gap enhancement of Si NWs showing to quantum confinement effects is generally larger than that of similar-sized Ge NWs, confirming the larger quantum confinement effects in Si than in Ge when they are confined in two dimensions.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132970435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236069
V. Saxena, Kaijun Li, Geng Zheng, R. J. Baker
As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents, and additional mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in these small processes the K-Delta-1- Sigma (KD1S) modulator-based ADC was proposed. The KD1S topology employs inherent time-interleaving with a shared opamp and K-quantizing paths and can achieve significantly higher conversion bandwidths when compared to the traditional delta-sigma ADCs. The 8-path KD1S modulator achieves an SNR of 58 dB (or 9.4-bits resolution) when clocked at 100 MHz for a conversion bandwidth of 6.25 MHz and an effective sampling rate equal to 800 MHz. The KD1S modulator has been fabricated in a 500 nm CMOS process and the experimental results are reported. Deficiencies in the first test chip performance are discussed along with their alleviation to achieve theoretical performance.
{"title":"A K-Delta-1-Sigma modulator for wideband analog to digital conversion","authors":"V. Saxena, Kaijun Li, Geng Zheng, R. J. Baker","doi":"10.1109/MWSCAS.2009.5236069","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236069","url":null,"abstract":"As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents, and additional mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in these small processes the K-Delta-1- Sigma (KD1S) modulator-based ADC was proposed. The KD1S topology employs inherent time-interleaving with a shared opamp and K-quantizing paths and can achieve significantly higher conversion bandwidths when compared to the traditional delta-sigma ADCs. The 8-path KD1S modulator achieves an SNR of 58 dB (or 9.4-bits resolution) when clocked at 100 MHz for a conversion bandwidth of 6.25 MHz and an effective sampling rate equal to 800 MHz. The KD1S modulator has been fabricated in a 500 nm CMOS process and the experimental results are reported. Deficiencies in the first test chip performance are discussed along with their alleviation to achieve theoretical performance.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132100739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236039
Meng-chou Chang, C. Tsai
This paper proposes a novel handshaking quasi-adiabatic logic (HQAL) circuit, which combines the advantages of adiabatic logics with those of asynchronous circuits. A HQAL circuit is composed of adiabatic logic blocks and the handshake control chain (HCC). The power of the adiabatic logic blocks in HQAL is controlled and supplied by the HCC, and the logic blocks in HQAL become active only when performing useful computations. With the handshake control chain, the HQAL circuit can avoid the problem of data token overriding, which may occur in conventional asynchronous adiabatic logic (AAL) circuits. Simulation results showed that the HQAL implementation of a pipelined Sklansky adder can achieve 33.1% reduction in power dissipation, compared to the CMOS implementation, for a data rate of 700 MHz and 72.5% reduction in power dissipation for a data rate of 10 MHz.
{"title":"Handshaking quasi-adiabatic logic","authors":"Meng-chou Chang, C. Tsai","doi":"10.1109/MWSCAS.2009.5236039","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236039","url":null,"abstract":"This paper proposes a novel handshaking quasi-adiabatic logic (HQAL) circuit, which combines the advantages of adiabatic logics with those of asynchronous circuits. A HQAL circuit is composed of adiabatic logic blocks and the handshake control chain (HCC). The power of the adiabatic logic blocks in HQAL is controlled and supplied by the HCC, and the logic blocks in HQAL become active only when performing useful computations. With the handshake control chain, the HQAL circuit can avoid the problem of data token overriding, which may occur in conventional asynchronous adiabatic logic (AAL) circuits. Simulation results showed that the HQAL implementation of a pipelined Sklansky adder can achieve 33.1% reduction in power dissipation, compared to the CMOS implementation, for a data rate of 700 MHz and 72.5% reduction in power dissipation for a data rate of 10 MHz.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126817052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235885
Christiane Leuer, K. Ochs
Finding an appropriate reference circuit, is an integral part of numerical integration using wave digital (WD) concepts. We show an approach for the systematic derivation of a canonical internally passive electrical circuit from a class of linear partial differential equations (PDEs). We present two methods to transform this circuit into a reference circuit, having a one-to-one corresponding wave digital structure. As an example, we deduce a reference circuit for a wave digital algorithm from Maxwell's equations and depict simulation results.
{"title":"Systematic derivation of reference circuits for wave digital modeling of passive linear partial differential equations","authors":"Christiane Leuer, K. Ochs","doi":"10.1109/MWSCAS.2009.5235885","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235885","url":null,"abstract":"Finding an appropriate reference circuit, is an integral part of numerical integration using wave digital (WD) concepts. We show an approach for the systematic derivation of a canonical internally passive electrical circuit from a class of linear partial differential equations (PDEs). We present two methods to transform this circuit into a reference circuit, having a one-to-one corresponding wave digital structure. As an example, we deduce a reference circuit for a wave digital algorithm from Maxwell's equations and depict simulation results.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122453881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235958
C. Villalobos, J. A. Reyes, J. C. S. Garcia
In this paper we present an implementation of the LMS (Least Mean Square), NLMS (Normalized Least Mean Square) and other LMS based algorithms on the DSK (DSP Starters Kit) TMS320C6713 with the intention to compare their performance. We obtained the time and frequency behaviour, and the processing speed of the analyzed algorithms. The objective of the NLMS algorithm is to obtain the best convergence factor considering the input signal power in order to improve the filter convergence time. The obtained results show that the NLMS has better performance than the LMS, unfortunately, the computational complexity increase which means more processing time.
{"title":"Implementation and analysis of the NLMS algorithm on TMS320C6713 DSP","authors":"C. Villalobos, J. A. Reyes, J. C. S. Garcia","doi":"10.1109/MWSCAS.2009.5235958","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235958","url":null,"abstract":"In this paper we present an implementation of the LMS (Least Mean Square), NLMS (Normalized Least Mean Square) and other LMS based algorithms on the DSK (DSP Starters Kit) TMS320C6713 with the intention to compare their performance. We obtained the time and frequency behaviour, and the processing speed of the analyzed algorithms. The objective of the NLMS algorithm is to obtain the best convergence factor considering the input signal power in order to improve the filter convergence time. The obtained results show that the NLMS has better performance than the LMS, unfortunately, the computational complexity increase which means more processing time.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126090201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235890
Xiong Liu, A. Willson
To address the problem of current source output impedance degradation in a large full-scale sub-ranging ADC's reference ladder, a feedback closed-loop negative supply system, occupying 0.028 mm2 in 0.18-µm CMOS, is proposed. This system can be applied to overcome headroom issues in other high-performance large-dynamic-range analog circuits such as large input swing continuous-time filters, analog amplifiers, buffers and analog precision control loops. With a more than 40% power efficient core and a small on-chip 16-pF MOS capacitor, this architecture provides a power and area efficient solution. Supporting up to a 400-µA current, the system generates a −0.7 V output with less than 5-mV ripple, which can easily be suppressed by more than 40 dB by a linear regulator.
{"title":"A CMOS negative supply for large dynamic range high-bandwidth analog circuits","authors":"Xiong Liu, A. Willson","doi":"10.1109/MWSCAS.2009.5235890","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235890","url":null,"abstract":"To address the problem of current source output impedance degradation in a large full-scale sub-ranging ADC's reference ladder, a feedback closed-loop negative supply system, occupying 0.028 mm2 in 0.18-µm CMOS, is proposed. This system can be applied to overcome headroom issues in other high-performance large-dynamic-range analog circuits such as large input swing continuous-time filters, analog amplifiers, buffers and analog precision control loops. With a more than 40% power efficient core and a small on-chip 16-pF MOS capacitor, this architecture provides a power and area efficient solution. Supporting up to a 400-µA current, the system generates a −0.7 V output with less than 5-mV ripple, which can easily be suppressed by more than 40 dB by a linear regulator.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113953872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235898
M. González-Lee, C. Santiago-Avila, M. Nakano-Miyatake, H. Perez-Meana
In almost all document authentication systems based on watermarking technique, the document is considered as a binary image and a watermark signal is embedded into it. However, actually an important document is saved in Document Description (DD) file, such as Portable Document Format (PDF) file, instead of the image file. Because generally DD file is more compact in size than image files, and the content of the document is not easy to be modified. However, recently some computer tools permit user to modify the contents of DD file, which brings a necessity to develop an efficient document authentication scheme. Considering it, in the proposed scheme, a watermark sequence is directly embedded into the DD file (Script file), modifying metrics of each characters of it. The experimental results show very good performance in the document authentication. Also the computer complexity of the proposed scheme is sufficiently low to apply in the practical situation.
{"title":"Watermarking based document authentication in Script format","authors":"M. González-Lee, C. Santiago-Avila, M. Nakano-Miyatake, H. Perez-Meana","doi":"10.1109/MWSCAS.2009.5235898","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235898","url":null,"abstract":"In almost all document authentication systems based on watermarking technique, the document is considered as a binary image and a watermark signal is embedded into it. However, actually an important document is saved in Document Description (DD) file, such as Portable Document Format (PDF) file, instead of the image file. Because generally DD file is more compact in size than image files, and the content of the document is not easy to be modified. However, recently some computer tools permit user to modify the contents of DD file, which brings a necessity to develop an efficient document authentication scheme. Considering it, in the proposed scheme, a watermark sequence is directly embedded into the DD file (Script file), modifying metrics of each characters of it. The experimental results show very good performance in the document authentication. Also the computer complexity of the proposed scheme is sufficiently low to apply in the practical situation.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124950034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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