Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235946
S. Amarchinta, H. Kanitkar, D. Kudithipudi
Digital subthreshold circuits are gaining importance because of their ability to serve as an ideal low power solution. In this paper, a methodology to design a performance enhanced subthreshold standard cell library robust to process variations is discussed. Several approaches to design a performance enhanced cell library are discussed and an optimal design choice is made with energy-delay product as a metric. Significant performance improvements of 2X, 8X and 1.5X are achieved for inverter, AND, and OR cells respectively over regular cell library. The variation in delay for the proposed standard cell library with respect to four process corners is studied. A significant reduction of about 75.6% in delay variation across worst case process corners was observed when a normal inverter and inverter from the high performance cell library were simulated.
{"title":"Robust and high performance subthreshold standard cell design","authors":"S. Amarchinta, H. Kanitkar, D. Kudithipudi","doi":"10.1109/MWSCAS.2009.5235946","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235946","url":null,"abstract":"Digital subthreshold circuits are gaining importance because of their ability to serve as an ideal low power solution. In this paper, a methodology to design a performance enhanced subthreshold standard cell library robust to process variations is discussed. Several approaches to design a performance enhanced cell library are discussed and an optimal design choice is made with energy-delay product as a metric. Significant performance improvements of 2X, 8X and 1.5X are achieved for inverter, AND, and OR cells respectively over regular cell library. The variation in delay for the proposed standard cell library with respect to four process corners is studied. A significant reduction of about 75.6% in delay variation across worst case process corners was observed when a normal inverter and inverter from the high performance cell library were simulated.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132244274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236020
V. Golikov, O. Lebedeva, F.J. Miguel Reyes
We investigated the robustness of the linear detector operating in a Gaussian environment in the presence of a mismatch between the design interference covariance matrix and the actual one. We have suggested that the Gaussian environment consists of a known colored clutter, a white noise and a strong unwanted periodical signal with unknown nonstationary power. It has been obtained the asymptotic inverse covariance matrix of the interference when the unwanted signal power tends to infinite. Using this formula we developed the asymptotic likelihood-ratio test (LRT). The performance of the new test statistic is analyzed and compared with well known optimal detector. The effect of the unwanted signal removing on the performance is evaluated for an example scenario.
{"title":"A robust detection in the presence of a strong unwanted periodical signal with unknown nonstationary power","authors":"V. Golikov, O. Lebedeva, F.J. Miguel Reyes","doi":"10.1109/MWSCAS.2009.5236020","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236020","url":null,"abstract":"We investigated the robustness of the linear detector operating in a Gaussian environment in the presence of a mismatch between the design interference covariance matrix and the actual one. We have suggested that the Gaussian environment consists of a known colored clutter, a white noise and a strong unwanted periodical signal with unknown nonstationary power. It has been obtained the asymptotic inverse covariance matrix of the interference when the unwanted signal power tends to infinite. Using this formula we developed the asymptotic likelihood-ratio test (LRT). The performance of the new test statistic is analyzed and compared with well known optimal detector. The effect of the unwanted signal removing on the performance is evaluated for an example scenario.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132810355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235993
J. A. Hernández, F. G. Castañeda, J. Cadenas
Edge detection is an important preprocessing task in artificial vision systems. In this paper the utility of a recently reported CNN template for edge detection was verified over a set of black and white images. These images were obtained applying an threshold procedure to their corresponding associated gray level images. An optimal threshold value for preserving a large number of features from the original gray level input images was used. Combining the threshold and edge detection templates, a procedure to obtain edges on gray level images was implemented.
{"title":"A method for edge detection in gray level images, based on cellular neural networks","authors":"J. A. Hernández, F. G. Castañeda, J. Cadenas","doi":"10.1109/MWSCAS.2009.5235993","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235993","url":null,"abstract":"Edge detection is an important preprocessing task in artificial vision systems. In this paper the utility of a recently reported CNN template for edge detection was verified over a set of black and white images. These images were obtained applying an threshold procedure to their corresponding associated gray level images. An optimal threshold value for preserving a large number of features from the original gray level input images was used. Combining the threshold and edge detection templates, a procedure to obtain edges on gray level images was implemented.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117001523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236038
Jin-Hua Hong, Wei-Chung Wu
In this paper, we propose an elliptic curve cryptographic (ECC) architecture for a lower hardware resource. In our work, the different paths of encryption and decryption could be chosen, and the elliptic curve (EC) is based on GF (2163). The EC scalar multiplication is a main operation module that includes add, Montgomery multiplier and inverse in ECC architecture. All modules are organized in a hierarchical structure according to their complexity. In the hardware implementations using a 0.18µ m TSMC cell library, a 69 K gate count is possessed, and the maximum speed is 181 MHz. The EC multiplication time is from 1.26 ms to 2.52 ms. The private key k is a 163-bit random number. If the private key k is chosen to be a small one, the EC multiplication time would be faster.
{"title":"The design of high performance elliptic curve cryptographic","authors":"Jin-Hua Hong, Wei-Chung Wu","doi":"10.1109/MWSCAS.2009.5236038","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236038","url":null,"abstract":"In this paper, we propose an elliptic curve cryptographic (ECC) architecture for a lower hardware resource. In our work, the different paths of encryption and decryption could be chosen, and the elliptic curve (EC) is based on GF (2163). The EC scalar multiplication is a main operation module that includes add, Montgomery multiplier and inverse in ECC architecture. All modules are organized in a hierarchical structure according to their complexity. In the hardware implementations using a 0.18µ m TSMC cell library, a 69 K gate count is possessed, and the maximum speed is 181 MHz. The EC multiplication time is from 1.26 ms to 2.52 ms. The private key k is a 163-bit random number. If the private key k is chosen to be a small one, the EC multiplication time would be faster.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124099742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236074
K. Layton, D. Comer
A pipelined analog to digital converter (ADC) architecture is introduced for VT +2Vdsat supply voltage operation. The pipeline stage amplifier uses an active bootstrapped gain enhancement technique to produce greater than 70dB of gain in a single stage amplifier without a full cascode to maximize output swing. Low-voltage sampling is achieved with reset-amplifier based switching. The pipeline architecture is used to design and implement a 10-bit fully differential ADC in an 0.35µ CMOS process. The fabricated ADC achieves greater than 9 effective number of bits (ENOB) at supply voltages as low as 0.64V with a process VT + 2Vdsat of 0.85V by using a bulk-source driven threshold lowering technique. The converter achieves 8.84 ENOB at sampling rates as high as 1MSPS with a 0.875V supply voltage.
{"title":"A pipelined ADC architecture for low-voltage CMOS applications","authors":"K. Layton, D. Comer","doi":"10.1109/MWSCAS.2009.5236074","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236074","url":null,"abstract":"A pipelined analog to digital converter (ADC) architecture is introduced for VT +2Vdsat supply voltage operation. The pipeline stage amplifier uses an active bootstrapped gain enhancement technique to produce greater than 70dB of gain in a single stage amplifier without a full cascode to maximize output swing. Low-voltage sampling is achieved with reset-amplifier based switching. The pipeline architecture is used to design and implement a 10-bit fully differential ADC in an 0.35µ CMOS process. The fabricated ADC achieves greater than 9 effective number of bits (ENOB) at supply voltages as low as 0.64V with a process VT + 2Vdsat of 0.85V by using a bulk-source driven threshold lowering technique. The converter achieves 8.84 ENOB at sampling rates as high as 1MSPS with a 0.875V supply voltage.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114561116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236134
S. Mahmoud
A new low voltage low power fully differential CMOS four-quadrant analog multiplier based on the operation of MOS transistors in saturation region is given. The proposed four-quadrant voltage-mode multiplier was confirmed by using PSPICE simulation and 0.25µm CMOS technology and found to have good linearity with wide input dynamic range. The static power consumption is 0.326 mW, the input voltage range is ±0.75 V from ±1V supply, the bandwidth is 16MHz at 1KΩ//10pF load, the output referred noise voltage is less than 10 nV/√Hz in 1KΩ, and the maximum linearity error is less than 1 % at ±0.5 V input voltage.
{"title":"Low voltage low power wide range fully differential CMOS four-quadrant analog multiplier","authors":"S. Mahmoud","doi":"10.1109/MWSCAS.2009.5236134","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236134","url":null,"abstract":"A new low voltage low power fully differential CMOS four-quadrant analog multiplier based on the operation of MOS transistors in saturation region is given. The proposed four-quadrant voltage-mode multiplier was confirmed by using PSPICE simulation and 0.25µm CMOS technology and found to have good linearity with wide input dynamic range. The static power consumption is 0.326 mW, the input voltage range is ±0.75 V from ±1V supply, the bandwidth is 16MHz at 1KΩ//10pF load, the output referred noise voltage is less than 10 nV/√Hz in 1KΩ, and the maximum linearity error is less than 1 % at ±0.5 V input voltage.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123858343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236091
E. G. Hernández-Martínez, E. Aranda-Bricaire
This paper presents a comparison between two non-collision strategies for multi-agent robots formations. The control objective is to coordinate a group of agents, considered as unicycle-type robots, to achieve desired inter-agent distances avoiding collisions. The formation strategy is based on the cyclic pursuit configuration where every agent can detect another agent only. The first non-collision strategy is the standard methodology of repulsive forces obtained as the gradient of Repulsive Potential Functions. The second strategy is a novel Repulsive Vector Field based on a scaled unstable focus. The comparison is carried out both by numerical simulations and over an experimental set-up consisting of three unicycle-type robots.
{"title":"Experimental comparison of non-collision strategies in multi-agent robots formation control","authors":"E. G. Hernández-Martínez, E. Aranda-Bricaire","doi":"10.1109/MWSCAS.2009.5236091","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236091","url":null,"abstract":"This paper presents a comparison between two non-collision strategies for multi-agent robots formations. The control objective is to coordinate a group of agents, considered as unicycle-type robots, to achieve desired inter-agent distances avoiding collisions. The formation strategy is based on the cyclic pursuit configuration where every agent can detect another agent only. The first non-collision strategy is the standard methodology of repulsive forces obtained as the gradient of Repulsive Potential Functions. The second strategy is a novel Repulsive Vector Field based on a scaled unstable focus. The comparison is carried out both by numerical simulations and over an experimental set-up consisting of three unicycle-type robots.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128374189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236058
George V. Leming, Kundan Nepal
As technology scales and the geometries of the transistors shrink, leakage current and subsequently total power consumption increase considerably. Many of the benefits brought forth by the smaller transistors will be lost if the high power consumption problem cannot be solved. The leakage power consumption problem is especially relevant to an FPGA because of the amount of unused interconnect and logic fabric in the chip during any operation. In this paper, we propose to lower the power consumption of a standard SRAM based FPGA by using half-width transistor stacks and adaptive body biasing techniques. SPICE simulation on a standard pass-transistor based switch block and a switch matrix from the Xilinx XC4000 FPGA show that the leakage power can be reduced by up to 46% for a 45nm technology node and up to 10% for a 70nm technology node when a switch-matrix is fully loaded.
{"title":"Low-power FPGA routing switches using adaptive body biasing technique","authors":"George V. Leming, Kundan Nepal","doi":"10.1109/MWSCAS.2009.5236058","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236058","url":null,"abstract":"As technology scales and the geometries of the transistors shrink, leakage current and subsequently total power consumption increase considerably. Many of the benefits brought forth by the smaller transistors will be lost if the high power consumption problem cannot be solved. The leakage power consumption problem is especially relevant to an FPGA because of the amount of unused interconnect and logic fabric in the chip during any operation. In this paper, we propose to lower the power consumption of a standard SRAM based FPGA by using half-width transistor stacks and adaptive body biasing techniques. SPICE simulation on a standard pass-transistor based switch block and a switch matrix from the Xilinx XC4000 FPGA show that the leakage power can be reduced by up to 46% for a 45nm technology node and up to 10% for a 70nm technology node when a switch-matrix is fully loaded.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128391369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236158
A. Tekin, H. Elwan, S. Mahmoud, K. Pedrotti
In this paper, a new technique for realizing area efficient, low noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the pass band of the filter. This is illustrated by implementing a 5th-order noise-shaped post mixer gain-filtering circuit in a 65-nm CMOS process. The proposed circuits consume 4.8 mA from a 1.2-V supply with an in-band noise density of 12 nV/sqrt(Hz) and an IIP3 of 25.5 dBm. The design provides 50 dB filtering for the adjacent blockers of the target Digital Video Broadcast-Handheld (DVB-H) receiver. The gain of the stage is programmable in 6-dB steps without altering the filter response.
{"title":"A 12nV/√Hz noise-shaped channel select filter for DVB-H mobile-TV tuners","authors":"A. Tekin, H. Elwan, S. Mahmoud, K. Pedrotti","doi":"10.1109/MWSCAS.2009.5236158","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236158","url":null,"abstract":"In this paper, a new technique for realizing area efficient, low noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the pass band of the filter. This is illustrated by implementing a 5th-order noise-shaped post mixer gain-filtering circuit in a 65-nm CMOS process. The proposed circuits consume 4.8 mA from a 1.2-V supply with an in-band noise density of 12 nV/sqrt(Hz) and an IIP3 of 25.5 dBm. The design provides 50 dB filtering for the adjacent blockers of the target Digital Video Broadcast-Handheld (DVB-H) receiver. The gain of the stage is programmable in 6-dB steps without altering the filter response.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128489384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235986
P. G. López, J. C. Quezada, A. L. Chau
The Concurrent Real-Time Tasks (TTRC), carry out all the activities of a System in Real-Time (STR); the Scheduler of Concurrent Real-Time Tasks (PTTRC) is the responsible of selecting the Real Time Task and the moment that it will take the resources, (PTTRC) is an algorithm that assigns the resources from the processor to different tasks in different moments. However, is necessary to verify effectiveness of the algorithm using an adequate approach that provides a metric between 0 and 1; the measuring should be carried out in local form and in a global way. In this work we intend the measuring of the efficiency of the scheduler through of the evolution of the instances of the Concurrent Tasks and their temporary restrictions.
{"title":"A metric for the evaluation of the efficiency in Scheduler of Concurrent Real-Time Tasks","authors":"P. G. López, J. C. Quezada, A. L. Chau","doi":"10.1109/MWSCAS.2009.5235986","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235986","url":null,"abstract":"The Concurrent Real-Time Tasks (TTRC), carry out all the activities of a System in Real-Time (STR); the Scheduler of Concurrent Real-Time Tasks (PTTRC) is the responsible of selecting the Real Time Task and the moment that it will take the resources, (PTTRC) is an algorithm that assigns the resources from the processor to different tasks in different moments. However, is necessary to verify effectiveness of the algorithm using an adequate approach that provides a metric between 0 and 1; the measuring should be carried out in local form and in a global way. In this work we intend the measuring of the efficiency of the scheduler through of the evolution of the instances of the Concurrent Tasks and their temporary restrictions.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128505245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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