Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236058
George V. Leming, Kundan Nepal
As technology scales and the geometries of the transistors shrink, leakage current and subsequently total power consumption increase considerably. Many of the benefits brought forth by the smaller transistors will be lost if the high power consumption problem cannot be solved. The leakage power consumption problem is especially relevant to an FPGA because of the amount of unused interconnect and logic fabric in the chip during any operation. In this paper, we propose to lower the power consumption of a standard SRAM based FPGA by using half-width transistor stacks and adaptive body biasing techniques. SPICE simulation on a standard pass-transistor based switch block and a switch matrix from the Xilinx XC4000 FPGA show that the leakage power can be reduced by up to 46% for a 45nm technology node and up to 10% for a 70nm technology node when a switch-matrix is fully loaded.
{"title":"Low-power FPGA routing switches using adaptive body biasing technique","authors":"George V. Leming, Kundan Nepal","doi":"10.1109/MWSCAS.2009.5236058","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236058","url":null,"abstract":"As technology scales and the geometries of the transistors shrink, leakage current and subsequently total power consumption increase considerably. Many of the benefits brought forth by the smaller transistors will be lost if the high power consumption problem cannot be solved. The leakage power consumption problem is especially relevant to an FPGA because of the amount of unused interconnect and logic fabric in the chip during any operation. In this paper, we propose to lower the power consumption of a standard SRAM based FPGA by using half-width transistor stacks and adaptive body biasing techniques. SPICE simulation on a standard pass-transistor based switch block and a switch matrix from the Xilinx XC4000 FPGA show that the leakage power can be reduced by up to 46% for a 45nm technology node and up to 10% for a 70nm technology node when a switch-matrix is fully loaded.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128391369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236158
A. Tekin, H. Elwan, S. Mahmoud, K. Pedrotti
In this paper, a new technique for realizing area efficient, low noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the pass band of the filter. This is illustrated by implementing a 5th-order noise-shaped post mixer gain-filtering circuit in a 65-nm CMOS process. The proposed circuits consume 4.8 mA from a 1.2-V supply with an in-band noise density of 12 nV/sqrt(Hz) and an IIP3 of 25.5 dBm. The design provides 50 dB filtering for the adjacent blockers of the target Digital Video Broadcast-Handheld (DVB-H) receiver. The gain of the stage is programmable in 6-dB steps without altering the filter response.
{"title":"A 12nV/√Hz noise-shaped channel select filter for DVB-H mobile-TV tuners","authors":"A. Tekin, H. Elwan, S. Mahmoud, K. Pedrotti","doi":"10.1109/MWSCAS.2009.5236158","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236158","url":null,"abstract":"In this paper, a new technique for realizing area efficient, low noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the pass band of the filter. This is illustrated by implementing a 5th-order noise-shaped post mixer gain-filtering circuit in a 65-nm CMOS process. The proposed circuits consume 4.8 mA from a 1.2-V supply with an in-band noise density of 12 nV/sqrt(Hz) and an IIP3 of 25.5 dBm. The design provides 50 dB filtering for the adjacent blockers of the target Digital Video Broadcast-Handheld (DVB-H) receiver. The gain of the stage is programmable in 6-dB steps without altering the filter response.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128489384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235986
P. G. López, J. C. Quezada, A. L. Chau
The Concurrent Real-Time Tasks (TTRC), carry out all the activities of a System in Real-Time (STR); the Scheduler of Concurrent Real-Time Tasks (PTTRC) is the responsible of selecting the Real Time Task and the moment that it will take the resources, (PTTRC) is an algorithm that assigns the resources from the processor to different tasks in different moments. However, is necessary to verify effectiveness of the algorithm using an adequate approach that provides a metric between 0 and 1; the measuring should be carried out in local form and in a global way. In this work we intend the measuring of the efficiency of the scheduler through of the evolution of the instances of the Concurrent Tasks and their temporary restrictions.
{"title":"A metric for the evaluation of the efficiency in Scheduler of Concurrent Real-Time Tasks","authors":"P. G. López, J. C. Quezada, A. L. Chau","doi":"10.1109/MWSCAS.2009.5235986","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235986","url":null,"abstract":"The Concurrent Real-Time Tasks (TTRC), carry out all the activities of a System in Real-Time (STR); the Scheduler of Concurrent Real-Time Tasks (PTTRC) is the responsible of selecting the Real Time Task and the moment that it will take the resources, (PTTRC) is an algorithm that assigns the resources from the processor to different tasks in different moments. However, is necessary to verify effectiveness of the algorithm using an adequate approach that provides a metric between 0 and 1; the measuring should be carried out in local form and in a global way. In this work we intend the measuring of the efficiency of the scheduler through of the evolution of the instances of the Concurrent Tasks and their temporary restrictions.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128505245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236114
Zhigang Hao, G. Shi
Capacitive and inductive coupling issues are hard to analyze in general; however, they are critical for signal integrity (SI) analysis in the contemporary integrated circuit technology. This paper presents a sensitivity based computation approach to coupled RLC trees for statistical signal integrity analysis. This technique is intended for use in SI-driven placement and routing.
{"title":"Sensitivity approach to statistical signal integrity analysis of coupled interconnect trees","authors":"Zhigang Hao, G. Shi","doi":"10.1109/MWSCAS.2009.5236114","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236114","url":null,"abstract":"Capacitive and inductive coupling issues are hard to analyze in general; however, they are critical for signal integrity (SI) analysis in the contemporary integrated circuit technology. This paper presents a sensitivity based computation approach to coupled RLC trees for statistical signal integrity analysis. This technique is intended for use in SI-driven placement and routing.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130579571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236130
J. Zeng, V. Joyner, J. Liao, Shengling Deng, Z. Huang
A 7-channel diversity receiver front-end based on current-summing for broadband free-space optical (FSO) MIMO communication is presented in this paper. This diversity receiver is designed for flip-chip bonding to a custom InGaAs metal-semiconductor-metal (MSM) photodetector array. Each channel employs a low input-impedance current mirror (CM) as the input stage, which allows the implementation of direct current-summing for equal-gain combining (EGC). The summed-up current signal drives a second stage transimpedance amplifier (TIA) to generate the output voltage. Implemented in an 180 nm CMOS technology, a total gain of 58.5 dBΩ, and −3dB bandwidth of 3.7 GHz for 0.25 pF photodiode capacitance is achieved. The power consumption for a single front-end amplifier circuit is 4.2 mW, and for the second stage TIA is 10.3mW with a single 1.8V supply.
{"title":"A 5Gb/s 7-channel current-mode imaging receiver front-end for free-space optical MIMO","authors":"J. Zeng, V. Joyner, J. Liao, Shengling Deng, Z. Huang","doi":"10.1109/MWSCAS.2009.5236130","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236130","url":null,"abstract":"A 7-channel diversity receiver front-end based on current-summing for broadband free-space optical (FSO) MIMO communication is presented in this paper. This diversity receiver is designed for flip-chip bonding to a custom InGaAs metal-semiconductor-metal (MSM) photodetector array. Each channel employs a low input-impedance current mirror (CM) as the input stage, which allows the implementation of direct current-summing for equal-gain combining (EGC). The summed-up current signal drives a second stage transimpedance amplifier (TIA) to generate the output voltage. Implemented in an 180 nm CMOS technology, a total gain of 58.5 dBΩ, and −3dB bandwidth of 3.7 GHz for 0.25 pF photodiode capacitance is achieved. The power consumption for a single front-end amplifier circuit is 4.2 mW, and for the second stage TIA is 10.3mW with a single 1.8V supply.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131137815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236024
V. Zaharov, Ángel Lambertt Lobaina, Jaime L. Rodriguez, Ramon Albandoz Soto
The mutual coupling between antenna array elements degrades the performance of spatial processing algorithm, such as signal-to-interference-plus-noise ratio (SINR) in output of antenna array, antenna gain, and so on. If the mutual coupling matrix (MCM) is known, mutual coupling effect can be mitigated by pre-multiplying the input signal by the inverse of the coupling matrix (assuming that it is invertible). Unfortunately, it requires intensive computational work with the cost of O(N2), where N is a number of antenna elements, especially for large antenna array applications. Taking into account that MCM has the Toeplitz structure, we propose to mitigate the mutual coupling with the cost of O(MlogM) by using fast algorithm that involve circular convolution, where 2N ≤ M < 4N and M is a number of power two. The performance of large adaptive antenna array in the presence of mutual coupling as well as after decoupling is discussed.
{"title":"Fast mutual coupling compensation algorithm for large adaptive antenna array","authors":"V. Zaharov, Ángel Lambertt Lobaina, Jaime L. Rodriguez, Ramon Albandoz Soto","doi":"10.1109/MWSCAS.2009.5236024","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236024","url":null,"abstract":"The mutual coupling between antenna array elements degrades the performance of spatial processing algorithm, such as signal-to-interference-plus-noise ratio (SINR) in output of antenna array, antenna gain, and so on. If the mutual coupling matrix (MCM) is known, mutual coupling effect can be mitigated by pre-multiplying the input signal by the inverse of the coupling matrix (assuming that it is invertible). Unfortunately, it requires intensive computational work with the cost of O(N2), where N is a number of antenna elements, especially for large antenna array applications. Taking into account that MCM has the Toeplitz structure, we propose to mitigate the mutual coupling with the cost of O(MlogM) by using fast algorithm that involve circular convolution, where 2N ≤ M < 4N and M is a number of power two. The performance of large adaptive antenna array in the presence of mutual coupling as well as after decoupling is discussed.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130104655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236007
Wen-Chih Wu, O. Chen
The problem of multiple-sound-source localization in a reverberant environment is investigated in this work, which is a critical technique in video conference applications and is still a challenging task in audio signal processing. In this study, sound signals are first estimated and separated from the mixtures received by a microphone array under a feedback architecture using the blind source separation algorithm. The parameters of time delay of arrival associated with microphones are calculated from the mixtures and estimated source signals by the time-domain cross correlation technique. Finally, the positions of sound sources are derived by the spatial position determination formulas. Experimental results demonstrate that the proposed scheme can effectively determine the locations of multiple sound sources in a near-field and reverberant environment. The direction prediction using the proposed scheme is very promising.
{"title":"Multiple-sound-source localization scheme based on feedback-architecture source separation","authors":"Wen-Chih Wu, O. Chen","doi":"10.1109/MWSCAS.2009.5236007","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236007","url":null,"abstract":"The problem of multiple-sound-source localization in a reverberant environment is investigated in this work, which is a critical technique in video conference applications and is still a challenging task in audio signal processing. In this study, sound signals are first estimated and separated from the mixtures received by a microphone array under a feedback architecture using the blind source separation algorithm. The parameters of time delay of arrival associated with microphones are calculated from the mixtures and estimated source signals by the time-domain cross correlation technique. Finally, the positions of sound sources are derived by the spatial position determination formulas. Experimental results demonstrate that the proposed scheme can effectively determine the locations of multiple sound sources in a near-field and reverberant environment. The direction prediction using the proposed scheme is very promising.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"6 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120866555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235920
H. Patangia, D. Gregory
The paper extends previous work on a novel multilevel PWM strategy to design and implement an optimal inverter for a stand-alone PV application. This modulation strategy produces a much higher fundamental output compared to conventional SPWM without any pulse dropping. Phase-shifted carriers have been used to produce a harmonically superior SPWM signal. A higher fundamental coupled with harmonic elimination through phase shifted carriers reduces THD and improves conversion efficiency. The simulation results have been validated through an experimental prototype.
{"title":"A class of optimal multilevel inverters based on sectionalized PWM (S-PWM) modulation strategy","authors":"H. Patangia, D. Gregory","doi":"10.1109/MWSCAS.2009.5235920","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235920","url":null,"abstract":"The paper extends previous work on a novel multilevel PWM strategy to design and implement an optimal inverter for a stand-alone PV application. This modulation strategy produces a much higher fundamental output compared to conventional SPWM without any pulse dropping. Phase-shifted carriers have been used to produce a harmonically superior SPWM signal. A higher fundamental coupled with harmonic elimination through phase shifted carriers reduces THD and improves conversion efficiency. The simulation results have been validated through an experimental prototype.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127055028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235999
Jing Li, Chunyan Wang
In this paper, a procedure of edge detection for a high dynamic range image with damaged edge information is proposed. This procedure is based on a scheme of multiple filtering processes which does not include any segmentation of the image. Three different filtering processes are designed to generate three gradient maps, in each of which gradients are calculated and modulated by using a specific filter. The enhanced gradients, i.e. those modulated correctly, are identified in each of the three gradient maps by using a selection algorithm. They are taken to generate a complete edge map. This procedure allows varieties of edge gradient enhancements applied in the same image by employing a set of simple filters without segmentation. The effectiveness of the detection process has been confirmed by simulations.
{"title":"Multiple-filtering process and its application in edge detection","authors":"Jing Li, Chunyan Wang","doi":"10.1109/MWSCAS.2009.5235999","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235999","url":null,"abstract":"In this paper, a procedure of edge detection for a high dynamic range image with damaged edge information is proposed. This procedure is based on a scheme of multiple filtering processes which does not include any segmentation of the image. Three different filtering processes are designed to generate three gradient maps, in each of which gradients are calculated and modulated by using a specific filter. The enhanced gradients, i.e. those modulated correctly, are identified in each of the three gradient maps by using a selection algorithm. They are taken to generate a complete edge map. This procedure allows varieties of edge gradient enhancements applied in the same image by employing a set of simple filters without segmentation. The effectiveness of the detection process has been confirmed by simulations.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127069180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236081
T. Oshima, Tomomi Takahashi, T. Yamawaki
Novel sampling-timing background calibration for time-interleaved A/D converters has been proposed and verified by simulation. An FIR(Finite Impulse Response)-filter structure exploiting the sampling theorem provides simple but accurate time derivative of converted signal and hence enables reliable estimation and compensation of sampling-timing deviation of each unit ADC assisted by reference converter and LMS(Least Mean Square) algorithm. It has also been confirmed that the sampling-timing calibration can successfully be combined with proposed gain and DC-offset calibrations.
{"title":"Novel sampling timing background calibration for time-interleaved A/D converters","authors":"T. Oshima, Tomomi Takahashi, T. Yamawaki","doi":"10.1109/MWSCAS.2009.5236081","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236081","url":null,"abstract":"Novel sampling-timing background calibration for time-interleaved A/D converters has been proposed and verified by simulation. An FIR(Finite Impulse Response)-filter structure exploiting the sampling theorem provides simple but accurate time derivative of converted signal and hence enables reliable estimation and compensation of sampling-timing deviation of each unit ADC assisted by reference converter and LMS(Least Mean Square) algorithm. It has also been confirmed that the sampling-timing calibration can successfully be combined with proposed gain and DC-offset calibrations.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125469405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：