Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235973
F. Ghaffar, M. Mobeen, Sharjeel Qamar, Muhammad Hasan
This paper reports the design and implementation of microstrip based quadrature phase shift keying (QPSK) modulator using quadrature hybrid (Branchline) coupler and MESFET switches. The modulator is designed to operate between 7.5 GHz to 9.5 GHz. Fabricated modulator has carrier suppression of 29 dB across the frequency range and has an amplitude imbalance of less than 0.1 dB with phase imbalance of 0.4° around its center frequency. The modulation is checked upto 160 Mbps and spurious suppression is found to be greater then 40 dB and has zero DC power consumption.
{"title":"A wide-band QPSK modulator using branch-line coupler and MESFET switches","authors":"F. Ghaffar, M. Mobeen, Sharjeel Qamar, Muhammad Hasan","doi":"10.1109/MWSCAS.2009.5235973","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235973","url":null,"abstract":"This paper reports the design and implementation of microstrip based quadrature phase shift keying (QPSK) modulator using quadrature hybrid (Branchline) coupler and MESFET switches. The modulator is designed to operate between 7.5 GHz to 9.5 GHz. Fabricated modulator has carrier suppression of 29 dB across the frequency range and has an amplitude imbalance of less than 0.1 dB with phase imbalance of 0.4° around its center frequency. The modulation is checked upto 160 Mbps and spurious suppression is found to be greater then 40 dB and has zero DC power consumption.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116056253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236001
A. Abdelgawad, S. Abdelhak, Soumik Ghosh, M. Bayoumi
Multiplication is at the core of many data processing tasks and saving power at the multiplication level can significantly impact the lifetime of a wireless sensor network. This paper introduces a novel light-weight low-power multiplication algorithm which is tailored for sensor nodes featuring low-end microcontrollers. These microcontrollers might have no hardware multiplier, or feature a fixed-point hardware multiplier which incurs significant energy overhead when enabled. The proposed algorithm aims to reduce the number of add operations during multiplication by rounding any sequence of 1's in the fractional part. The applied rounding decreases the number of instruction cycles, and reduces the memory storage without increasing the code complexity or sacrificing accuracy. Simulation results show that the proposed algorithm achieves up to 17% power saving and 16% increase in speed, with only 1% accuracy loss compared to Horner's algorithm. The effectiveness of the algorithm was demonstrated by implementing a finite impulse response (FIR) using the proposed method. The new multiplication method has been validated experimentally using the eZ430-RF2500 wireless sensor board.
{"title":"A low-power multiplication algorithm for signal processing in wireless sensor networks","authors":"A. Abdelgawad, S. Abdelhak, Soumik Ghosh, M. Bayoumi","doi":"10.1109/MWSCAS.2009.5236001","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236001","url":null,"abstract":"Multiplication is at the core of many data processing tasks and saving power at the multiplication level can significantly impact the lifetime of a wireless sensor network. This paper introduces a novel light-weight low-power multiplication algorithm which is tailored for sensor nodes featuring low-end microcontrollers. These microcontrollers might have no hardware multiplier, or feature a fixed-point hardware multiplier which incurs significant energy overhead when enabled. The proposed algorithm aims to reduce the number of add operations during multiplication by rounding any sequence of 1's in the fractional part. The applied rounding decreases the number of instruction cycles, and reduces the memory storage without increasing the code complexity or sacrificing accuracy. Simulation results show that the proposed algorithm achieves up to 17% power saving and 16% increase in speed, with only 1% accuracy loss compared to Horner's algorithm. The effectiveness of the algorithm was demonstrated by implementing a finite impulse response (FIR) using the proposed method. The new multiplication method has been validated experimentally using the eZ430-RF2500 wireless sensor board.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127298712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235984
Seonghan Ryu
A multi standard carrier generator chain satisfying all requirements of phase noise and frequency range for Quad-band GSM/EDGE and WCDMA standards is presented. It adopts a VCO utilizing bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain. CMOS logic dividers are also adopted in this LO chain to meet the most stringent phase noise specification of GSM. The proposed divider structure also shows very wide tuning range of self oscillation frequency(0.54 to 2.44GHz). The proposed LO chain is implemented in 0.13 µm CMOS technology. The measured tuning range is about 22% (3.25 to 4.05 GHz). The LO chain exhibits a phase noise of −126, −136 and −164dBc/Hz measured respectively at 400KHz, 1MHz and 20MHz offset from 900MHz Carrier.
{"title":"Multi-standard carrier generator with CMOS logic divider","authors":"Seonghan Ryu","doi":"10.1109/MWSCAS.2009.5235984","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235984","url":null,"abstract":"A multi standard carrier generator chain satisfying all requirements of phase noise and frequency range for Quad-band GSM/EDGE and WCDMA standards is presented. It adopts a VCO utilizing bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain. CMOS logic dividers are also adopted in this LO chain to meet the most stringent phase noise specification of GSM. The proposed divider structure also shows very wide tuning range of self oscillation frequency(0.54 to 2.44GHz). The proposed LO chain is implemented in 0.13 µm CMOS technology. The measured tuning range is about 22% (3.25 to 4.05 GHz). The LO chain exhibits a phase noise of −126, −136 and −164dBc/Hz measured respectively at 400KHz, 1MHz and 20MHz offset from 900MHz Carrier.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125264500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236136
Sungho Kim, W. Lepkowski, T. Thornton, B. Bakkaloglu
MESFET devices provide high breakdown characteristics, enable high voltage operation, and direct battery hook-up with no changes in processing on state of the art SOI and SOS CMOS processes. Fundamental analog building blocks, including single-ended and differential amplifiers and high impedance current mirror were designed and fabricated in a single poly, 3-layer metal digital CMOS technology utilizing fully depletion mode MESFET devices. The measured breakdown voltage of the SOS MESFETS presented here has a breakdown voltage of over 7.5 V without causing irreversible damage. DC characteristics were measured by varying the power supply from 2.5 to 5.5V. The measured DC transfer curves of amplifiers show good agreement with the simulated ones with extracted models from the same process. The accuracy of the current mirror showing inverse operation is within ±5% for the current from 0 to 1.5 mA with the power supply from 2.5 to 5.5V.
{"title":"CMOS compatible high voltage compliant MESFET based analog IC building blocks","authors":"Sungho Kim, W. Lepkowski, T. Thornton, B. Bakkaloglu","doi":"10.1109/MWSCAS.2009.5236136","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236136","url":null,"abstract":"MESFET devices provide high breakdown characteristics, enable high voltage operation, and direct battery hook-up with no changes in processing on state of the art SOI and SOS CMOS processes. Fundamental analog building blocks, including single-ended and differential amplifiers and high impedance current mirror were designed and fabricated in a single poly, 3-layer metal digital CMOS technology utilizing fully depletion mode MESFET devices. The measured breakdown voltage of the SOS MESFETS presented here has a breakdown voltage of over 7.5 V without causing irreversible damage. DC characteristics were measured by varying the power supply from 2.5 to 5.5V. The measured DC transfer curves of amplifiers show good agreement with the simulated ones with extracted models from the same process. The accuracy of the current mirror showing inverse operation is within ±5% for the current from 0 to 1.5 mA with the power supply from 2.5 to 5.5V.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126612706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236017
K. Gbolagade, S. Cotofana
In this paper, we investigate Residue Number System (RNS) to decimal conversion for moduli sets with common factors. First, we propose a new RNS to decimal converter for the moduli set {2n+2; 2n+1; 2n} for any integer n > 0, which is a generalization of a recently proposed reverse converter for this moduli set. Second, we provide a general 4-moduli RNS conversion scheme and then present a compact form of multiplicative inverses, valid for odd-n, for the moduli set {2n+3; 2n+2; 2n+1; 2n}. This extended moduli set increases the dynamic range and the processing parallelism enabling efficient conversion.
本文研究了具有公因式模集的剩余数制到十进制的转换。首先，我们针对模集{2n+2]提出了一种新的RNS - decimal转换器;2 n + 1;对于任意整数n > 0的2n}，这是最近提出的对该模集的反向转换器的推广。其次，我们提供了一个一般的4模RNS转换方案，然后给出了对奇数n有效的乘逆的紧凑形式，对于模集{2n+3;2 n + 2;2 n + 1;2 n}。这种扩展模集增加了动态范围和处理并行性，从而实现了有效的转换。
{"title":"Residue-to-decimal converters for moduli sets with common factors","authors":"K. Gbolagade, S. Cotofana","doi":"10.1109/MWSCAS.2009.5236017","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236017","url":null,"abstract":"In this paper, we investigate Residue Number System (RNS) to decimal conversion for moduli sets with common factors. First, we propose a new RNS to decimal converter for the moduli set {2n+2; 2n+1; 2n} for any integer n > 0, which is a generalization of a recently proposed reverse converter for this moduli set. Second, we provide a general 4-moduli RNS conversion scheme and then present a compact form of multiplicative inverses, valid for odd-n, for the moduli set {2n+3; 2n+2; 2n+1; 2n}. This extended moduli set increases the dynamic range and the processing parallelism enabling efficient conversion.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123384949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235945
Jin-Hua Hong, Tun-Kai Yao, Liang-Jia Lue
In this paper, we design and implement a cryptosystem SoC (CSoC). We combine a virtual microprocessor and AMBA bus to elaborate an embedded system model that is capable of shortening the testing time of the global system and calculating the performance for various types of microprocessors. The virtual microprocessor instead of the physical one is used to control the entire system, so that the high level program could be applied to monitor the behavior of the system. The power management technology and Chaos key evolved module are integrated to improve our design. The CSoC is implemented using both a 0.18µm TSMC cell library and an FPGA Device.
{"title":"Design and implementation of a low-power cryptosystem SoC","authors":"Jin-Hua Hong, Tun-Kai Yao, Liang-Jia Lue","doi":"10.1109/MWSCAS.2009.5235945","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235945","url":null,"abstract":"In this paper, we design and implement a cryptosystem SoC (CSoC). We combine a virtual microprocessor and AMBA bus to elaborate an embedded system model that is capable of shortening the testing time of the global system and calculating the performance for various types of microprocessors. The virtual microprocessor instead of the physical one is used to control the entire system, so that the high level program could be applied to monitor the behavior of the system. The power management technology and Chaos key evolved module are integrated to improve our design. The CSoC is implemented using both a 0.18µm TSMC cell library and an FPGA Device.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128198155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236042
Takuya Yamamoto, V. Moshnyaga
This paper presents a new architecture of rank-order median filter. The architecture processes all window samples in parallel in the bit-serial manner. Unlike related architectures, it neither sorts/swaps nor modifies the window samples and requires less hardware resources. To process k samples, each of N-bits in size, the architecture uses N shift registers of k bits each and a simple logic. It produces the result in N+1 clock cycles independently to the window size.
{"title":"A new bit-serial architecture of rank-order filter","authors":"Takuya Yamamoto, V. Moshnyaga","doi":"10.1109/MWSCAS.2009.5236042","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236042","url":null,"abstract":"This paper presents a new architecture of rank-order median filter. The architecture processes all window samples in parallel in the bit-serial manner. Unlike related architectures, it neither sorts/swaps nor modifies the window samples and requires less hardware resources. To process k samples, each of N-bits in size, the architecture uses N shift registers of k bits each and a simple logic. It produces the result in N+1 clock cycles independently to the window size.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126676611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236029
S. Bokhari, B. Nowrouzian
Frequency-Response Masking (FRM) technique is known to significantly reduce computational complexity of sharp transition-band digital filters. This paper presents a novel technique for the design and optimization of a guaranteed BIBO stable FRM IIR lowpass digital filter, employing an odd-order IIR elliptic minimum Q-factor (EMQF) prototype digital filter. The bilinear-LDI design approach is used to realize the prototype digital filter as a parallel combination of a pair of digital allpass networks. A diversity-controlled genetic algorithm (DCGA) is employed for the optimization of the bilinear-LDI FRM IIR digital filter over the canonical signed-digit multiplier coefficient space. A LUT-based scheme is employed to ensure that the resulting FRM IIR digital filter is automatically BIBO stable during DCGA optimization. The proposed technique is illustrated through its application to the optimization of a fifth-order lowpass elliptic FRM IIR digital filter, resulting in a rapid convergence speed of around 300 iterations.
{"title":"DCGA optimization of lowpass FRM IIR digital filters over CSD multiplier coefficient space","authors":"S. Bokhari, B. Nowrouzian","doi":"10.1109/MWSCAS.2009.5236029","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236029","url":null,"abstract":"Frequency-Response Masking (FRM) technique is known to significantly reduce computational complexity of sharp transition-band digital filters. This paper presents a novel technique for the design and optimization of a guaranteed BIBO stable FRM IIR lowpass digital filter, employing an odd-order IIR elliptic minimum Q-factor (EMQF) prototype digital filter. The bilinear-LDI design approach is used to realize the prototype digital filter as a parallel combination of a pair of digital allpass networks. A diversity-controlled genetic algorithm (DCGA) is employed for the optimization of the bilinear-LDI FRM IIR digital filter over the canonical signed-digit multiplier coefficient space. A LUT-based scheme is employed to ensure that the resulting FRM IIR digital filter is automatically BIBO stable during DCGA optimization. The proposed technique is illustrated through its application to the optimization of a fifth-order lowpass elliptic FRM IIR digital filter, resulting in a rapid convergence speed of around 300 iterations.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127281284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236166
Fuding Ge
This paper presents a CMOS chopper-stabilized instrumentation amplifier based on a compact differential difference amplifier (DDA). The DDA itself is based on a high gain and robust two-stage class-AB amplifier. Simulation results show that with chopping frequency at 250 KHz, both the noise density and offset can be reduced by a factor of 10. Detailed practical application considerations of the proposed In-Amp as a current-sensing amplifier in a power management chip are presented.
{"title":"A pseudo rail-to-rail chopper-stabilized instrumentation amplifier in 0.13 µm CMOS","authors":"Fuding Ge","doi":"10.1109/MWSCAS.2009.5236166","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236166","url":null,"abstract":"This paper presents a CMOS chopper-stabilized instrumentation amplifier based on a compact differential difference amplifier (DDA). The DDA itself is based on a high gain and robust two-stage class-AB amplifier. Simulation results show that with chopping frequency at 250 KHz, both the noise density and offset can be reduced by a factor of 10. Detailed practical application considerations of the proposed In-Amp as a current-sensing amplifier in a power management chip are presented.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131502667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235992
R. Martínez-Noriega, M. Nakano, B. Kurkoski, K. Yamaguchi, K. Kobayashi
In this paper, we analyze audio watermarking methods based on quantization index modulation and low-density parity-check (LDPC) codes. We found that dither modulation (DM) can achieve better performance using half-rate Margulis LDPC code even better than some low-rate codes. Then, we propose a scheme based on LDPC codes and DM with distortion-compensation (DC) property which has a robustness benefit of 6 dB versus uncoded case, 2 dB versus algebraic codes, 1 dB versus DM with LDPC code. In DM with DC property, we show that it is possible to achieve. 5 dB better robustness using a scale parameter α lower than the theoretically optimal and LDPC codes. Finally our proposal was evaluated against more practical attacks. These results show that our scheme could be a good option for robust watermarks.
{"title":"Analysis of QIM-based audio watermarking using LDPC codes","authors":"R. Martínez-Noriega, M. Nakano, B. Kurkoski, K. Yamaguchi, K. Kobayashi","doi":"10.1109/MWSCAS.2009.5235992","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235992","url":null,"abstract":"In this paper, we analyze audio watermarking methods based on quantization index modulation and low-density parity-check (LDPC) codes. We found that dither modulation (DM) can achieve better performance using half-rate Margulis LDPC code even better than some low-rate codes. Then, we propose a scheme based on LDPC codes and DM with distortion-compensation (DC) property which has a robustness benefit of 6 dB versus uncoded case, 2 dB versus algebraic codes, 1 dB versus DM with LDPC code. In DM with DC property, we show that it is possible to achieve. 5 dB better robustness using a scale parameter α lower than the theoretically optimal and LDPC codes. Finally our proposal was evaluated against more practical attacks. These results show that our scheme could be a good option for robust watermarks.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125680019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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