Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00006
Aibin Yan, Zhen Wu, Jun Zhou, Yuanjie Hu, Yan Chen, Zuobin Ying, X. Wen, P. Girard
The Aggressive technology scaling makes modern advanced SRAMs more and more sensitive to soft errors that include single-node upsets (SNUs) and double-node upsets (DNUs). This paper presents a novel Sextuple Cross-Coupled SRAM cell, namely SCCS cell, which can tolerate both SNUs and DNUs. The cell mainly consists of six cross-coupled input-split inverters, constructing a large error-interceptive feedback loop to robustly retain stored values. Since the cell has many redundant storage nodes, the cell achieves the following robustness: (1) the cell can self-recover from all possible SNU; (2) the cell can self-recover from partial DNUs; (3) the cell can avoid the occurrence of other DNUs due to node-separation. Simulation results validate the excellent robustness of the proposed cell. Moreover, compared with the state-of-the-art typical existing hardened cells, the proposed cell achieves an approximate 61% read access time as well as 12% write access time reduction at the costs of 47% power dissipation as well as 44% silicon area on average.
{"title":"Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications","authors":"Aibin Yan, Zhen Wu, Jun Zhou, Yuanjie Hu, Yan Chen, Zuobin Ying, X. Wen, P. Girard","doi":"10.1109/ATS47505.2019.00006","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00006","url":null,"abstract":"The Aggressive technology scaling makes modern advanced SRAMs more and more sensitive to soft errors that include single-node upsets (SNUs) and double-node upsets (DNUs). This paper presents a novel Sextuple Cross-Coupled SRAM cell, namely SCCS cell, which can tolerate both SNUs and DNUs. The cell mainly consists of six cross-coupled input-split inverters, constructing a large error-interceptive feedback loop to robustly retain stored values. Since the cell has many redundant storage nodes, the cell achieves the following robustness: (1) the cell can self-recover from all possible SNU; (2) the cell can self-recover from partial DNUs; (3) the cell can avoid the occurrence of other DNUs due to node-separation. Simulation results validate the excellent robustness of the proposed cell. Moreover, compared with the state-of-the-art typical existing hardened cells, the proposed cell achieves an approximate 61% read access time as well as 12% write access time reduction at the costs of 47% power dissipation as well as 44% silicon area on average.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115738361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.000-1
Saranyu Chattopadhyay, P. Kumari, B. Ray, R. Chakraborty
With the large-scale adaptation of a "horizontal" business model, modern semiconductor supply chain is plagued by recycled and counterfeit ICs, including flash memory chips. Since flash memory modules have an inherently finite lifespan, detection of recycled flash memory chips before their deployment in safety-critical systems is important to prevent disastrous consequences. The state-of-art detection methods can detect flash memory modules between 0.05% to 3.00% of their lifespan as minimum usage duration, depending on the details of the flash memory chip. In this paper, we propose a versatile machine learning assisted detection methodology to improve the minimum usage duration accuracy between 0.05% to 0.96% of their lifespan, and also to accurately associate a flash memory IC with its manufacturer. Through detailed experimentation and comparison of detection results obtained using three popular supervised machine learning techniques (Support Vector Machines, Logistic Regression and Artificial Neural Networks), we demonstrate that usage of features composed of multiple characteristics of a given chip, rather than just a single property of a chip (as used in previous works), improves detection accuracy.
{"title":"Machine Learning Assisted Accurate Estimation of Usage Duration and Manufacturer for Recycled and Counterfeit Flash Memory Detection","authors":"Saranyu Chattopadhyay, P. Kumari, B. Ray, R. Chakraborty","doi":"10.1109/ATS47505.2019.000-1","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.000-1","url":null,"abstract":"With the large-scale adaptation of a \"horizontal\" business model, modern semiconductor supply chain is plagued by recycled and counterfeit ICs, including flash memory chips. Since flash memory modules have an inherently finite lifespan, detection of recycled flash memory chips before their deployment in safety-critical systems is important to prevent disastrous consequences. The state-of-art detection methods can detect flash memory modules between 0.05% to 3.00% of their lifespan as minimum usage duration, depending on the details of the flash memory chip. In this paper, we propose a versatile machine learning assisted detection methodology to improve the minimum usage duration accuracy between 0.05% to 0.96% of their lifespan, and also to accurately associate a flash memory IC with its manufacturer. Through detailed experimentation and comparison of detection results obtained using three popular supervised machine learning techniques (Support Vector Machines, Logistic Regression and Artificial Neural Networks), we demonstrate that usage of features composed of multiple characteristics of a given chip, rather than just a single property of a chip (as used in previous works), improves detection accuracy.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128829862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.000-6
Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, X. Lin, M. Kassab, I. Pomeranz
Timing exceptions are commonly used to indicate that the timing of certain paths have been relaxed so as to enable the design to meet timing closure. Generating scan-based test patterns without considering timing exceptions can lead to invalid test responses, resulting in unpredictable test quality impact. The existing simulation-based solution masks out unreliable signals after a test pattern is generated. If the signals required for detecting the target fault are unreliable and masked out, the generated test pattern fails to detect the target fault, and it is discarded. To achieve an acceptable test coverage, several iterations of test generation with a randomized decision-making process are typically required where different tests are generated for target faults. In this paper, an innovative deterministic ATPG algorithm called TEA (Timing Exception ATPG) is proposed to prevent the generated test patterns from being impacted by timing exceptions. The deterministic algorithm is compatible with the existing simulation-based approach. In this simulation environment, TEA is complete such that for a target fault, the test pattern generated is guaranteed to detect it. If a test pattern cannot be generated using TEA, the target fault is untestable given the timing exception paths in the design and the existing simulation environment. Compared to the existing simulation-based approach, using TEA can generate a more effective test set, improving test coverage, test pattern count, and the total ATPG run time significantly.
{"title":"TEA: A Test Generation Algorithm for Designs with Timing Exceptions","authors":"Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, X. Lin, M. Kassab, I. Pomeranz","doi":"10.1109/ATS47505.2019.000-6","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.000-6","url":null,"abstract":"Timing exceptions are commonly used to indicate that the timing of certain paths have been relaxed so as to enable the design to meet timing closure. Generating scan-based test patterns without considering timing exceptions can lead to invalid test responses, resulting in unpredictable test quality impact. The existing simulation-based solution masks out unreliable signals after a test pattern is generated. If the signals required for detecting the target fault are unreliable and masked out, the generated test pattern fails to detect the target fault, and it is discarded. To achieve an acceptable test coverage, several iterations of test generation with a randomized decision-making process are typically required where different tests are generated for target faults. In this paper, an innovative deterministic ATPG algorithm called TEA (Timing Exception ATPG) is proposed to prevent the generated test patterns from being impacted by timing exceptions. The deterministic algorithm is compatible with the existing simulation-based approach. In this simulation environment, TEA is complete such that for a target fault, the test pattern generated is guaranteed to detect it. If a test pattern cannot be generated using TEA, the target fault is untestable given the timing exception paths in the design and the existing simulation environment. Compared to the existing simulation-based approach, using TEA can generate a more effective test set, improving test coverage, test pattern count, and the total ATPG run time significantly.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124683866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ats47505.2019.00-11
{"title":"ATS 2019 Industry Forum Invited Talks","authors":"","doi":"10.1109/ats47505.2019.00-11","DOIUrl":"https://doi.org/10.1109/ats47505.2019.00-11","url":null,"abstract":"","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117212247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ats47505.2019.00005
The main goal of organizing IEEE Asian Test Symposium (ATS 2019) is to promote discussions and scientific exchange of knowledge between researchers, developers, engineers, academicians, and students working in India and abroad. ATS 2019 hopes to address design, test, and yield challenges faced by the industry with the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.
{"title":"About the 2019 IEEE 28th Asian Test Symposium","authors":"","doi":"10.1109/ats47505.2019.00005","DOIUrl":"https://doi.org/10.1109/ats47505.2019.00005","url":null,"abstract":"The main goal of organizing IEEE Asian Test Symposium (ATS 2019) is to promote discussions and scientific exchange of knowledge between researchers, developers, engineers, academicians, and students working in India and abroad. ATS 2019 hopes to address design, test, and yield challenges faced by the industry with the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128431629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ats47505.2019.00009
Michiko Inoue, Huawei Li, B. Bhattacharya, Tomoo Inoue, Kuen-Jong Lee
Committee Members Bhargab B. Bhattacharya, Indian Institute of Technology Kharagpur, India Krishnendu Chakrabarty, Duke University, USA Patrick Girard, LIRMM/CNRS, France Masaki Hashizume, University of Tokushima, Japan Shi-Yu Huang, National Tsing Hua University, Taiwan Jinn-Lang Huang, National Taiwan University, Taiwan Tomoo Inoue, Hiroshima City University, Japan Seiji Kajihara, Kyushu Institute of Technology, Japan Kuen-Jong Lee, National Cheng Kung University, Taiwan Huawei Li, Chinese Academy of Sciences, China Xiaowei Li, Chinese Academy of Sciences, China Virendra Singh, Indian Institute of Science, India Hiroshi Takahashi, Ehime University, Japan Sying-Jyan Wang, National Chung Hsing University, Taiwan Shiyi Xu, Shanghai University, China
委员会成员Bhargab B. Bhattacharya、印度Kharagpur理工学院、印度Krishnendu Chakrabarty、杜克大学、美国Patrick Girard、limm /CNRS、法国Masaki Hashizume、德岛大学、日本黄世玉、国立清华大学、台湾黄金朗、国立台湾大学、台湾井上友茂、广岛市立大学、日本梶原诚司、九州工业大学、日本李根钟、国立成功大学、台湾李华华、中国科学院，中国李晓伟，中国科学院，中国Virendra Singh，印度科学研究所，印度高桥宏，爱媛大学，日本王赛吉安，国立中兴大学，台湾徐世义，上海大学，中国
{"title":"ATS 2019 Steering Committee","authors":"Michiko Inoue, Huawei Li, B. Bhattacharya, Tomoo Inoue, Kuen-Jong Lee","doi":"10.1109/ats47505.2019.00009","DOIUrl":"https://doi.org/10.1109/ats47505.2019.00009","url":null,"abstract":"Committee Members Bhargab B. Bhattacharya, Indian Institute of Technology Kharagpur, India Krishnendu Chakrabarty, Duke University, USA Patrick Girard, LIRMM/CNRS, France Masaki Hashizume, University of Tokushima, Japan Shi-Yu Huang, National Tsing Hua University, Taiwan Jinn-Lang Huang, National Taiwan University, Taiwan Tomoo Inoue, Hiroshima City University, Japan Seiji Kajihara, Kyushu Institute of Technology, Japan Kuen-Jong Lee, National Cheng Kung University, Taiwan Huawei Li, Chinese Academy of Sciences, China Xiaowei Li, Chinese Academy of Sciences, China Virendra Singh, Indian Institute of Science, India Hiroshi Takahashi, Ehime University, Japan Sying-Jyan Wang, National Chung Hsing University, Taiwan Shiyi Xu, Shanghai University, China","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125222424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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