Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00019
Binod Kumar, Atul Kumar Bhosale, M. Fujita, Virendra Singh
Modern chip multi-processors (CMP) inevitably require cache coherence mechanisms for their correct operation. However, exhaustive functional verification of a complex cache coherence mechanism is a challenging task. This leads to bugs escaping to the first silicon and necessitates validation at the post- silicon stage. In this work, an on-chip signal logging method is proposed which helps in bug detection in case of design errors and soft-errors arising out of reliability issues. The logged contents can then be further dumped off-line for fine-grained bug localization. The proposed methodology utilizes cache coherence protocol specifications to obtain the signal states of coherence transactions and the detector module flags an error once a mismatch is found between observed signal states and correct signal states. The proposed logging mechanism decreases the error detection latency at minimal area and power overheads. Experiments on a four core multiprocessor having a 7-stage MIPS pipeline implementing the widely utilized directory-based MESI protocol indicate that the proposed methodology succeeds in detecting design errors. Analysis of soft errors have also been performed and shorter error detection latency is achieved compared to a previously proposed technique in the literature.
{"title":"Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability","authors":"Binod Kumar, Atul Kumar Bhosale, M. Fujita, Virendra Singh","doi":"10.1109/ATS47505.2019.00019","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00019","url":null,"abstract":"Modern chip multi-processors (CMP) inevitably require cache coherence mechanisms for their correct operation. However, exhaustive functional verification of a complex cache coherence mechanism is a challenging task. This leads to bugs escaping to the first silicon and necessitates validation at the post- silicon stage. In this work, an on-chip signal logging method is proposed which helps in bug detection in case of design errors and soft-errors arising out of reliability issues. The logged contents can then be further dumped off-line for fine-grained bug localization. The proposed methodology utilizes cache coherence protocol specifications to obtain the signal states of coherence transactions and the detector module flags an error once a mismatch is found between observed signal states and correct signal states. The proposed logging mechanism decreases the error detection latency at minimal area and power overheads. Experiments on a four core multiprocessor having a 7-stage MIPS pipeline implementing the widely utilized directory-based MESI protocol indicate that the proposed methodology succeeds in detecting design errors. Analysis of soft errors have also been performed and shorter error detection latency is achieved compared to a previously proposed technique in the literature.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121099855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.000-4
Yushiro Hiramoto, S. Ohtake, Hiroshi Takahashi
In this paper, we propose a built-in self-diagnosis (BISD) mechanism for delay faults induced by degradation. This mechanism solely generates expected signatures using slower clock on the fly and requires no memory for storing pre-computed expected signatures. In our experiment, the proposed BISD mechanism is applied to benchmark circuits. Area overhead and diagnostic resolution are evaluated.
{"title":"A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures","authors":"Yushiro Hiramoto, S. Ohtake, Hiroshi Takahashi","doi":"10.1109/ATS47505.2019.000-4","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.000-4","url":null,"abstract":"In this paper, we propose a built-in self-diagnosis (BISD) mechanism for delay faults induced by degradation. This mechanism solely generates expected signatures using slower clock on the fly and requires no memory for storing pre-computed expected signatures. In our experiment, the proposed BISD mechanism is applied to benchmark circuits. Area overhead and diagnostic resolution are evaluated.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129449728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00027
Sourav Ghosh, Dolan Maity, Arijit Chowdhury, S. Roy, C. Giri
Digital microfluidic biochip is a revolutionizing platform to execute complex bioassay operations concurrently. Dependability is an important feature of digital microfluidic biochip which is used for many safety-critical applications, such as point-of-care health assessment, air-quality monitoring, and food-safety testing. Therefore to ensure the proper functionality of the biochip a robust offline and online testing is required. Testing can be done before manufacturing or concurrently with other bioassay operations. In this work, we are presenting an efficient parallel testing and diagnosis scheme to reveal the location of all the faulty electrodes. Most of the algorithms present in the literature are mainly focused on single fault identification. But the diagnosis of biochip with multiple faults is not addressed properly. Even some of the algorithms have incorrectly classified the non faulty electrode as a faulty electrode. Thus in this paper, we are mainly focusing on the detection of multiple faults, correctly and efficiently. Moreover, this testing method is capable to check the given biochip with other concurrently running bioassay operations.
{"title":"Iterative Parallel Test to Detect and Diagnose Multiple Defects for Digital Microfluidic Biochip","authors":"Sourav Ghosh, Dolan Maity, Arijit Chowdhury, S. Roy, C. Giri","doi":"10.1109/ATS47505.2019.00027","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00027","url":null,"abstract":"Digital microfluidic biochip is a revolutionizing platform to execute complex bioassay operations concurrently. Dependability is an important feature of digital microfluidic biochip which is used for many safety-critical applications, such as point-of-care health assessment, air-quality monitoring, and food-safety testing. Therefore to ensure the proper functionality of the biochip a robust offline and online testing is required. Testing can be done before manufacturing or concurrently with other bioassay operations. In this work, we are presenting an efficient parallel testing and diagnosis scheme to reveal the location of all the faulty electrodes. Most of the algorithms present in the literature are mainly focused on single fault identification. But the diagnosis of biochip with multiple faults is not addressed properly. Even some of the algorithms have incorrectly classified the non faulty electrode as a faulty electrode. Thus in this paper, we are mainly focusing on the detection of multiple faults, correctly and efficiently. Moreover, this testing method is capable to check the given biochip with other concurrently running bioassay operations.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114396134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00013
Ching-Yuan Chen, Jiun-Lang Huang
Software-based Self-test (SBST) has been recognized as a promising complement to scan-based structural Built-in Self-test (BIST), especially for in-field self-test applications. In response to the ever-increasing complexities of the modern CPU designs, machine learning algorithms have been proposed to extract processor behavior from simulation data and help constrain ATPG to generate functionally-compatible patterns. However, these simulation-based approaches in general suffer sample inefficiency, i.e., only a small portion of the simulation traces are relevant to fault detection. Inspired by the recent advances in reinforcement learning (RL), we propose an RL-based test program generation technique for transition delay fault (TDF) detection. During the training process, knowledge learned from the simulation data is employed to tune the simulation policy; this close-loop approach significantly improves data efficiency, compared to previous open-loop approaches. Furthermore, RL is capable of dealing with delayed responses, which is common when executing processor instructions. Using the trained RL model, instruction sequences that bring the processor to the fault-sensitizing states, i.e., TDF test patterns, can be generated. The proposed test program generation technique is applied to a MIPS32 processor. For TDF, the fault coverage is 94.94%, which is just 2.57% less than the full-scan based approach.
{"title":"Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test","authors":"Ching-Yuan Chen, Jiun-Lang Huang","doi":"10.1109/ATS47505.2019.00013","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00013","url":null,"abstract":"Software-based Self-test (SBST) has been recognized as a promising complement to scan-based structural Built-in Self-test (BIST), especially for in-field self-test applications. In response to the ever-increasing complexities of the modern CPU designs, machine learning algorithms have been proposed to extract processor behavior from simulation data and help constrain ATPG to generate functionally-compatible patterns. However, these simulation-based approaches in general suffer sample inefficiency, i.e., only a small portion of the simulation traces are relevant to fault detection. Inspired by the recent advances in reinforcement learning (RL), we propose an RL-based test program generation technique for transition delay fault (TDF) detection. During the training process, knowledge learned from the simulation data is employed to tune the simulation policy; this close-loop approach significantly improves data efficiency, compared to previous open-loop approaches. Furthermore, RL is capable of dealing with delayed responses, which is common when executing processor instructions. Using the trained RL model, instruction sequences that bring the processor to the fault-sensitizing states, i.e., TDF test patterns, can be generated. The proposed test program generation technique is applied to a MIPS32 processor. For TDF, the fault coverage is 94.94%, which is just 2.57% less than the full-scan based approach.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121600465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00007
Aditya Rohan, K. Basu, R. Karri
Signature and behavior-based anti-virus systems (AVS) are traditionally used to detect Malware. However, these AVS fail to catch metamorphic and polymorphic Malware-which can reconstruct themselves every generation or every instance. We introduce two Machine learning (ML) approaches on system state + instruction sequences – which use hardware debug data – to detect such challenging Malware. Our experiments on hundreds of Intel Malware samples show that the techniques either alone or jointly detect Malware with ≥ 99.5% accuracy.
{"title":"Can Monitoring System State + Counting Custom Instruction Sequences Aid Malware Detection?","authors":"Aditya Rohan, K. Basu, R. Karri","doi":"10.1109/ATS47505.2019.00007","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00007","url":null,"abstract":"Signature and behavior-based anti-virus systems (AVS) are traditionally used to detect Malware. However, these AVS fail to catch metamorphic and polymorphic Malware-which can reconstruct themselves every generation or every instance. We introduce two Machine learning (ML) approaches on system state + instruction sequences – which use hardware debug data – to detect such challenging Malware. Our experiments on hundreds of Intel Malware samples show that the techniques either alone or jointly detect Malware with ≥ 99.5% accuracy.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115557261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ats47505.2019.00008
I. Sengupta
Over the past three decades, ATS has grown to be one of the most significant international forums in the area of testing and diagnosis of circuits, systems and software. It is an honour for us to lead the organization of this conference this year. ATS 2019 continues the tradition of a very competitive review process, high-quality technical papers, stimulating and in-depth tutorials, and a wide variety of industry forum presentations.
{"title":"Message from the ATS 2019 Organizing Co-Chairs","authors":"I. Sengupta","doi":"10.1109/ats47505.2019.00008","DOIUrl":"https://doi.org/10.1109/ats47505.2019.00008","url":null,"abstract":"Over the past three decades, ATS has grown to be one of the most significant international forums in the area of testing and diagnosis of circuits, systems and software. It is an honour for us to lead the organization of this conference this year. ATS 2019 continues the tradition of a very competitive review process, high-quality technical papers, stimulating and in-depth tutorials, and a wide variety of industry forum presentations.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131884271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-01DOI: 10.1109/ATS47505.2019.00022
L. S. D. Araújo, Vinay C. Patil, L. A. J. Marzulo, F. França, S. Kundu
Physically unclonable functions (PUFs) have emerged as lightweight hardware security primitives for implementing secure authentication. Strong PUFs rely on random manufacturing process variation to create unique Boolean mappings from input (challenge) to output (output). For secure authentication, challenge to response mappings are required to be unique for each device. However, uniqueness is not guaranteed by design or manufacturing. Testing for uniqueness and weeding out non-unique parts are the only way to ensure uniqueness of devices. Uniqueness testing can be expensive in time as the challenge-responses of the N th device under-test, must be proven to be different from previously tested N - 1 devices, or the device must be discarded. To reduce the time complexity of uniqueness testing, Multi-Index hashing (MIH) was proposed for online testing in high volume manufacturing. Database search using MIH was shown to be fast, but it suffers from high memory cost. In this paper, we address the memory problem of MIH based uniqueness testing by proposing alternative MIH strategies. Our results indicate that the proposed search strategies can significantly reduce the memory cost without sacrificing performance, requiring ≈ 3.35× less memory with just a 17% performance overhead when testing the uniqueness of 1 million PUFs.
{"title":"Efficient Testing of Physically Unclonable Functions for Uniqueness","authors":"L. S. D. Araújo, Vinay C. Patil, L. A. J. Marzulo, F. França, S. Kundu","doi":"10.1109/ATS47505.2019.00022","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00022","url":null,"abstract":"Physically unclonable functions (PUFs) have emerged as lightweight hardware security primitives for implementing secure authentication. Strong PUFs rely on random manufacturing process variation to create unique Boolean mappings from input (challenge) to output (output). For secure authentication, challenge to response mappings are required to be unique for each device. However, uniqueness is not guaranteed by design or manufacturing. Testing for uniqueness and weeding out non-unique parts are the only way to ensure uniqueness of devices. Uniqueness testing can be expensive in time as the challenge-responses of the N th device under-test, must be proven to be different from previously tested N - 1 devices, or the device must be discarded. To reduce the time complexity of uniqueness testing, Multi-Index hashing (MIH) was proposed for online testing in high volume manufacturing. Database search using MIH was shown to be fast, but it suffers from high memory cost. In this paper, we address the memory problem of MIH based uniqueness testing by proposing alternative MIH strategies. Our results indicate that the proposed search strategies can significantly reduce the memory cost without sacrificing performance, requiring ≈ 3.35× less memory with just a 17% performance overhead when testing the uniqueness of 1 million PUFs.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124580802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Model checking of large designs is a challenging task because of different scalability issues. In this paper, we aim to utilize guided state space traversal to address this issue. However, providing guidance for state space traversal of complex designs is also an equally challenging problem. We adopt a simulation-based strategy combined with Bayesian modelling approach for finding effective guidance hints for state space traversal. A heuristic-based structural dependency of the design yields ineffective guidance hints which need further of filtering. To prune out the ineffective guidance hints, we first generate module-level sub-properties from static analysis of the design. These sub-properties and structural dependency-based guidance hints are analyzed in simulation traces generated from the constrained-random test benches. These conditional occurrence of sub-properties and guidance hints are inputs to a Bayesian model which can then provide us the guidance hints with the highest profitability. With the proposed methodology, we succeed in pruning out the set of unprofitable guidance hints and obtain effective search directions which are then used to assist the model checking procedure. Experiments on two complex designs for different properties show the effectiveness of the proposed methodology in reducing CPU time during model checking.
{"title":"Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification","authors":"S. VineeshV., Binod Kumar, Rushikesh Shinde, Akshay Jaiswal, Harsh Bhargava, Virendra Singh","doi":"10.1109/ATS47505.2019.00023","DOIUrl":"https://doi.org/10.1109/ATS47505.2019.00023","url":null,"abstract":"Model checking of large designs is a challenging task because of different scalability issues. In this paper, we aim to utilize guided state space traversal to address this issue. However, providing guidance for state space traversal of complex designs is also an equally challenging problem. We adopt a simulation-based strategy combined with Bayesian modelling approach for finding effective guidance hints for state space traversal. A heuristic-based structural dependency of the design yields ineffective guidance hints which need further of filtering. To prune out the ineffective guidance hints, we first generate module-level sub-properties from static analysis of the design. These sub-properties and structural dependency-based guidance hints are analyzed in simulation traces generated from the constrained-random test benches. These conditional occurrence of sub-properties and guidance hints are inputs to a Bayesian model which can then provide us the guidance hints with the highest profitability. With the proposed methodology, we succeed in pruning out the set of unprofitable guidance hints and obtain effective search directions which are then used to assist the model checking procedure. Experiments on two complex designs for different properties show the effectiveness of the proposed methodology in reducing CPU time during model checking.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128372742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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