Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213060
Jae Hong Park, J. Choi, M. Kim, J. Chong
This paper proposes an efficient equalizer architecture using the tap allocation memory based on the Kalman algorithm. The equalizer for HDTV channel needs many taps to be adequate for a long delay multipath, which causes a high computational complexity to update the coefficient. We propose a new method that the energy of tap and the channel delay length are observed during training period and then the taps having negligible energy are gradually excluded from the coefficient update. The remaining taps form a new coefficient vector by the tap allocation memory that reduces the computational complexity without any performance degradation. The proposed structure is simulated on the channel of North American terrestrial High Definition Television (HDTV).
{"title":"An efficient equalizer architecture using tap allocation memory for HDTV channel","authors":"Jae Hong Park, J. Choi, M. Kim, J. Chong","doi":"10.1109/IWSOC.2003.1213060","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213060","url":null,"abstract":"This paper proposes an efficient equalizer architecture using the tap allocation memory based on the Kalman algorithm. The equalizer for HDTV channel needs many taps to be adequate for a long delay multipath, which causes a high computational complexity to update the coefficient. We propose a new method that the energy of tap and the channel delay length are observed during training period and then the taps having negligible energy are gradually excluded from the coefficient update. The remaining taps form a new coefficient vector by the tap allocation memory that reduces the computational complexity without any performance degradation. The proposed structure is simulated on the channel of North American terrestrial High Definition Television (HDTV).","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123031730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213015
Peter Waldeck, N. Bergmann
This paper introduces a computer architecture suitable for embedded real-time applications where low power consumption is a requirement. This is achieved through the use of a hybrid hardware-software system. A system architecture is proposed which allows for modules of a system to be implemented in either hardware or software. Implementation choices may be made dynamically based on the loading of the host microprocessor, in a multi-tasking environment. An approach to inter-module communications is described along with how this is affected by dynamic configuration. Acoustic echo cancellation through the use of the maximal length correlation technique is used as an application example. Implementation as a hybrid hardware-software system is examined. An example partitioning arrangement shows total bus bandwidth utilization to be approximately 1%.
{"title":"Dynamic hardware-software partitioning on reconfigurable system-on-chip","authors":"Peter Waldeck, N. Bergmann","doi":"10.1109/IWSOC.2003.1213015","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213015","url":null,"abstract":"This paper introduces a computer architecture suitable for embedded real-time applications where low power consumption is a requirement. This is achieved through the use of a hybrid hardware-software system. A system architecture is proposed which allows for modules of a system to be implemented in either hardware or software. Implementation choices may be made dynamically based on the loading of the host microprocessor, in a multi-tasking environment. An approach to inter-module communications is described along with how this is affected by dynamic configuration. Acoustic echo cancellation through the use of the maximal length correlation technique is used as an application example. Implementation as a hybrid hardware-software system is examined. An example partitioning arrangement shows total bus bandwidth utilization to be approximately 1%.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"570 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123149230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213011
Jhy-Neng Yang, Y. Cheng, Chen-Yi Lee
A CMOS broadband amplifier with high-Q active inductor using 0.25 /spl mu/m CMOS process is presented. In this broadband amplifier, the compact high-Q active inductor is connected to the common-gate configuration to improve the performance of the high power gain, wide bandwidth, low power consumption and simple matching characteristics. Not using any passive inductor components is to be reduced the area of chip and the complexity. Advance Design System (ADS) simulator has been performed to verify the performance of the designed broadband amplifier. It has been shown that the amplifier has a 20 dB(S21) power gain in -3 dB bandwidth, S11 of -17 dB, S22 of -21 dB and noise figure (NF) of 8 dB under 2.5 V power supply with 18 mW power consumption.
{"title":"A design of CMOS broadband amplifier with high-Q active inductor","authors":"Jhy-Neng Yang, Y. Cheng, Chen-Yi Lee","doi":"10.1109/IWSOC.2003.1213011","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213011","url":null,"abstract":"A CMOS broadband amplifier with high-Q active inductor using 0.25 /spl mu/m CMOS process is presented. In this broadband amplifier, the compact high-Q active inductor is connected to the common-gate configuration to improve the performance of the high power gain, wide bandwidth, low power consumption and simple matching characteristics. Not using any passive inductor components is to be reduced the area of chip and the complexity. Advance Design System (ADS) simulator has been performed to verify the performance of the designed broadband amplifier. It has been shown that the amplifier has a 20 dB(S21) power gain in -3 dB bandwidth, S11 of -17 dB, S22 of -21 dB and noise figure (NF) of 8 dB under 2.5 V power supply with 18 mW power consumption.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124276769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1212997
M. Grünewald, Jörg-Christian Niemann, U. Rückert
Performance evaluation is an important step for designing embedded applications that require small footprints, low energy consumption and high throughput. We present a simulation-based method to characterize several resource properties (memory accesses, energy consumption, execution time) of embedded software that runs on dedicated processing engines targeted for SoC designs. The results of the characterization process are back-annotated to the source code to aid the designer in optimizing the implementation. Our approach allows the replacement of software parts by hardware units to speed up processing. We have performed case studies with software and hardware implementations of a pseudo-random number generator and a transmission error detector. The results show that computation speed-ups and energy reductions up to a factor of 15 can be obtained with implementations that exploit hardware extensions.
{"title":"A performance evaluation method for optimizing embedded applications","authors":"M. Grünewald, Jörg-Christian Niemann, U. Rückert","doi":"10.1109/IWSOC.2003.1212997","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1212997","url":null,"abstract":"Performance evaluation is an important step for designing embedded applications that require small footprints, low energy consumption and high throughput. We present a simulation-based method to characterize several resource properties (memory accesses, energy consumption, execution time) of embedded software that runs on dedicated processing engines targeted for SoC designs. The results of the characterization process are back-annotated to the source code to aid the designer in optimizing the implementation. Our approach allows the replacement of software parts by hardware units to speed up processing. We have performed case studies with software and hardware implementations of a pseudo-random number generator and a transmission error detector. The results show that computation speed-ups and energy reductions up to a factor of 15 can be obtained with implementations that exploit hardware extensions.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121252408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213036
O. Cadenas, G. Megson
Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed. Control circuits using a synchronous, a semisynchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.
{"title":"Pullpipelining: a technique for systolic pipelined circuits","authors":"O. Cadenas, G. Megson","doi":"10.1109/IWSOC.2003.1213036","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213036","url":null,"abstract":"Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed. Control circuits using a synchronous, a semisynchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127850773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213049
Suchitav Khadanga
In the wireless communication market, trends are moving towards smaller size, fewer parts, longer lifetime and higher frequency operation. These trends imply that wireless communications circuits must incorporate higher integration and that their design and IC technology must be optimized for low power and high frequency system. One innovative method to increase the frequency of programmable divider is discussed. The new method not only increases the frequency of operation but also decreases circuit complexity and power dissipation. This new design use synchronous counters instead of asynchronous counters. The digital gates are optimized for minimum propagation delay and loading effect using progressive sizing of the transistors. This is better configuration in every aspect in terms of frequency, power dissipation and chip area.
{"title":"Synchronous programmable divider design for PLL using 0.18 /spl mu/m CMOS technology","authors":"Suchitav Khadanga","doi":"10.1109/IWSOC.2003.1213049","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213049","url":null,"abstract":"In the wireless communication market, trends are moving towards smaller size, fewer parts, longer lifetime and higher frequency operation. These trends imply that wireless communications circuits must incorporate higher integration and that their design and IC technology must be optimized for low power and high frequency system. One innovative method to increase the frequency of programmable divider is discussed. The new method not only increases the frequency of operation but also decreases circuit complexity and power dissipation. This new design use synchronous counters instead of asynchronous counters. The digital gates are optimized for minimum propagation delay and loading effect using progressive sizing of the transistors. This is better configuration in every aspect in terms of frequency, power dissipation and chip area.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134402932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213057
M. Sayed, Wael Badawy
This paper presents a new class of Computational RAM (C-RAM) architectures for real-time MPEG-4 applications. The proposed C-RAM architecture consists of an embedded SRAM and number of processing elements working in parallel to process the data stored in the memory. The processing elements are working as a single instruction multiple data (SIMD) architecture. Each processing element is used to process one memory column. The proposed class of C-RAM architectures has been used for MPEG-4 block-based motion estimation, which is the most computational intensive task in the encoder. The proposed architecture has been designed, prototyped, and simulated for 0.18 /spl mu/m CMOS TSMC technology. The simulation results show a promising performance of the proposed class of C-RAM architectures in video coding applications; it can process up to 126 frames per second with clock frequency 100 MHz.
{"title":"A new class of computational RAM architectures for real-time MPEG-4 applications","authors":"M. Sayed, Wael Badawy","doi":"10.1109/IWSOC.2003.1213057","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213057","url":null,"abstract":"This paper presents a new class of Computational RAM (C-RAM) architectures for real-time MPEG-4 applications. The proposed C-RAM architecture consists of an embedded SRAM and number of processing elements working in parallel to process the data stored in the memory. The processing elements are working as a single instruction multiple data (SIMD) architecture. Each processing element is used to process one memory column. The proposed class of C-RAM architectures has been used for MPEG-4 block-based motion estimation, which is the most computational intensive task in the encoder. The proposed architecture has been designed, prototyped, and simulated for 0.18 /spl mu/m CMOS TSMC technology. The simulation results show a promising performance of the proposed class of C-RAM architectures in video coding applications; it can process up to 126 frames per second with clock frequency 100 MHz.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133105480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213070
R. Gulde, M. Weeks
A Position Controller is a device used in many applications, such as controlling the movement of an elevator. In this paper, we examine the technological issues surrounding the development of an integrated circuit of a position control system. This system has been designed using Magic CAD software. The final estimated size after routing is expected to be approximately 9000 x 3250 lambd/sup 2/. The total number of transistors is estimated to be 4850. We are currently in the process of testing this layout with SPICE.
位置控制器是一种在许多应用中使用的设备，例如控制电梯的运动。在本文中，我们研究了围绕位置控制系统集成电路开发的技术问题。本系统是用Magic CAD软件设计的。路由后的最终估计大小预计约为9000 x 3250 lambd/sup 2/。晶体管的总数估计为4850个。我们目前正在用SPICE测试这个布局。
{"title":"A position control system design","authors":"R. Gulde, M. Weeks","doi":"10.1109/IWSOC.2003.1213070","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213070","url":null,"abstract":"A Position Controller is a device used in many applications, such as controlling the movement of an elevator. In this paper, we examine the technological issues surrounding the development of an integrated circuit of a position control system. This system has been designed using Magic CAD software. The final estimated size after routing is expected to be approximately 9000 x 3250 lambd/sup 2/. The total number of transistors is estimated to be 4850. We are currently in the process of testing this layout with SPICE.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128923078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213019
Giuseppe Costantino Giaconia, A. D. Stefano, G. Capponi
A novel application of FPGA to realize digital test equipment is proposed. It takes advantage of the dynamic reconfigurability of FPGAs so easily tailoring custom test functions in the same instrument. This results in high effective, compact and low cost instruments.
{"title":"Reconfigurable digital instrumentation based on FPGA","authors":"Giuseppe Costantino Giaconia, A. D. Stefano, G. Capponi","doi":"10.1109/IWSOC.2003.1213019","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213019","url":null,"abstract":"A novel application of FPGA to realize digital test equipment is proposed. It takes advantage of the dynamic reconfigurability of FPGAs so easily tailoring custom test functions in the same instrument. This results in high effective, compact and low cost instruments.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128668447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213000
L. Behjat, A. Vannelli
Global routing is an essential part of physical design, and has been traditionally formulated to minimize either an estimate of the total wirelength or the channel capacity of a circuit ignoring important issues such as congestion and number of bends. In this paper, a mathematical programming model that combines the wirelength minimization model and the channel capacity minimization model is presented. The combined model is also capable of incorporating different aspects of the global routing problem, such as via-count and congestion in two stages of the global routing problem: route construction and problem formulation. In addition, numerical enhancements have been proposed to increase the speed of the global routing formulation. Experiments on different benchmarks show that the new model builds a flexible and powerful technique that enhances the global routing solution compared to other mathematical programming techniques developed for global routing.
{"title":"Steiner tree construction based on congestion for the global routing problem","authors":"L. Behjat, A. Vannelli","doi":"10.1109/IWSOC.2003.1213000","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213000","url":null,"abstract":"Global routing is an essential part of physical design, and has been traditionally formulated to minimize either an estimate of the total wirelength or the channel capacity of a circuit ignoring important issues such as congestion and number of bends. In this paper, a mathematical programming model that combines the wirelength minimization model and the channel capacity minimization model is presented. The combined model is also capable of incorporating different aspects of the global routing problem, such as via-count and congestion in two stages of the global routing problem: route construction and problem formulation. In addition, numerical enhancements have been proposed to increase the speed of the global routing formulation. Experiments on different benchmarks show that the new model builds a flexible and powerful technique that enhances the global routing solution compared to other mathematical programming techniques developed for global routing.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117127425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：