Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213032
K. Rashid
Adaptive controller based on a multimodel technique is proposed in this paper. Optimal parameters are calculated offline for each zone in the grid plane of a multiunits system and placed in memory storage. The controller tracks the operating conditions and updates the optimal parameters as conditions change. These zones can be considered as reference models for adaptive controllers. The master computer supervises the operating conditions of a single controlled unit from the multiunits system and selects the corresponding optimal feedback gains. This paper illustrates and compare between the classical automatic voltage controls with the proposed adaptive controller over a wide range of operation. The results show that high quality control can be achieved by this technique that should overcome the nonlinearity of complex systems.
{"title":"Multimodels adaptive controller for multivariable systems","authors":"K. Rashid","doi":"10.1109/IWSOC.2003.1213032","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213032","url":null,"abstract":"Adaptive controller based on a multimodel technique is proposed in this paper. Optimal parameters are calculated offline for each zone in the grid plane of a multiunits system and placed in memory storage. The controller tracks the operating conditions and updates the optimal parameters as conditions change. These zones can be considered as reference models for adaptive controllers. The master computer supervises the operating conditions of a single controlled unit from the multiunits system and selects the corresponding optimal feedback gains. This paper illustrates and compare between the classical automatic voltage controls with the proposed adaptive controller over a wide range of operation. The results show that high quality control can be achieved by this technique that should overcome the nonlinearity of complex systems.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114771040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213047
R. Pinto, F. Maloberti
This paper presents a methodology that addresses short-channel effects to design MOSFET circuits. The circuit design is based on a combination of parameter extraction and simple analytical models that allows precise results. The extraction mainly depends on the inversion level, which is independent of geometry, therefore providing points that are applicable to a wide variety of circuits. Trade-offs and design space of the device are clearly brought to the circuit design. Hand calculations and simulations of a common-source amplifier illustrate the methodology.
{"title":"Novel design methodology for short-channel MOSFET analog circuits","authors":"R. Pinto, F. Maloberti","doi":"10.1109/IWSOC.2003.1213047","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213047","url":null,"abstract":"This paper presents a methodology that addresses short-channel effects to design MOSFET circuits. The circuit design is based on a combination of parameter extraction and simple analytical models that allows precise results. The extraction mainly depends on the inversion level, which is independent of geometry, therefore providing points that are applicable to a wide variety of circuits. Trade-offs and design space of the device are clearly brought to the circuit design. Hand calculations and simulations of a common-source amplifier illustrate the methodology.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125854400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213025
Hiroto Saito, S. Nakamura, M. Yoneyama
A speech speed control techniques are used in the various fields such as language training and audio instruments and so on. To realize the speech speed control, there is an easy way that changes a playback speed of a tape-recorder. However, the original speech quality is severely degraded by this method. Currently popular speech speed control method is to change the voice part duration of a speech signal while a pitch period remains. In this paper, we would like to propose a novel approach to change the speech speed due to altering the duration of output of band-pass components.
{"title":"A speech speed control using Fourier composite approach","authors":"Hiroto Saito, S. Nakamura, M. Yoneyama","doi":"10.1109/IWSOC.2003.1213025","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213025","url":null,"abstract":"A speech speed control techniques are used in the various fields such as language training and audio instruments and so on. To realize the speech speed control, there is an easy way that changes a playback speed of a tape-recorder. However, the original speech quality is severely degraded by this method. Currently popular speech speed control method is to change the voice part duration of a speech signal while a pitch period remains. In this paper, we would like to propose a novel approach to change the speech speed due to altering the duration of output of band-pass components.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125870877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213046
L. Jia, A. Cabuk, Jianguo Ma, K. Yeo
A fully integrated 52 GHz millimeter wave LC VCO with -106 dBc/Hz phase noise at 600 kHz offset frequency and 0.93 GHz tuning range is reported in the paper using IBM BiCMOS-6HP technology. The output voltage swing of the VCO is about 0.4 Vp-p for the complementary cross-coupled topology with the buffer. A bipolar device is used as the tail transistor to supply constant a current to preserve the oscillation of the VCO. The parasitics due to interconnect metals are extracted from the layouts, the effects of those parasitics on the VCO's performance are investigated. Based on the analyses, the optimized layout of the complementary VCO is obtained, the pre-layout and the post-layout simulations are compared and presented in this paper.
{"title":"A 52 GHz VCO with low phase noise implemented in SiGe BiCMOS technology","authors":"L. Jia, A. Cabuk, Jianguo Ma, K. Yeo","doi":"10.1109/IWSOC.2003.1213046","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213046","url":null,"abstract":"A fully integrated 52 GHz millimeter wave LC VCO with -106 dBc/Hz phase noise at 600 kHz offset frequency and 0.93 GHz tuning range is reported in the paper using IBM BiCMOS-6HP technology. The output voltage swing of the VCO is about 0.4 Vp-p for the complementary cross-coupled topology with the buffer. A bipolar device is used as the tail transistor to supply constant a current to preserve the oscillation of the VCO. The parasitics due to interconnect metals are extracted from the layouts, the effects of those parasitics on the VCO's performance are investigated. Based on the analyses, the optimized layout of the complementary VCO is obtained, the pre-layout and the post-layout simulations are compared and presented in this paper.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131932978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213040
S. Regimbal, Jean-Francois Lemire, Y. Savaria, G. Bois, E. Aboulhamid, A. Baron
This paper presents a novel approach for functional coverage analysis automation. It is well known that functional verification is a real bottleneck in any digital design development. Consequently, it is necessary to develop new methodologies to increase the quality of functional verification. A metric that measures the functional coverage is specific to each design, and it depends on its functional requirements. Hence, we propose a methodology supported by a tool that automates the coverage analysis at the functional level. Our tool takes as entry a standard executable specification and generates test bench components aimed at performing a functional coverage analysis on a specific design. We use functional metrics as parameters in our tool and apply theses metrics on an executable specification. Using our methodology, we are able to provide a quantitative evaluation of test suites developed to exercise the functionality defined in an executable specification. The application of these test suites on a RTL design improves error detection, through a better exploration of the design. It also increases the degree of confidence in the design.
{"title":"Automating functional coverage analysis based on an executable specification","authors":"S. Regimbal, Jean-Francois Lemire, Y. Savaria, G. Bois, E. Aboulhamid, A. Baron","doi":"10.1109/IWSOC.2003.1213040","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213040","url":null,"abstract":"This paper presents a novel approach for functional coverage analysis automation. It is well known that functional verification is a real bottleneck in any digital design development. Consequently, it is necessary to develop new methodologies to increase the quality of functional verification. A metric that measures the functional coverage is specific to each design, and it depends on its functional requirements. Hence, we propose a methodology supported by a tool that automates the coverage analysis at the functional level. Our tool takes as entry a standard executable specification and generates test bench components aimed at performing a functional coverage analysis on a specific design. We use functional metrics as parameters in our tool and apply theses metrics on an executable specification. Using our methodology, we are able to provide a quantitative evaluation of test suites developed to exercise the functionality defined in an executable specification. The application of these test suites on a RTL design improves error detection, through a better exploration of the design. It also increases the degree of confidence in the design.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133680770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213062
Aman A. Al-Imari, K. Rashid, Najat Hader Al-Egaidy
In this paper the concept of the electromyogram EMG and how the surface electromyogram SEMG signal is obtained have been given. Electromyogram system offers a great benefit to the sport field application. Due to their requirements SEMG systems has been designed and implemented. This system consists of three basic units. These units are: Detection, signal conditioning, and signal processing. It provides measurement of electrical activity of muscles, efficiency of electrical activity, explosion power (response velocity), and fatigue degree. These parameters are most vital to physical assessment in the sports field.
{"title":"Design and implementation of a surface electromyogram system for sport field application","authors":"Aman A. Al-Imari, K. Rashid, Najat Hader Al-Egaidy","doi":"10.1109/IWSOC.2003.1213062","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213062","url":null,"abstract":"In this paper the concept of the electromyogram EMG and how the surface electromyogram SEMG signal is obtained have been given. Electromyogram system offers a great benefit to the sport field application. Due to their requirements SEMG systems has been designed and implemented. This system consists of three basic units. These units are: Detection, signal conditioning, and signal processing. It provides measurement of electrical activity of muscles, efficiency of electrical activity, explosion power (response velocity), and fatigue degree. These parameters are most vital to physical assessment in the sports field.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114053623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213030
A. Armaroli, M. Coppola, M. Diaz-Nava, L. Fanucci
In order to deal with present System on Chip design complexity and short time to market, system level specification/verification techniques and reusable Intellectual Property cores are key factors. To this aim, system level C++ object oriented methodology named IPsim has been developed as a C++ library on top SystemC 2.0. In this paper, the IPsim modeling and simulation of a VDSL modem is presented. Moreover, quantitative comparison between IPsim and behavioral VHDL simulation speed is also performed.
{"title":"High level modeling and simulation of a VDSL modem in SystemC 2.0-IPsim","authors":"A. Armaroli, M. Coppola, M. Diaz-Nava, L. Fanucci","doi":"10.1109/IWSOC.2003.1213030","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213030","url":null,"abstract":"In order to deal with present System on Chip design complexity and short time to market, system level specification/verification techniques and reusable Intellectual Property cores are key factors. To this aim, system level C++ object oriented methodology named IPsim has been developed as a C++ library on top SystemC 2.0. In this paper, the IPsim modeling and simulation of a VDSL modem is presented. Moreover, quantitative comparison between IPsim and behavioral VHDL simulation speed is also performed.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123872216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213048
F. Schlogl, H. Zimmerman
A fully differential 3-stage operational amplifier in 0.12/spl mu/m digital CMOS technology achieving a differential gain in excess of 86dB is presented. This operational amplifier contains only regular-VTh transistors. It uses a pseudo-cascode input differential stage and a pseudo-cascoded load for the high gain. Positive feedback is primarily implemented for a good common-mode rejection. A transit frequency of 46 MHz and a phase margin of 66/spl deg/ at a /spl plusmn/0.6V supply and with a load of 10pF have been measured. The current consumption is less than 1.7mA in the temperature range from -40 to +80/spl deg/C.
{"title":"120nm CMOS operational amplifier with pseudo-cascodes and positive feedback","authors":"F. Schlogl, H. Zimmerman","doi":"10.1109/IWSOC.2003.1213048","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213048","url":null,"abstract":"A fully differential 3-stage operational amplifier in 0.12/spl mu/m digital CMOS technology achieving a differential gain in excess of 86dB is presented. This operational amplifier contains only regular-VTh transistors. It uses a pseudo-cascode input differential stage and a pseudo-cascoded load for the high gain. Positive feedback is primarily implemented for a good common-mode rejection. A transit frequency of 46 MHz and a phase margin of 66/spl deg/ at a /spl plusmn/0.6V supply and with a load of 10pF have been measured. The current consumption is less than 1.7mA in the temperature range from -40 to +80/spl deg/C.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116348070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213043
A. Kassem, J. Wang, A. Khouas, M. Sawan, M. Boukadoum
The real-time ultrasonic imaging system can be achieved using a digital beamforming (DBF) method. The critical part of the DBF is the real-time sampled-delay focusing (SDF) which requires a large number of memories (FIFO) to store the scanned information. The sampled-delay focusing technique is used to eliminate the use of the analog delay lines. This paper concerns the design and implementation of pipelined sampled-delay architecture for ultrasonic digital beamforming. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18 /spl mu/m technology and the resulting active layout area is 0.14 mm/sup 2/, while its total power consumption is below 40 mW.
{"title":"Pipelined sampled-delay focusing CMOS implementation for ultrasonic digital beamforming","authors":"A. Kassem, J. Wang, A. Khouas, M. Sawan, M. Boukadoum","doi":"10.1109/IWSOC.2003.1213043","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213043","url":null,"abstract":"The real-time ultrasonic imaging system can be achieved using a digital beamforming (DBF) method. The critical part of the DBF is the real-time sampled-delay focusing (SDF) which requires a large number of memories (FIFO) to store the scanned information. The sampled-delay focusing technique is used to eliminate the use of the analog delay lines. This paper concerns the design and implementation of pipelined sampled-delay architecture for ultrasonic digital beamforming. The design uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches. The circuit is implemented in CMOS 0.18 /spl mu/m technology and the resulting active layout area is 0.14 mm/sup 2/, while its total power consumption is below 40 mW.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116317931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213054
C. H. Pyoun, Chi-Ho Lin, Hi-Seok Kim, J. Chong
This paper presents the dynamic bus arbiter architecture for a system on chip design. The conventional bus-distribution algorithms, such as the static fixed priority and the round robin, show several defects that are bus starvation, and low system performance because of bus distribution latency in a bus cycle time. The proposed dynamic bus architecture is based on a probability bus distribution algorithm and uses an adaptive ticket value method to solve the impartiality and starvation problems. The simulation results show that the proposed algorithm reduces the buffer size of a master by 11% and decreases the bus latency of a master by 50%.
{"title":"The efficient bus arbitration scheme in SoC environment","authors":"C. H. Pyoun, Chi-Ho Lin, Hi-Seok Kim, J. Chong","doi":"10.1109/IWSOC.2003.1213054","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213054","url":null,"abstract":"This paper presents the dynamic bus arbiter architecture for a system on chip design. The conventional bus-distribution algorithms, such as the static fixed priority and the round robin, show several defects that are bus starvation, and low system performance because of bus distribution latency in a bus cycle time. The proposed dynamic bus architecture is based on a probability bus distribution algorithm and uses an adaptive ticket value method to solve the impartiality and starvation problems. The simulation results show that the proposed algorithm reduces the buffer size of a master by 11% and decreases the bus latency of a master by 50%.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121646587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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