Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213033
J. Heikkinen, Tommi Rantanen, A. Cilio, J. Takala, H. Corporaal
Program code size has become a critical design constraint of embedded systems. Code compression is one of the approaches to reduce the program code size; it results in smaller memories and reduced cost of the chip. In this paper, a code compression method based on instruction templates has been used to improve the code density transport triggered architecture. Six applications taken from different application domains are used for benchmarking. The obtained results show significant improvements in code density.
{"title":"Evaluating template-based instruction compression on transport triggered architectures","authors":"J. Heikkinen, Tommi Rantanen, A. Cilio, J. Takala, H. Corporaal","doi":"10.1109/IWSOC.2003.1213033","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213033","url":null,"abstract":"Program code size has become a critical design constraint of embedded systems. Code compression is one of the approaches to reduce the program code size; it results in smaller memories and reduced cost of the chip. In this paper, a code compression method based on instruction templates has been used to improve the code density transport triggered architecture. Six applications taken from different application domains are used for benchmarking. The obtained results show significant improvements in code density.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126242416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-02DOI: 10.1109/IWSOC.2003.1213013
Sau-Mou Wu, Ron-Yi Liu, Wei-Liang Chen
A high efficient, low power and low phase noise 5.8 GHz LC voltage-controlled oscillator (VCO) for IEEE 802.11a WLAN applications is designed and fabricated in TSMC 0.25 /spl mu/m 1P5M CMOS process. With single 2.5 V supply, it has a tuning range of 240 MHz and a phase noise of -115 dBc/Hz at 1 MHz offset from center frequency throughout the tuning range. The total power consumption is 6.23 mW while the VCO core consumes only 2.62 mW. Compared with the recent proposed works by using the power-frequency-normalized (PFN) figure of merit, it shows a superior phase noise performance while with very low power consumption.
{"title":"A 5.8-GHz high efficient, low power, low phase noise CMOS VCO for IEEE 802.11a","authors":"Sau-Mou Wu, Ron-Yi Liu, Wei-Liang Chen","doi":"10.1109/IWSOC.2003.1213013","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213013","url":null,"abstract":"A high efficient, low power and low phase noise 5.8 GHz LC voltage-controlled oscillator (VCO) for IEEE 802.11a WLAN applications is designed and fabricated in TSMC 0.25 /spl mu/m 1P5M CMOS process. With single 2.5 V supply, it has a tuning range of 240 MHz and a phase noise of -115 dBc/Hz at 1 MHz offset from center frequency throughout the tuning range. The total power consumption is 6.23 mW while the VCO core consumes only 2.62 mW. Compared with the recent proposed works by using the power-frequency-normalized (PFN) figure of merit, it shows a superior phase noise performance while with very low power consumption.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123675540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-30DOI: 10.1109/IWSOC.2003.1212995
Yuanqing Guo, G. Smit, H. Broersma, P. M. Heysters
The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation method to extract functional equivalent structures, i.e. templates, from a control data flow graph. By inspecting the graph the algorithm generates all the possible templates and the corresponding matches. Using unique serial numbers and circle numbers the algorithm can find all distinct templates with multiple outputs. The template selection algorithm shows how this information can be used in compilers for reconfigurable systems. The objective of the template selection algorithm is to find an efficient cover for an application graph with a minimal number of distinct templates and minimal number of matches.
{"title":"Template generation and selection algorithms","authors":"Yuanqing Guo, G. Smit, H. Broersma, P. M. Heysters","doi":"10.1109/IWSOC.2003.1212995","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1212995","url":null,"abstract":"The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation method to extract functional equivalent structures, i.e. templates, from a control data flow graph. By inspecting the graph the algorithm generates all the possible templates and the corresponding matches. Using unique serial numbers and circle numbers the algorithm can find all distinct templates with multiple outputs. The template selection algorithm shows how this information can be used in compilers for reconfigurable systems. The objective of the template selection algorithm is to find an efficient cover for an application graph with a minimal number of distinct templates and minimal number of matches.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131629432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWSOC.2003.1213024
M. Maamoun, A. Benbelkacem, D. Berkani, A. Guessoum
This work develops a new technique for interfacing the data exchange between the microprocessor-based systems and the external devices. This technique exploits the great capacity of interfacing of Extended Physical Addressing and uses the technique of Direct Memory Access (DMA), increases the frequency of the new bus and improves the speed of data exchange. This Fast Physical Addressing, based on the use of software/hardware system in the microprocessor-based system, has two aims. First, the management of a large external memory capacity, with a reduced use of physical addresses of the microprocessor-based system. Second, the increase of the data exchange speed compared to the Extended Physical Addressing. While using this architecture in microprocessor-based system or in computer, the input of the hardware part of our system will be connected to the bus system, and the output, which is a new bus, will be connected to an external device. The new bus is composed of a data bus, a control bus and an address bus.
{"title":"Interfacing in microprocessor-based systems with a fast physical addressing","authors":"M. Maamoun, A. Benbelkacem, D. Berkani, A. Guessoum","doi":"10.1109/IWSOC.2003.1213024","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213024","url":null,"abstract":"This work develops a new technique for interfacing the data exchange between the microprocessor-based systems and the external devices. This technique exploits the great capacity of interfacing of Extended Physical Addressing and uses the technique of Direct Memory Access (DMA), increases the frequency of the new bus and improves the speed of data exchange. This Fast Physical Addressing, based on the use of software/hardware system in the microprocessor-based system, has two aims. First, the management of a large external memory capacity, with a reduced use of physical addresses of the microprocessor-based system. Second, the increase of the data exchange speed compared to the Extended Physical Addressing. While using this architecture in microprocessor-based system or in computer, the input of the hardware part of our system will be connected to the bus system, and the output, which is a new bus, will be connected to an external device. The new bus is composed of a data bus, a control bus and an address bus.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121343649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWSOC.2003.1212994
The following topics are dealt with: SoC design methodologies, SoC physical design, low power SoCs, arithmetic techniques, analog and mixed signals, reconfigurable hardware, digital circuits, SoC applications, modeling issues in SoCs, embedded processors, sensors, interconnect, memory techniques for SoCs, SoC medical applications and SoC testing.
{"title":"Proceedings 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications","authors":"","doi":"10.1109/IWSOC.2003.1212994","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1212994","url":null,"abstract":"The following topics are dealt with: SoC design methodologies, SoC physical design, low power SoCs, arithmetic techniques, analog and mixed signals, reconfigurable hardware, digital circuits, SoC applications, modeling issues in SoCs, embedded processors, sensors, interconnect, memory techniques for SoCs, SoC medical applications and SoC testing.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133974601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWSOC.2003.1213010
S. M. Rezaul Hasan
This paper describes a novel low noise CMOS current feed-back transimpedance amplifier using a low-cost Agilent 0.5 /spl mu/m 3M2p CMOS process technology. The bandwidth of the amplifier was extended using inductive peaking technique and simulation results indicated a -3 dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/ 60 dB ohms. The dynamic range of the amplifier was high enough to enable an output voltage swing of around 400 mV for a test input current of 100 /spl mu/A. The output noise voltage spectral density was 12 nV/sqrt(Hz) (with a peak of /spl ap/ 25 nV/sqrt(Hz)), while the input referred noise current spectral density was below 20 pA/sqrt(Hz) within the amplifier frequency band.
{"title":"A high performance wide-band CMOS transimpedance amplifier for optical transceivers","authors":"S. M. Rezaul Hasan","doi":"10.1109/IWSOC.2003.1213010","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213010","url":null,"abstract":"This paper describes a novel low noise CMOS current feed-back transimpedance amplifier using a low-cost Agilent 0.5 /spl mu/m 3M2p CMOS process technology. The bandwidth of the amplifier was extended using inductive peaking technique and simulation results indicated a -3 dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/ 60 dB ohms. The dynamic range of the amplifier was high enough to enable an output voltage swing of around 400 mV for a test input current of 100 /spl mu/A. The output noise voltage spectral density was 12 nV/sqrt(Hz) (with a peak of /spl ap/ 25 nV/sqrt(Hz)), while the input referred noise current spectral density was below 20 pA/sqrt(Hz) within the amplifier frequency band.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125969133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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