Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213061
Aman A. Al-Imari, K. Rashid, Mohammed Al-Dagstany
The paper presents design and implementation of a telemetry system for measurement and monitoring of bioelectric signals such as EEG, ECG or EMG. The proposed system consists of two parts, a portable part and a stationary part. The transmitter uses a pair of 2.8v lithium D cell batteries and can operate for 1.5 months before replacement. The stationary part consists of a commercial radio receiver. The signals can be plotted (using x-y plotter), displayed (using a conventional analogue CRT), or sent to PC system for further processing and interpretation. The design details of the circuits are presented together with the essential operational software of the system. The performance of the proposed system is practically assessed. This is achieved by connecting the patient's body to the system through bipolar surface electrodes. The bioelectric signals are successfully picked up within the range of the used electrodes.
{"title":"Telemetry based system for measurement and monitoring of biomedical signals","authors":"Aman A. Al-Imari, K. Rashid, Mohammed Al-Dagstany","doi":"10.1109/IWSOC.2003.1213061","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213061","url":null,"abstract":"The paper presents design and implementation of a telemetry system for measurement and monitoring of bioelectric signals such as EEG, ECG or EMG. The proposed system consists of two parts, a portable part and a stationary part. The transmitter uses a pair of 2.8v lithium D cell batteries and can operate for 1.5 months before replacement. The stationary part consists of a commercial radio receiver. The signals can be plotted (using x-y plotter), displayed (using a conventional analogue CRT), or sent to PC system for further processing and interpretation. The design details of the circuits are presented together with the essential operational software of the system. The performance of the proposed system is practically assessed. This is achieved by connecting the patient's body to the system through bipolar surface electrodes. The bioelectric signals are successfully picked up within the range of the used electrodes.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126049428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213001
Dorothy Kucar, A. Vannelli
In physical design software, it is often necessary to estimate net, i.e. interconnection delays. Interconnections are typically modelled as lumped RC circuits. This approximation is reasonable in technologies where overall delay is dominated by gate delays. With present sub 130 nm technologies, characteristic signal propagation lengths are comparable to signal wavelengths. Interconnections no longer allow currents to flow through efficiently, resulting in a conspiracy of capacitative, resistive and inductive effects. In recent years, more accurate interconnections models, that approximate an interconnection as n distributed RLC segments, have been devised. In this work, we let the number of segments go to infinity and obtain exact expressions for voltages. In particular, we present a mathematically rigorous time-domain analysis of the Lossy Transmission Line Model.
{"title":"Interconnection modelling using distributed RLC models","authors":"Dorothy Kucar, A. Vannelli","doi":"10.1109/IWSOC.2003.1213001","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213001","url":null,"abstract":"In physical design software, it is often necessary to estimate net, i.e. interconnection delays. Interconnections are typically modelled as lumped RC circuits. This approximation is reasonable in technologies where overall delay is dominated by gate delays. With present sub 130 nm technologies, characteristic signal propagation lengths are comparable to signal wavelengths. Interconnections no longer allow currents to flow through efficiently, resulting in a conspiracy of capacitative, resistive and inductive effects. In recent years, more accurate interconnections models, that approximate an interconnection as n distributed RLC segments, have been devised. In this work, we let the number of segments go to infinity and obtain exact expressions for voltages. In particular, we present a mathematically rigorous time-domain analysis of the Lossy Transmission Line Model.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127174719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213014
S. Machan
A fully differential 2.4-GHz 8/9 dual modulus prescaler is presented in this paper. The circuit has been constructed in a 0.18 /spl mu/m 1.8 V CMOS process for use in a low-power ISM transceiver. The prescaler consists of internal buffering, the divider itself, a differential to CMOS converter, and a self-contained current source. Simulations imply a maximum operating frequency of 3.05 GHz which is the measurement of the silicon support. Its simulated current drain is 2.5 mA and it occupies an area of 130 /spl mu/m /spl times/ 60 /spl mu/m.
{"title":"A low-power fully differential 2.4-GHz prescaler in 0.18 /spl mu/m CMOS technology","authors":"S. Machan","doi":"10.1109/IWSOC.2003.1213014","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213014","url":null,"abstract":"A fully differential 2.4-GHz 8/9 dual modulus prescaler is presented in this paper. The circuit has been constructed in a 0.18 /spl mu/m 1.8 V CMOS process for use in a low-power ISM transceiver. The prescaler consists of internal buffering, the divider itself, a differential to CMOS converter, and a self-contained current source. Simulations imply a maximum operating frequency of 3.05 GHz which is the measurement of the silicon support. Its simulated current drain is 2.5 mA and it occupies an area of 130 /spl mu/m /spl times/ 60 /spl mu/m.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133777253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213008
B. Andreev, E. Titlebaum, E. Friedman
The VLSI implementation of arithmetic operations may be significantly improved by using non-conventional number representations and transforming intermediate results from one format to another format. For a target function, the objective is to change the number representations of the input and output operands such that a minimum amount of logic circuitry is required to achieve a computation. Redundant arithmetic has received increasing interest in the past decade to reduce or eliminate carry propagation chains. The development of an analytical framework that expands the scope of functions that can be efficiently implemented using signed-binary representation is discussed in this paper. Implementation details are described that demonstrate the application of these results. Particular attention is placed on realizing the (a + b), -(a + b), (a - b), and -(a - b) functions in a complex /spl plusmn/1 multiplier serving as a pseudonoise code scrambler in wireless CDMA transceivers.
{"title":"Transformations of signed-binary number representations for efficient VLSI arithmetic","authors":"B. Andreev, E. Titlebaum, E. Friedman","doi":"10.1109/IWSOC.2003.1213008","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213008","url":null,"abstract":"The VLSI implementation of arithmetic operations may be significantly improved by using non-conventional number representations and transforming intermediate results from one format to another format. For a target function, the objective is to change the number representations of the input and output operands such that a minimum amount of logic circuitry is required to achieve a computation. Redundant arithmetic has received increasing interest in the past decade to reduce or eliminate carry propagation chains. The development of an analytical framework that expands the scope of functions that can be efficiently implemented using signed-binary representation is discussed in this paper. Implementation details are described that demonstrate the application of these results. Particular attention is placed on realizing the (a + b), -(a + b), (a - b), and -(a - b) functions in a complex /spl plusmn/1 multiplier serving as a pseudonoise code scrambler in wireless CDMA transceivers.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114632463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213068
N. B. Rizvandi, A. Nabavi
A power efficient multistage digital decimation filter for an ADSL modem is presented. In this design, a fractional delay (FD) filter with complex coefficients, a symmetric FIR filter, and a shift register are used to meet the requirements of the G.232 standard. The multistage architecture of the decimation filter consumes less than 28% of power consumed by single-stage implementation for oversampling ratio of 16. Although the order of the designed filter is low (16), it provides very accurate magnitude and group delay responses within the passband.
{"title":"Design, simulation and implementation of a low-power digital decimation filter for G.232 standard","authors":"N. B. Rizvandi, A. Nabavi","doi":"10.1109/IWSOC.2003.1213068","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213068","url":null,"abstract":"A power efficient multistage digital decimation filter for an ADSL modem is presented. In this design, a fractional delay (FD) filter with complex coefficients, a symmetric FIR filter, and a shift register are used to meet the requirements of the G.232 standard. The multistage architecture of the decimation filter consumes less than 28% of power consumed by single-stage implementation for oversampling ratio of 16. Although the order of the designed filter is low (16), it provides very accurate magnitude and group delay responses within the passband.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133818914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213042
V. Matko
In response to a need for a more accurate porosity measuring method for small solid samples (approximately 1 g in mass) the porosity measurement sensor using a sensitive capacitive-dependent crystal was developed. This paper presents the new sensor and the probe sensitivity, frequency dependence on the volume. In addition, the new idea of excitation of the entire sensor with stochastic test signals is described, and the porosity measuring method is provided. The latter includes the influence of test signals on the weighting function uncertainty. The experimental results of the porosity determination in volcanic rock samples are presented. The uncertainty of the porosity measurement is less than 0.1 % in the temperature range 10-30 /spl deg/C.
{"title":"Porosity sensor by using quartz crystals and two excitation signals","authors":"V. Matko","doi":"10.1109/IWSOC.2003.1213042","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213042","url":null,"abstract":"In response to a need for a more accurate porosity measuring method for small solid samples (approximately 1 g in mass) the porosity measurement sensor using a sensitive capacitive-dependent crystal was developed. This paper presents the new sensor and the probe sensitivity, frequency dependence on the volume. In addition, the new idea of excitation of the entire sensor with stochastic test signals is described, and the porosity measuring method is provided. The latter includes the influence of test signals on the weighting function uncertainty. The experimental results of the porosity determination in volcanic rock samples are presented. The uncertainty of the porosity measurement is less than 0.1 % in the temperature range 10-30 /spl deg/C.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121911122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213053
P. Pande, C. Grecu, A. Ivanov
System on Chip (SoC) design in the forthcoming billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. The success of this approach depends on the seamless integration of cores like processors, memories, UARTs, etc. Some of the main problems in future SoC designs arise from non scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues and difficulties associated with non scalable bus-based functional interconnects. These problems can be addressed by using a network-centric approach to design SoCs, where instead of global wiring, IP blocks are integrated using a switch-based on-chip interconnection network. One of the major concerns with interconnection networks is throughput degradation due to idle physical channels. By introducing the concept of virtual channels in an on-chip interconnection network, the overall throughput of the SoC can be improved. To achieve this throughput improvement, extra silicon area is required but the overall area consumed by the switches can be made to amount to a very small portion of a billion transistor SoC.
{"title":"High-throughput switch-based interconnect for future SoCs","authors":"P. Pande, C. Grecu, A. Ivanov","doi":"10.1109/IWSOC.2003.1213053","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213053","url":null,"abstract":"System on Chip (SoC) design in the forthcoming billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. The success of this approach depends on the seamless integration of cores like processors, memories, UARTs, etc. Some of the main problems in future SoC designs arise from non scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues and difficulties associated with non scalable bus-based functional interconnects. These problems can be addressed by using a network-centric approach to design SoCs, where instead of global wiring, IP blocks are integrated using a switch-based on-chip interconnection network. One of the major concerns with interconnection networks is throughput degradation due to idle physical channels. By introducing the concept of virtual channels in an on-chip interconnection network, the overall throughput of the SoC can be improved. To achieve this throughput improvement, extra silicon area is required but the overall area consumed by the switches can be made to amount to a very small portion of a billion transistor SoC.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125851856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213069
F. Bernardinis, L. Fanucci, T. Ramacciotti, P. Terreni
In this paper we describe the implementation of a scheduler capable of Quality of Service (QoS) management on the Intel IXP 1200 network processor. First, the scheduling algorithm PTTSD is introduced at the abstract level showing its characteristics and complexity. Then, the IXP architecture is briefly described with the purpose of refining the PTTSD algorithm in order to provide a more efficient implementation. The refined PTTSD scheduler has been implemented on top of the reference design provided by Intel. The dependency of the adopted software architecture on the IXP network processor is analyzed and, finally, the implementation is described. A set of characterization tests is reported to demonstrate the efficiency of the implementation and the effectiveness of the Intel architecture to implement flexible QoS routers.
{"title":"A QoS Internet protocol scheduler on the IXP1200 network platform","authors":"F. Bernardinis, L. Fanucci, T. Ramacciotti, P. Terreni","doi":"10.1109/IWSOC.2003.1213069","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213069","url":null,"abstract":"In this paper we describe the implementation of a scheduler capable of Quality of Service (QoS) management on the Intel IXP 1200 network processor. First, the scheduling algorithm PTTSD is introduced at the abstract level showing its characteristics and complexity. Then, the IXP architecture is briefly described with the purpose of refining the PTTSD algorithm in order to provide a more efficient implementation. The refined PTTSD scheduler has been implemented on top of the reference design provided by Intel. The dependency of the adopted software architecture on the IXP network processor is analyzed and, finally, the implementation is described. A set of characterization tests is reported to demonstrate the efficiency of the implementation and the effectiveness of the Intel architecture to implement flexible QoS routers.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123051964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213018
M. Sadasivam, Sangjin Hong
This paper presents an application specific reconfigurable architecture based on coarse-grain FPGA for real-time parallel particle filters. The architecture consists of a set of heterogeneous arithmetic units and buffer banks, where their interconnections are reconfigurable at the hardware level. The proposed architecture separates fixed and reconfigurable units for high-throughput realization. We compare potential throughput of the design with that of commercial FPGAs and DSPs. The proposed architecture is implemented in 0.25 /spl mu/m CMOS process.
{"title":"Application specific coarse-grained FPGA for processing element in real time parallel particle filters","authors":"M. Sadasivam, Sangjin Hong","doi":"10.1109/IWSOC.2003.1213018","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213018","url":null,"abstract":"This paper presents an application specific reconfigurable architecture based on coarse-grain FPGA for real-time parallel particle filters. The architecture consists of a set of heterogeneous arithmetic units and buffer banks, where their interconnections are reconfigurable at the hardware level. The proposed architecture separates fixed and reconfigurable units for high-throughput realization. We compare potential throughput of the design with that of commercial FPGAs and DSPs. The proposed architecture is implemented in 0.25 /spl mu/m CMOS process.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116951934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213039
C. Panis, Raimund Leitner, J. Nurmi
SoC (System-on-Chip) applications map complex system functions on a single die. The increasing importance of flexibility in SoC applications leads to raising portion implemented in firmware. Therefore, the demand on computational power of the embedded processors in the application is increasing. The newest silicon technologies (e.g. 0.13 /spl mu/m and lower) help to increase the reachable frequency, but the demand cannot be sufficiently satisfied. One approach to increase the processor frequency is the introduction of pipelining. To guarantee data consistency in deep pipelined processors different methods have been developed. Additional complexity is introduced by the occurrence of interrupts. This paper describes a concept to enable data consistency between the instructions of different pipeline stages in pipelined DSP kernels during interrupt service routines, without the interaction of the DSP itself and with no restrictions concerning the nesting level of the interrupts. The scaleable shadow stack is part of a development project for a configurable DSP concept.
{"title":"Scaleable shadow stack for a configurable DSP concept","authors":"C. Panis, Raimund Leitner, J. Nurmi","doi":"10.1109/IWSOC.2003.1213039","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213039","url":null,"abstract":"SoC (System-on-Chip) applications map complex system functions on a single die. The increasing importance of flexibility in SoC applications leads to raising portion implemented in firmware. Therefore, the demand on computational power of the embedded processors in the application is increasing. The newest silicon technologies (e.g. 0.13 /spl mu/m and lower) help to increase the reachable frequency, but the demand cannot be sufficiently satisfied. One approach to increase the processor frequency is the introduction of pipelining. To guarantee data consistency in deep pipelined processors different methods have been developed. Additional complexity is introduced by the occurrence of interrupts. This paper describes a concept to enable data consistency between the instructions of different pipeline stages in pipelined DSP kernels during interrupt service routines, without the interaction of the DSP itself and with no restrictions concerning the nesting level of the interrupts. The scaleable shadow stack is part of a development project for a configurable DSP concept.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116928306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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