Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213044
J. Calvano, M. Lubaszewski
Conceptually, signal processors are systems, with reasonable complexity, were different mathematical operations are performed over signals derived from different origins. This paper presents the preliminary results for a Design for Test Methodology for analog signal processors, which can be used for MEMS and for the basic electronic circuitry around the micromachine core. The methodology is based on an analysis and a synthesis recursive process, which guarantees a good trade-of between extra structures, used to implement built-in self-test features in the original design. Basically, the whole design process is founded over the building of a system, with structural blocks, with a dynamic behavior of 1st and 2nd order.
{"title":"Designing for test analog signal processors for MEMS-based inertial sensors","authors":"J. Calvano, M. Lubaszewski","doi":"10.1109/IWSOC.2003.1213044","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213044","url":null,"abstract":"Conceptually, signal processors are systems, with reasonable complexity, were different mathematical operations are performed over signals derived from different origins. This paper presents the preliminary results for a Design for Test Methodology for analog signal processors, which can be used for MEMS and for the basic electronic circuitry around the micromachine core. The methodology is based on an analysis and a synthesis recursive process, which guarantees a good trade-of between extra structures, used to implement built-in self-test features in the original design. Basically, the whole design process is founded over the building of a system, with structural blocks, with a dynamic behavior of 1st and 2nd order.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133085781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213021
Shih-Chang Hsia
Currently, a comparison function has been widely used for discrete signal processing. In this study, a novel comparison-cell is presented based on clocking concept. The advantages are that the circuit complexity can be largely reduced and the delay time becomes shorter. The prototype cell is designed for 4-bit comparison cell using Spice simulator. As comparisons with CMOS base, the complexity of proposed cell is reduced to one-third, and the circuit delay can be shortened to half. With a regular design, the prototype of 4/spl times/6 comparison circuit is implemented based on 4-bit basic cell. The chip core is about 0.9mm/sup 2/ using UMC 0.5 /spl mu/m process.
{"title":"A high speed multi-input comparator with clocking-charge based for low-power systems","authors":"Shih-Chang Hsia","doi":"10.1109/IWSOC.2003.1213021","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213021","url":null,"abstract":"Currently, a comparison function has been widely used for discrete signal processing. In this study, a novel comparison-cell is presented based on clocking concept. The advantages are that the circuit complexity can be largely reduced and the delay time becomes shorter. The prototype cell is designed for 4-bit comparison cell using Spice simulator. As comparisons with CMOS base, the complexity of proposed cell is reduced to one-third, and the circuit delay can be shortened to half. With a regular design, the prototype of 4/spl times/6 comparison circuit is implemented based on 4-bit basic cell. The chip core is about 0.9mm/sup 2/ using UMC 0.5 /spl mu/m process.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125211048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213017
N. Bergmann, Peter Waldeck, John A. Williams
The new technology of reconfigurable System-on-Chip is shown to be a good match to the requirements of real-time embedded systems. In particular, the judicious use of specialized data processing peripherals can reduce the CPU load significantly and greatly ease the task of guaranteeing that real-time deadlines are met in complex multiprocessing real-time systems. A catalog of other possible uses for the reconfigurable logic resources on such a chip which can assist in improving real-time system performance is also presented.
{"title":"A catalog of hardware acceleration techniques for real-time reconfigurable system on chip","authors":"N. Bergmann, Peter Waldeck, John A. Williams","doi":"10.1109/IWSOC.2003.1213017","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213017","url":null,"abstract":"The new technology of reconfigurable System-on-Chip is shown to be a good match to the requirements of real-time embedded systems. In particular, the judicious use of specialized data processing peripherals can reduce the CPU load significantly and greatly ease the task of guaranteeing that real-time deadlines are met in complex multiprocessing real-time systems. A catalog of other possible uses for the reconfigurable logic resources on such a chip which can assist in improving real-time system performance is also presented.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134102912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213006
A. T. Abdel-Hamid, S. Tahar, E. Aboulhamid
Intellectual property (IP) block reuse is essential for facilitating the design process of System-on-a-Chip. Sharing IP blocks in such a competitive market poses significant high security risks. IPs can be read, copied or even partitioned to cover the authorship proof. Creators and owners of IP designs want assurance that their content will not be illegally redistributed by consumers. Consumers, on the other hand, want assurance that the content they buy is legitimate. Digital watermarking, used with most of the shared digital media, has emerged as a candidate solution for helping copyright protection of IP blocks. In this paper, we outline IP watermarking and survey the current state-of- the-art of different schemes and algorithms. We also highlight the main technical problems that should be solved in order to let IP watermarking be used widely in industry.
{"title":"IP watermarking techniques: survey and comparison","authors":"A. T. Abdel-Hamid, S. Tahar, E. Aboulhamid","doi":"10.1109/IWSOC.2003.1213006","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213006","url":null,"abstract":"Intellectual property (IP) block reuse is essential for facilitating the design process of System-on-a-Chip. Sharing IP blocks in such a competitive market poses significant high security risks. IPs can be read, copied or even partitioned to cover the authorship proof. Creators and owners of IP designs want assurance that their content will not be illegally redistributed by consumers. Consumers, on the other hand, want assurance that the content they buy is legitimate. Digital watermarking, used with most of the shared digital media, has emerged as a candidate solution for helping copyright protection of IP blocks. In this paper, we outline IP watermarking and survey the current state-of- the-art of different schemes and algorithms. We also highlight the main technical problems that should be solved in order to let IP watermarking be used widely in industry.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132891236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213023
P. Wijetunga
A new low-swing pass-transistor logic style for designing high-performance crossbar switches for system-on-chip applications is proposed. The new pass-transistor architecture uses current-switching and end-to-end swing restoration to improve the crossbar performance. The architecture is verified in 0.35 and 0.25 /spl mu/m CMOS technology. The 4-b 4x4 crossbar switch in 0.35 /spl mu/m CMOS occupied an area of 1.4 /spl mu/m/sup 2/ and achieved 36 Gb/s. Analysis suggests that the new logic style can be used to design multi-Tb/s crossbar switches in 0.18 /spl mu/m and lower CMOS technology.
{"title":"High-performance crossbar design for system-on-chip","authors":"P. Wijetunga","doi":"10.1109/IWSOC.2003.1213023","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213023","url":null,"abstract":"A new low-swing pass-transistor logic style for designing high-performance crossbar switches for system-on-chip applications is proposed. The new pass-transistor architecture uses current-switching and end-to-end swing restoration to improve the crossbar performance. The architecture is verified in 0.35 and 0.25 /spl mu/m CMOS technology. The 4-b 4x4 crossbar switch in 0.35 /spl mu/m CMOS occupied an area of 1.4 /spl mu/m/sup 2/ and achieved 36 Gb/s. Analysis suggests that the new logic style can be used to design multi-Tb/s crossbar switches in 0.18 /spl mu/m and lower CMOS technology.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122656274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213029
M. Karray, P. Desgreys, J. Charlot
A CMOS inverter transimpedance TIA, also known as current feedback amplifier, is described. This amplifier has features of high bandwidth and high transimpedance-bandwidth product. A model of photodiode and TIA are presented.
{"title":"A CMOS inverter TIA modeling with VHDL-AMS","authors":"M. Karray, P. Desgreys, J. Charlot","doi":"10.1109/IWSOC.2003.1213029","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213029","url":null,"abstract":"A CMOS inverter transimpedance TIA, also known as current feedback amplifier, is described. This amplifier has features of high bandwidth and high transimpedance-bandwidth product. A model of photodiode and TIA are presented.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"371 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122774099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213022
Dae-Ik Kim, Myung-Whan An, Ho-Yong Chung, Suk-Young Kim
The performance of communication systems should be tested against a set of requirements. To this end, noise generation systems are used to generate noise signals with specified characteristics. In this paper, area efficient noise generation system based on DCT is proposed. It is shown that the proposed structure results in a reduction in the area by 61-64% except DCT block. Also, the proposed structure can reduce power consumption by eliminating unnecessary operations in some blocks of the noise generation system.
{"title":"Area efficient implementation of noise generation system","authors":"Dae-Ik Kim, Myung-Whan An, Ho-Yong Chung, Suk-Young Kim","doi":"10.1109/IWSOC.2003.1213022","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213022","url":null,"abstract":"The performance of communication systems should be tested against a set of requirements. To this end, noise generation systems are used to generate noise signals with specified characteristics. In this paper, area efficient noise generation system based on DCT is proposed. It is shown that the proposed structure results in a reduction in the area by 61-64% except DCT block. Also, the proposed structure can reduce power consumption by eliminating unnecessary operations in some blocks of the noise generation system.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115913545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213045
B. Georgescu, J. Nakaska, R. Randall, J. Haslett
Bluetooth is a communications standard targeting shortrange wireless communications with data rates of 1Mb/s at 10m distance. To encourage Canadian universities to pursue this commercially promising standard the Canadian Microelectronics Corporation is providing the intellectual property for a Bluetooth SOC Reference Platform. This platform does not currently include an RF transceiver core. This work describes a research effort made at the University of Calgary to build a compatible RF transceiver core in a CMOS 0.18/spl mu/m process. A brief Bluetooth specification translation process is presented. A pilot PCB Bluetooth frequency synthesizer is presented together with specific measurements made at NEWT, TRLabs' new test and measurement facility. Finally, a fully integrated Bluetooth frequency synthesizer implemented in a CMOS 0.18/spl mu/m process is presented.
{"title":"A 0.18/spl mu/m CMOS Bluetooth frequency synthesizer for integration with a Bluetooth SOC reference platform","authors":"B. Georgescu, J. Nakaska, R. Randall, J. Haslett","doi":"10.1109/IWSOC.2003.1213045","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213045","url":null,"abstract":"Bluetooth is a communications standard targeting shortrange wireless communications with data rates of 1Mb/s at 10m distance. To encourage Canadian universities to pursue this commercially promising standard the Canadian Microelectronics Corporation is providing the intellectual property for a Bluetooth SOC Reference Platform. This platform does not currently include an RF transceiver core. This work describes a research effort made at the University of Calgary to build a compatible RF transceiver core in a CMOS 0.18/spl mu/m process. A brief Bluetooth specification translation process is presented. A pilot PCB Bluetooth frequency synthesizer is presented together with specific measurements made at NEWT, TRLabs' new test and measurement facility. Finally, a fully integrated Bluetooth frequency synthesizer implemented in a CMOS 0.18/spl mu/m process is presented.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122330086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1212999
Bill Halpin, Naresh Sehgal, C. Y. Chen
Increasing demands created by Systems-On-Chip (SOC) and process advances have increased the difficulty of timing driven placement. The primary issue in SOC is timing closure. This requires us to look at timing at all design levels, especially placement. Recently, several promising approaches for timing-driven placement have been presented using net length constraints for timing optimization (Alpert et al., 2001). A Net Length Constraint (NLC) is an upper limit on a net's length. These net-constrained global placement techniques give excellent timing results by meeting NLCs on timing-critical nets. These works focused only on global NLC placement. Detailed placement and legalization are important steps in the placement flow. Current algorithms, which are not NLC aware, give back the gains from global NLC placement. The contributions of this paper are a new NLC global placement rebalancing method and two detailed placement algorithms that work in conjunction with the recursive bisection net-constrained global placer (Alpert et al., 2001). The first detailed placer uses grid-based placement and transportation solving to assign instances to the grid. The second detailed placer uses simulated annealing to optimize placement for NLC. On benchmark circuits from MCNC and Intel Corporation, the grid and simulated annealing placers are able to achieve placements which exceed constraints by, on average only, 2.7% and 1.9%, respectively.
片上系统(SOC)和工艺进步带来的日益增长的需求增加了定时驱动放置的难度。SOC的主要问题是定时关闭。这就要求我们在所有设计层面都考虑时间，尤其是布局。最近，已经提出了几种有前途的时间驱动放置方法，使用净长度约束进行时间优化(Alpert et al.， 2001)。网长约束(NLC)是对网长的上限限制。这些网络约束的全局布局技术通过满足时间关键网络上的NLCs，获得了出色的时序结果。这些工作只关注全球NLC安置。详细安置和合法化是安置流程中的重要步骤。目前的算法不能感知NLC，会使全局NLC放置的收益倒退。本文的贡献是一种新的NLC全局布局再平衡方法和两种详细的布局算法，这些算法与递归平分网约束的全局布局相结合(Alpert et al.， 2001)。第一个详细的placer使用基于网格的放置和传输求解来将实例分配到网格。第二个详细的砂矿使用模拟退火来优化NLC的放置。在MCNC和Intel公司的基准电路上，网格和模拟退火放置器能够实现超出约束的放置，平均分别仅为2.7%和1.9%。
{"title":"Detailed placement with net length constraints","authors":"Bill Halpin, Naresh Sehgal, C. Y. Chen","doi":"10.1109/IWSOC.2003.1212999","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1212999","url":null,"abstract":"Increasing demands created by Systems-On-Chip (SOC) and process advances have increased the difficulty of timing driven placement. The primary issue in SOC is timing closure. This requires us to look at timing at all design levels, especially placement. Recently, several promising approaches for timing-driven placement have been presented using net length constraints for timing optimization (Alpert et al., 2001). A Net Length Constraint (NLC) is an upper limit on a net's length. These net-constrained global placement techniques give excellent timing results by meeting NLCs on timing-critical nets. These works focused only on global NLC placement. Detailed placement and legalization are important steps in the placement flow. Current algorithms, which are not NLC aware, give back the gains from global NLC placement. The contributions of this paper are a new NLC global placement rebalancing method and two detailed placement algorithms that work in conjunction with the recursive bisection net-constrained global placer (Alpert et al., 2001). The first detailed placer uses grid-based placement and transportation solving to assign instances to the grid. The second detailed placer uses simulated annealing to optimize placement for NLC. On benchmark circuits from MCNC and Intel Corporation, the grid and simulated annealing placers are able to achieve placements which exceed constraints by, on average only, 2.7% and 1.9%, respectively.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127502258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-22DOI: 10.1109/IWSOC.2003.1213063
J. Keilman, G. Jullien, K. Kaler
Future bio-analysis devices and systems will be heavily dependent on the micro-convergence of SoC platforms with the disparate technologies of MEMS and microfluidics. This paper describes a bio-analysis system that will be part of a future low-power bio-analysis platform being developed jointly in the ATIPS and Bioelectrics Laboratories at the University of Calgary. The analysis technique will exploit dielectrophoresis (DEP), an electrokinetic phenomenon that has demonstrated novel and noninvasive biological cell identification, interrogation and species separation capabilities. Various electrode configurations have been previously developed and implemented, each of which can manipulate cells in a specific manner, and test microstructures have been built by fabricating the electrodes using a standard CMOS process. In this paper we generalize this concept by providing a generic electrode structure, a "lexel" (electric field element) array, which, when integrated with a processor, is capable of generating an arbitrary electric field shape, thus facilitating a programmable sequence of different cell manipulations to be performed. This paper presents a proposal for the "lexel" array, a two dimensional array of discrete, independent electrodes, and discusses it's interfacing with appropriate controlling and sensing electronic components to provide flexible cell manipulation and subsequent analysis capability as part of a System-on-Chip bio-analysis platform.
{"title":"A SoC bio-analysis platform for real-time biological cell analysis-on-a-chip","authors":"J. Keilman, G. Jullien, K. Kaler","doi":"10.1109/IWSOC.2003.1213063","DOIUrl":"https://doi.org/10.1109/IWSOC.2003.1213063","url":null,"abstract":"Future bio-analysis devices and systems will be heavily dependent on the micro-convergence of SoC platforms with the disparate technologies of MEMS and microfluidics. This paper describes a bio-analysis system that will be part of a future low-power bio-analysis platform being developed jointly in the ATIPS and Bioelectrics Laboratories at the University of Calgary. The analysis technique will exploit dielectrophoresis (DEP), an electrokinetic phenomenon that has demonstrated novel and noninvasive biological cell identification, interrogation and species separation capabilities. Various electrode configurations have been previously developed and implemented, each of which can manipulate cells in a specific manner, and test microstructures have been built by fabricating the electrodes using a standard CMOS process. In this paper we generalize this concept by providing a generic electrode structure, a \"lexel\" (electric field element) array, which, when integrated with a processor, is capable of generating an arbitrary electric field shape, thus facilitating a programmable sequence of different cell manipulations to be performed. This paper presents a proposal for the \"lexel\" array, a two dimensional array of discrete, independent electrodes, and discusses it's interfacing with appropriate controlling and sensing electronic components to provide flexible cell manipulation and subsequent analysis capability as part of a System-on-Chip bio-analysis platform.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120848000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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