Pub Date : 2017-11-01DOI: 10.1109/ROPEC.2017.8261577
A. Valderrábano‐González, J. Rosas-Caro, F. Beltrán-Carbajal, R. Tapia-Olvera, H. Gabbar, A. Sharaf
This paper presents a step by step method for designing a residential PV inverter based on a six IGBT module. The use of an LC filter in the output, designed considering phasor relationships, brings the ability of having a very low THD without phase shifting or reduction in the voltage amplitude. An extra switch in the input conveys the advantage of managing buck and boost capabilities depending on the duty cycle. Simulations illustrate the viability of the results, and tables are provided for verification.
{"title":"An easy guide for inverter design for residential smart building applications","authors":"A. Valderrábano‐González, J. Rosas-Caro, F. Beltrán-Carbajal, R. Tapia-Olvera, H. Gabbar, A. Sharaf","doi":"10.1109/ROPEC.2017.8261577","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261577","url":null,"abstract":"This paper presents a step by step method for designing a residential PV inverter based on a six IGBT module. The use of an LC filter in the output, designed considering phasor relationships, brings the ability of having a very low THD without phase shifting or reduction in the voltage amplitude. An extra switch in the input conveys the advantage of managing buck and boost capabilities depending on the duty cycle. Simulations illustrate the viability of the results, and tables are provided for verification.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117233143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ROPEC.2017.8261610
M. del Rosario Rivera-Espinosa, Alfredo Y. Alejandre-López, Jesus E. Pedraza-Barrón, P. García-Vite, Héctor R. Robles-Campos
This paper exhibits the performance of a high step-up converter employed for maximum power extraction in a photovoltaic system. The proposed converter is conformed by a conventional boost followed by a diode-capacitor-based multiplier for increasing the nominal voltage gain of the boost converter, resulting in a lower duty cycle at the maximum power point. The main characteristics of the converters are analyzed in order to determine an optimal equivalent input impedance. Evaluation of the proposed converter using standard Perturb and Observe algorithm is carried out. Switching simulations evidence the good performance of the whole system under irradiance disturbances.
{"title":"A high step-up DC-DC converter with MPPT for PV application","authors":"M. del Rosario Rivera-Espinosa, Alfredo Y. Alejandre-López, Jesus E. Pedraza-Barrón, P. García-Vite, Héctor R. Robles-Campos","doi":"10.1109/ROPEC.2017.8261610","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261610","url":null,"abstract":"This paper exhibits the performance of a high step-up converter employed for maximum power extraction in a photovoltaic system. The proposed converter is conformed by a conventional boost followed by a diode-capacitor-based multiplier for increasing the nominal voltage gain of the boost converter, resulting in a lower duty cycle at the maximum power point. The main characteristics of the converters are analyzed in order to determine an optimal equivalent input impedance. Evaluation of the proposed converter using standard Perturb and Observe algorithm is carried out. Switching simulations evidence the good performance of the whole system under irradiance disturbances.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129221713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ROPEC.2017.8261653
M. Quizhpi-Cuesta, F. Gómez-Juca, W. Orozco-Tupacyupanqui, F. Quizhpi-Palomeque
The classification of partial discharge (PD) or partial breakdown (PB) is an important issue that helps to identify the cause of this electrical phenomenon in pin type insulators. In this work, a PD classification method based on neural networks (NN) is proposed. This sorting technique consists of three parts. First, the detection and measurement of partial discharge are achieved by using a digital finite impulse response (FIR) filter, whose main objective is to obtain electrical charges with significant characteristics of the PB. The second part of the process deals with the classification of partial discharge. A statistical analysis is implemented to obtain PD patterns or fingerprints which are classified by a neural network. Finally, the third part of the proposed method focuses on interpreting the information obtained from the NN and determining the PD current in the pin isolator. The results show that this proposed technique of analysis and detection of partial discharge in pin type isolators is successful in optimizing the time of analysis and classification of PB.
{"title":"Classification of partial discharge in pin type insulators using fingerprints and neural networks","authors":"M. Quizhpi-Cuesta, F. Gómez-Juca, W. Orozco-Tupacyupanqui, F. Quizhpi-Palomeque","doi":"10.1109/ROPEC.2017.8261653","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261653","url":null,"abstract":"The classification of partial discharge (PD) or partial breakdown (PB) is an important issue that helps to identify the cause of this electrical phenomenon in pin type insulators. In this work, a PD classification method based on neural networks (NN) is proposed. This sorting technique consists of three parts. First, the detection and measurement of partial discharge are achieved by using a digital finite impulse response (FIR) filter, whose main objective is to obtain electrical charges with significant characteristics of the PB. The second part of the process deals with the classification of partial discharge. A statistical analysis is implemented to obtain PD patterns or fingerprints which are classified by a neural network. Finally, the third part of the proposed method focuses on interpreting the information obtained from the NN and determining the PD current in the pin isolator. The results show that this proposed technique of analysis and detection of partial discharge in pin type isolators is successful in optimizing the time of analysis and classification of PB.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127913709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ROPEC.2017.8261662
Francisco Ramón Urquijo Ramos, J. Ramírez, J. Jiménez, L. Hernández
This paper presents a multi-level single-phase converter as an option to inject photovoltaic power into the grid and it is shown how at the same time it can be used to compensate power factor. The converter consists of three cell connected in cascade, each cell is an H-bridge inverter. A relatively low switching frequency and low size coupling inductance are used in order to achieve the power injection. In order to maintain regulated dc links a control strategy is carried out. Also, how this control strategy is capable to improve power quality, through to compensate reactive power and harmonic distortion, is shown in detail. The performance of the converter and its control is validated through simulation results on PSIM simulator.
{"title":"Multi-level inverter connected to the grid with harmonic mitigation for photovoltaic power injection","authors":"Francisco Ramón Urquijo Ramos, J. Ramírez, J. Jiménez, L. Hernández","doi":"10.1109/ROPEC.2017.8261662","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261662","url":null,"abstract":"This paper presents a multi-level single-phase converter as an option to inject photovoltaic power into the grid and it is shown how at the same time it can be used to compensate power factor. The converter consists of three cell connected in cascade, each cell is an H-bridge inverter. A relatively low switching frequency and low size coupling inductance are used in order to achieve the power injection. In order to maintain regulated dc links a control strategy is carried out. Also, how this control strategy is capable to improve power quality, through to compensate reactive power and harmonic distortion, is shown in detail. The performance of the converter and its control is validated through simulation results on PSIM simulator.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127937701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ROPEC.2017.8261618
Luis Caiza, Albert Rosich-Oliva, C. Ocampo‐Martinez, D. Benítez
In this paper, we propose to use Model Predictive Control techniques to reduce the energy consumption in an industrial process by incorporating energy consumption restrictions in the problem formulation. We propose to use a Model Predictive Control supervisor to calculate the optimum references for simple control loops regulated by individual PID controllers. The results obtained are compared against those obtained when a traditional control strategy exclusively based on PID controllers was used. By using this supervisory control strategy a reduction on energy consumption of about 10% was achieved.
{"title":"Reducing energy consumption in an industrial process by using model predictive control","authors":"Luis Caiza, Albert Rosich-Oliva, C. Ocampo‐Martinez, D. Benítez","doi":"10.1109/ROPEC.2017.8261618","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261618","url":null,"abstract":"In this paper, we propose to use Model Predictive Control techniques to reduce the energy consumption in an industrial process by incorporating energy consumption restrictions in the problem formulation. We propose to use a Model Predictive Control supervisor to calculate the optimum references for simple control loops regulated by individual PID controllers. The results obtained are compared against those obtained when a traditional control strategy exclusively based on PID controllers was used. By using this supervisory control strategy a reduction on energy consumption of about 10% was achieved.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130899272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ROPEC.2017.8261692
Reagan Mbitiru, T. Ustun
Developed initially for pre-paid electricity meters in South Africa, the IEC 662055-41 standard is now the world's most ubiquitous open pre-paid metering standard. The standard is used in 35 million meters operated in 400 utilities in 30 countries. It now serves more users in Asia than in Africa. The standard uses 16 cycles of a block-cipher-like substitution and permutation process to both generate 20 digit tokens (through an encryption process) and to decode 20 digit tokens and determine the number of kWhs procured (through a decryption process), in conjunction with a 64 bit decoder key generated using the Data Encryption standard (DES). Despite its popularity, there is little work on the cryptology aspects of this standard. This paper discusses two types of cryptanalysis techniques used to attack this pre-paid metering standard. The first is a statistical analysis of the encrypted and decrypted inputs and outputs to determine if any correlation between them exists. The second is the use of slide attacks, a technique traditionally used for attacking block ciphers that use the same or ‘weak’ round keys for each encryption/decryption cycle. Using this second cryptanalysis attack, it is shown that 16 of the 64 bits of the decoder key can be exposed, an aspect not intended by its designers. Further combination with other techniques may be used to compromise the entire key.
{"title":"Using input-output correlations and a modified slide attack to compromise IEC 62055-41","authors":"Reagan Mbitiru, T. Ustun","doi":"10.1109/ROPEC.2017.8261692","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261692","url":null,"abstract":"Developed initially for pre-paid electricity meters in South Africa, the IEC 662055-41 standard is now the world's most ubiquitous open pre-paid metering standard. The standard is used in 35 million meters operated in 400 utilities in 30 countries. It now serves more users in Asia than in Africa. The standard uses 16 cycles of a block-cipher-like substitution and permutation process to both generate 20 digit tokens (through an encryption process) and to decode 20 digit tokens and determine the number of kWhs procured (through a decryption process), in conjunction with a 64 bit decoder key generated using the Data Encryption standard (DES). Despite its popularity, there is little work on the cryptology aspects of this standard. This paper discusses two types of cryptanalysis techniques used to attack this pre-paid metering standard. The first is a statistical analysis of the encrypted and decrypted inputs and outputs to determine if any correlation between them exists. The second is the use of slide attacks, a technique traditionally used for attacking block ciphers that use the same or ‘weak’ round keys for each encryption/decryption cycle. Using this second cryptanalysis attack, it is shown that 16 of the 64 bits of the decoder key can be exposed, an aspect not intended by its designers. Further combination with other techniques may be used to compromise the entire key.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132880972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ROPEC.2017.8261602
Jose F. Tenesaca, Marco Carpio, R. Saltarén, G. Portilla
This article presents the nonlinear mathematical modeling of a proportional valve. In order to be able to determine the external and internal technical characteristics of the valve through experimental measurements of its parameters, it is possible to model and determine the parameters; however, it varies due to its aging effects and causes the system to respond incorrectly. Once the measurements were made it was possible to know that the model obtained experimentally approximates with the technical data of the manufacturer.
{"title":"Experimental determination of the nonlinear model for a proportional hydraulic valve","authors":"Jose F. Tenesaca, Marco Carpio, R. Saltarén, G. Portilla","doi":"10.1109/ROPEC.2017.8261602","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261602","url":null,"abstract":"This article presents the nonlinear mathematical modeling of a proportional valve. In order to be able to determine the external and internal technical characteristics of the valve through experimental measurements of its parameters, it is possible to model and determine the parameters; however, it varies due to its aging effects and causes the system to respond incorrectly. Once the measurements were made it was possible to know that the model obtained experimentally approximates with the technical data of the manufacturer.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133871422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ROPEC.2017.8261606
Candy Obdulia Sosa-Jimenez, H. Rios-Figueroa, E. Rechy-Ramirez, A. Marín-Hernández, Ana Luisa Solís González-Cosío
The Mexican Sign Language (MSL) has its own structure and grammar different from the Spanish spoken in Mexico. The MSL is composed of more than 1000 signs used by the deaf community of this country. Few hearing people know and use MSL, therefore there is a communication barrier between hearing and deaf people. In order to overcome this issue, we propose a non-invasive sign detection application, so that the interlocutor interacts with the system in a natural way interpreting a set of signs of the MSL using a bimodal cognitive vision system. Our application uses a Kinect sensor to obtain the gestures, geometric moments and Hidden Markov models to process it. From experiments performed with 10 people, it was concluded that our application achieved an average sensitivity of 86% and an average specificity of 80%.
{"title":"Real-time Mexican Sign Language recognition","authors":"Candy Obdulia Sosa-Jimenez, H. Rios-Figueroa, E. Rechy-Ramirez, A. Marín-Hernández, Ana Luisa Solís González-Cosío","doi":"10.1109/ROPEC.2017.8261606","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261606","url":null,"abstract":"The Mexican Sign Language (MSL) has its own structure and grammar different from the Spanish spoken in Mexico. The MSL is composed of more than 1000 signs used by the deaf community of this country. Few hearing people know and use MSL, therefore there is a communication barrier between hearing and deaf people. In order to overcome this issue, we propose a non-invasive sign detection application, so that the interlocutor interacts with the system in a natural way interpreting a set of signs of the MSL using a bimodal cognitive vision system. Our application uses a Kinect sensor to obtain the gestures, geometric moments and Hidden Markov models to process it. From experiments performed with 10 people, it was concluded that our application achieved an average sensitivity of 86% and an average specificity of 80%.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121382136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ROPEC.2017.8261575
Ali Far
An input-output rail-to-rail buffer amplifier is presented that is low noise, fast, and operates at ultra low currents. The amplifier targets energy harvesting applications that require low cost, high volume, and rugged manufacturing by avoiding use of non-standard device configurations or special processes. The main contributions of this work are: (1) The method of lowering voltage output noise by narrow-banding an amplifier, while introducing a time dependent bias current boost that is triggered by large differential input signals. Narrowbanding an amplifier to reduce its output noise, slows its dynamic response, and this method aims to restore and boost both the amplifier's slew rate and settling time. (2) Amplifier can operate at low VDD of about VGS+2VDS, while running in subthreshold, based in standard 0.18u digital CMOS. (3) PMOSFETs are utilized as inputs, compensation capacitors, and bias resistors in both the amplifier and the boost stages, which helps optimize for yield and lower noise. More importantly, the dynamic response of both the main amplifier and the boost stage being substantially dependent on PMOSFET device parameters, facilitates a smoother dynamic response in and out of boost, over process and operating variations. Based on montecarlo (MC) and worst case (WC) simulations, the following specifications are achievable: voltage output noise (VOnOiSe) of 10 uv/Hz⁁1/2 at 1KHz, supply current (Idd) ∼ 500 nA; Vdd minimum ∼0.6V; rail-to-rail voltage input (VIN) range and output voltage (VOUT) range of ∼ +/− 25mv from the rails; output resistor load (Rl) ∼2k Ohms; output capacitor load (Cl) ∼1nF; slew-rate (SR) −/+ ∼ 4/2.5 v/us; settling time (tS) ∼ 5us to 1%; power supply rejection ratio (PSRR) −/+ ∼ 80dB/85dB, common mode rejection ration (CMRR) ∼ 125dB, unity gain bandwidth (fr) ∼ 20KHz with phase margin (PM) ∼ 75 degrees; open loop gain (G) ∼ 85dB; preliminary area estimate of ∼ 180 um per side.
{"title":"Low noise rail-to-rail amplifier runs fast at ultra low currents and targets energy harvesting","authors":"Ali Far","doi":"10.1109/ROPEC.2017.8261575","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261575","url":null,"abstract":"An input-output rail-to-rail buffer amplifier is presented that is low noise, fast, and operates at ultra low currents. The amplifier targets energy harvesting applications that require low cost, high volume, and rugged manufacturing by avoiding use of non-standard device configurations or special processes. The main contributions of this work are: (1) The method of lowering voltage output noise by narrow-banding an amplifier, while introducing a time dependent bias current boost that is triggered by large differential input signals. Narrowbanding an amplifier to reduce its output noise, slows its dynamic response, and this method aims to restore and boost both the amplifier's slew rate and settling time. (2) Amplifier can operate at low VDD of about VGS+2VDS, while running in subthreshold, based in standard 0.18u digital CMOS. (3) PMOSFETs are utilized as inputs, compensation capacitors, and bias resistors in both the amplifier and the boost stages, which helps optimize for yield and lower noise. More importantly, the dynamic response of both the main amplifier and the boost stage being substantially dependent on PMOSFET device parameters, facilitates a smoother dynamic response in and out of boost, over process and operating variations. Based on montecarlo (MC) and worst case (WC) simulations, the following specifications are achievable: voltage output noise (VO<inf>nOiSe</inf>) of 10 uv/Hz⁁1/2 at 1KHz, supply current (Idd) ∼ 500 nA; V<inf>dd</inf> minimum ∼0.6V; rail-to-rail voltage input (V<inf>IN</inf>) range and output voltage (V<inf>OUT</inf>) range of ∼ +/− 25mv from the rails; output resistor load (R<inf>l</inf>) ∼2k Ohms; output capacitor load (C<inf>l</inf>) ∼1nF; slew-rate (SR) −/+ ∼ 4/2.5 v/us; settling time (t<inf>S</inf>) ∼ 5us to 1%; power supply rejection ratio (PSRR) −/+ ∼ 80dB/85dB, common mode rejection ration (CMRR) ∼ 125dB, unity gain bandwidth (f<inf>r</inf>) ∼ 20KHz with phase margin (PM) ∼ 75 degrees; open loop gain (G) ∼ 85dB; preliminary area estimate of ∼ 180 um per side.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126799745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/ROPEC.2017.8261677
L. Trojman, Diego R. Benalcázar, L. Prócel, Guillaume Jobard
In this article, we study the mobility for short devices (down to 24-nm-channel length) using the RFCV technique. We also evaluate how this technique is reliable for such small devices and discuss the consequences of extrinsic process effects like the HALO on the mobility degradation. Using the additional mobility, we deduce that this degradation occurs due to an increase in the doping concentration caused by the HALO technique, which also affects the screening effect at low effective field.
{"title":"Mobility extraction for 24-nm-channel length n-MOS using the RFCV technique: Effect of the fabrication process","authors":"L. Trojman, Diego R. Benalcázar, L. Prócel, Guillaume Jobard","doi":"10.1109/ROPEC.2017.8261677","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261677","url":null,"abstract":"In this article, we study the mobility for short devices (down to 24-nm-channel length) using the RFCV technique. We also evaluate how this technique is reliable for such small devices and discuss the consequences of extrinsic process effects like the HALO on the mobility degradation. Using the additional mobility, we deduce that this degradation occurs due to an increase in the doping concentration caused by the HALO technique, which also affects the screening effect at low effective field.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115432406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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