Pub Date : 2006-11-01DOI: 10.1109/NVMT.2006.378879
Bin Li, A. Bumgarner, D. Pirkl, J. Stobie, W. Neiderer, M. Graziano, L. Burcin, T. Storey, B. Orlowsky, K. Hunt, J. Rodgers, J. Maimon
A 4 Mbit non-volatile chalcogenide-random access memory (C-RAMTM) has been designed and fabricated in RH 25, a radiation hardened CMOS technology. The top-down design focused on accommodating chalcogenide process variations and satisfying space system specifications. The optimized band-gap circuit supplies reference current and voltage that meet temperature and voltage requirements. The innovative write circuitry supplies appropriate currents (amplitude and shape) to the chalcogenide memory cells to allow them to be programmed either in amorphous state (write "0") or crystalline state (write "1"). The on-chip pulse generator circuit can provide multiple pulse widths for write "0" and write "1". The write circuits have a dedicated power supply, which can be removed to place the part in a read only mode. The read circuitry includes a voltage limiting circuit, an adjustable current reference, an adjustable pre-charge circuit, and a sense amplifier to accurately sense the current difference between cells programmed as "0" or "1". A localized, redundant cell architecture is implemented with shared read/write circuits to improve yield without impacting access times. The redundant cells can be tested prior to laser fusing or used to monitor endurance. Considerations for testability such as direct chalcogenide cell access, margin testing, analog monitors, and endurance acceleration have been implemented. Noise and power reduction techniques have also been used globally.
{"title":"A 4-Mbit Non-Volatile Chalcogenide-Random Access Memory Designed for Space Applications","authors":"Bin Li, A. Bumgarner, D. Pirkl, J. Stobie, W. Neiderer, M. Graziano, L. Burcin, T. Storey, B. Orlowsky, K. Hunt, J. Rodgers, J. Maimon","doi":"10.1109/NVMT.2006.378879","DOIUrl":"https://doi.org/10.1109/NVMT.2006.378879","url":null,"abstract":"A 4 Mbit non-volatile chalcogenide-random access memory (C-RAMTM) has been designed and fabricated in RH 25, a radiation hardened CMOS technology. The top-down design focused on accommodating chalcogenide process variations and satisfying space system specifications. The optimized band-gap circuit supplies reference current and voltage that meet temperature and voltage requirements. The innovative write circuitry supplies appropriate currents (amplitude and shape) to the chalcogenide memory cells to allow them to be programmed either in amorphous state (write \"0\") or crystalline state (write \"1\"). The on-chip pulse generator circuit can provide multiple pulse widths for write \"0\" and write \"1\". The write circuits have a dedicated power supply, which can be removed to place the part in a read only mode. The read circuitry includes a voltage limiting circuit, an adjustable current reference, an adjustable pre-charge circuit, and a sense amplifier to accurately sense the current difference between cells programmed as \"0\" or \"1\". A localized, redundant cell architecture is implemented with shared read/write circuits to improve yield without impacting access times. The redundant cells can be tested prior to laser fusing or used to monitor endurance. Considerations for testability such as direct chalcogenide cell access, margin testing, analog monitors, and endurance acceleration have been implemented. Noise and power reduction techniques have also been used globally.","PeriodicalId":263387,"journal":{"name":"2006 7th Annual Non-Volatile Memory Technology Symposium","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121213515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/NVMT.2006.378872
Yasuo Cho, S. Hashimoto, N. Odagawa, K. Tanaka, Y. Hiranaga
Nano-sized inverted domain dots in ferroelectric materials have potential application in ultrahigh-density rewritable data storage systems. Herein, a data storage system is presented based on scanning non-linear dielectric microscopy and a thin film of ferroelectric single-crystal lithium tantalite. Through domain engineering, we succeeded to form an smallest artificial nano-domain single dot of 5.1 nm in diameter and artificial nano-domain dot-array with a memory density of 10.1 Tbit/inch2 and a bit spacing of 8.0 nm, representing the highest memory density for rewritable data storage reported to date. Sub-nanosecond (500 psec) domain switching speed also has been achieved. Next, long term retention characteristic of data with inverted domain dots is investigated by conducting heat treatment test. Obtained life time of inverted dot with the radius of 50 nm was 16.9 years at 80degC. Finally, actual information storage with low bit error and high memory density was performed. A bit error ratio of less than 1times 10-4 was achieved at an areal density of 258 Gbit/inch2. Moreover, actual information storage is demonstrated at a density of 1 Tbit/inch2.
{"title":"Ferroelectric Ultra High-Density Data Storage Based on Scanning Nonlinear Dielectric Microscopy","authors":"Yasuo Cho, S. Hashimoto, N. Odagawa, K. Tanaka, Y. Hiranaga","doi":"10.1109/NVMT.2006.378872","DOIUrl":"https://doi.org/10.1109/NVMT.2006.378872","url":null,"abstract":"Nano-sized inverted domain dots in ferroelectric materials have potential application in ultrahigh-density rewritable data storage systems. Herein, a data storage system is presented based on scanning non-linear dielectric microscopy and a thin film of ferroelectric single-crystal lithium tantalite. Through domain engineering, we succeeded to form an smallest artificial nano-domain single dot of 5.1 nm in diameter and artificial nano-domain dot-array with a memory density of 10.1 Tbit/inch2 and a bit spacing of 8.0 nm, representing the highest memory density for rewritable data storage reported to date. Sub-nanosecond (500 psec) domain switching speed also has been achieved. Next, long term retention characteristic of data with inverted domain dots is investigated by conducting heat treatment test. Obtained life time of inverted dot with the radius of 50 nm was 16.9 years at 80degC. Finally, actual information storage with low bit error and high memory density was performed. A bit error ratio of less than 1times 10-4 was achieved at an areal density of 258 Gbit/inch2. Moreover, actual information storage is demonstrated at a density of 1 Tbit/inch2.","PeriodicalId":263387,"journal":{"name":"2006 7th Annual Non-Volatile Memory Technology Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126915251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/NVMT.2006.378883
J. Yeh, F. Chen, D. Chao, Wen-Han Wang, Yi-Chan Chen, Chain-Ming Lee, M. Tsai, M. Kao
A simulation procedure using the conventional thermal-electric finite element method for the phase change memory has been developed. By introducing a defect on the amorphous chalcogenide of a reset phase change memory, the snapback by hot filament due to thermal runaway has been investigated by the numerical simulations with three-dimensional model.
{"title":"Snapback by Hot Filament","authors":"J. Yeh, F. Chen, D. Chao, Wen-Han Wang, Yi-Chan Chen, Chain-Ming Lee, M. Tsai, M. Kao","doi":"10.1109/NVMT.2006.378883","DOIUrl":"https://doi.org/10.1109/NVMT.2006.378883","url":null,"abstract":"A simulation procedure using the conventional thermal-electric finite element method for the phase change memory has been developed. By introducing a defect on the amorphous chalcogenide of a reset phase change memory, the snapback by hot filament due to thermal runaway has been investigated by the numerical simulations with three-dimensional model.","PeriodicalId":263387,"journal":{"name":"2006 7th Annual Non-Volatile Memory Technology Symposium","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121294998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/NVMT.2006.378878
D. Strukov, K. Likharev
We have calculated the useful density that may be achieved by the synergy of bad bit exclusion and advanced (BCH) error correcting codes in prospective hybrid (CMOS/nanodevice) resistive memories, as a function of the defective memory cell fraction. The results indicate that the memories with a CMOS/nano pitch ratio close to 3 (which is typical for the current, initial stage of hybrid circuit development), may overcome the usual resistive and flash memories with the same CMOS design rules in useful bit density if the fraction of bad nanodevices is below ~ 15%, even under rather tough (30 ns) restrictions on the total access time. Moreover, as the technology matures, and the pitch ratio approaches an order of magnitude, the hybrid resistive memories may be far superior to the densest semiconductor memories by providing, e. g., a 1 Tbit/cm2 density even for a very conservative defect fraction of ~ 2%.
{"title":"A Defect-Tolerant Architecture for Nanoelectronic Resistive Memories","authors":"D. Strukov, K. Likharev","doi":"10.1109/NVMT.2006.378878","DOIUrl":"https://doi.org/10.1109/NVMT.2006.378878","url":null,"abstract":"We have calculated the useful density that may be achieved by the synergy of bad bit exclusion and advanced (BCH) error correcting codes in prospective hybrid (CMOS/nanodevice) resistive memories, as a function of the defective memory cell fraction. The results indicate that the memories with a CMOS/nano pitch ratio close to 3 (which is typical for the current, initial stage of hybrid circuit development), may overcome the usual resistive and flash memories with the same CMOS design rules in useful bit density if the fraction of bad nanodevices is below ~ 15%, even under rather tough (30 ns) restrictions on the total access time. Moreover, as the technology matures, and the pitch ratio approaches an order of magnitude, the hybrid resistive memories may be far superior to the densest semiconductor memories by providing, e. g., a 1 Tbit/cm2 density even for a very conservative defect fraction of ~ 2%.","PeriodicalId":263387,"journal":{"name":"2006 7th Annual Non-Volatile Memory Technology Symposium","volume":"692 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121990349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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