Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131575
J. Tyszer, P. Maxwell
{"title":"ETS 2019 Best Paper","authors":"J. Tyszer, P. Maxwell","doi":"10.1109/ets48528.2020.9131575","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131575","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126926056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131584
{"title":"ETS 2020 Sponsors","authors":"","doi":"10.1109/ets48528.2020.9131584","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131584","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122318289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131570
{"title":"Title Page","authors":"","doi":"10.1109/ets48528.2020.9131570","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131570","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122197561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131588
R. Feitoza, M. Barragán, A. Ginés, S. Mir
This paper describes a BIST technique for the static linearity test of $V_{cm}$ -based successive-approximation analog-to-digital converters (SAR ADCs). We discuss the application of reduced-code techniques for the $V_{cm}$ -based SAR ADC topology and present a practical on-chip implementation based on an embedded incremental ADC. Simulation results are provided for validating the feasibility and performance of the proposed on-chip reduced-code static linearity test.
{"title":"On-chip reduced-code static linearity test of $V_{cm}$ -based switching SAR ADCs using an incremental analog-to-digital converter","authors":"R. Feitoza, M. Barragán, A. Ginés, S. Mir","doi":"10.1109/ETS48528.2020.9131588","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131588","url":null,"abstract":"This paper describes a BIST technique for the static linearity test of $V_{cm}$ -based successive-approximation analog-to-digital converters (SAR ADCs). We discuss the application of reduced-code techniques for the $V_{cm}$ -based SAR ADC topology and present a practical on-chip implementation based on an embedded incremental ADC. Simulation results are provided for validating the feasibility and performance of the proposed on-chip reduced-code static linearity test.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122073464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131603
C. Reinbrecht, S. Hamdioui, M. Taouil, Behrad Niazmand, Tara Ghasempouri, J. Raik, Martha Johanna Sepúlveda
Cache attacks are one of the most wide-spread and dangerous threats to embedded computing systems' security. A promising approach to detect such attacks at runtime is to monitor the System-on-Chip (SoC) behavior. However, designing a secure SoC capable of detecting such attacks is very challenging: the monitors should be lightweight in order to avoid excessive power/energy and area costs and the attack behavior should be clearly known upfront. In this work, we present LiD-CAT, a lightweight and flexible hardware detector that is aware of leakage patterns that can be used by attackers to perform cache based attacks. LiD-CAT is a cache wrapper that implements a set of leakage properties derived from cache attacks and cache models using templates. These templates identify suspicious behavior that may lead to cache attacks. LiD-CAT is evaluated using two different cache architectures, one with a secure cache and one without. On each of them, SPEC2000 benchmarks are run together with malicious applications that execute cache attacks (i.e., Evict+Time, Prime+Probe, Flush+Reload and Flush+Flush). Results show that our lightweight detector successfully detects 99.99% of the attacks with less than 1% false-positives, has no timing penalties, and increases the area of a SoC with only 1.6%.
{"title":"LiD-CAT: A Lightweight Detector for Cache ATtacks","authors":"C. Reinbrecht, S. Hamdioui, M. Taouil, Behrad Niazmand, Tara Ghasempouri, J. Raik, Martha Johanna Sepúlveda","doi":"10.1109/ETS48528.2020.9131603","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131603","url":null,"abstract":"Cache attacks are one of the most wide-spread and dangerous threats to embedded computing systems' security. A promising approach to detect such attacks at runtime is to monitor the System-on-Chip (SoC) behavior. However, designing a secure SoC capable of detecting such attacks is very challenging: the monitors should be lightweight in order to avoid excessive power/energy and area costs and the attack behavior should be clearly known upfront. In this work, we present LiD-CAT, a lightweight and flexible hardware detector that is aware of leakage patterns that can be used by attackers to perform cache based attacks. LiD-CAT is a cache wrapper that implements a set of leakage properties derived from cache attacks and cache models using templates. These templates identify suspicious behavior that may lead to cache attacks. LiD-CAT is evaluated using two different cache architectures, one with a secure cache and one without. On each of them, SPEC2000 benchmarks are run together with malicious applications that execute cache attacks (i.e., Evict+Time, Prime+Probe, Flush+Reload and Flush+Flush). Results show that our lightweight detector successfully detects 99.99% of the attacks with less than 1% false-positives, has no timing penalties, and increases the area of a SoC with only 1.6%.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125618929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131565
Helen-Maria Dounavi, Y. Tsiatouhas
Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena degrade seriously the reliability of an SRAM. Such phenomena affect all SRAM blocks; among them the Address Decoders. Over-aged Decoders lead to potential read and/or write failures. It is imperative to develop design techniques that provide aging-tolerance in order to retain the SRAM reliable operation. An embedded circuit for the BTI and HCI aging monitoring in SRAM Decoders is presented along with an approach to react for memory repair after aging detection.
{"title":"Monitoring of BTI and HCI Aging in SRAM Decoders","authors":"Helen-Maria Dounavi, Y. Tsiatouhas","doi":"10.1109/ETS48528.2020.9131565","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131565","url":null,"abstract":"Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena degrade seriously the reliability of an SRAM. Such phenomena affect all SRAM blocks; among them the Address Decoders. Over-aged Decoders lead to potential read and/or write failures. It is imperative to develop design techniques that provide aging-tolerance in order to retain the SRAM reliable operation. An embedded circuit for the BTI and HCI aging monitoring in SRAM Decoders is presented along with an approach to react for memory repair after aging detection.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126318203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131556
{"title":"ETS 2020 Steering and Program Committees","authors":"","doi":"10.1109/ets48528.2020.9131556","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131556","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131444354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131587
Manhong Zhu, Jia Li, Weibing Wang, Dapeng Chen
Nowadays, MEMS testing has become a growing problem because it usually needs specific and sophisticated testing equipment and is very time-consuming. To solve this problem, this paper proposes a Built-In Self-Test (BIST) method for membrane MEMS piezoresistive sensor. With the proposed method, an on-chip electric signal can be used as the test stimuli, and process defects of piezoresistive sensor can be diagnosed by analyzing the output response of piezoresistive sensor on chip. The simulation shows that the proposed MEMS BIST scheme can effectively replace the physical testing stimuli with electric signal, thus reduce the dependence on external signal sources and the cost of manufacturing devices.
{"title":"A Built-In Self-Test Method For MEMS Piezoresistive Sensor","authors":"Manhong Zhu, Jia Li, Weibing Wang, Dapeng Chen","doi":"10.1109/ETS48528.2020.9131587","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131587","url":null,"abstract":"Nowadays, MEMS testing has become a growing problem because it usually needs specific and sophisticated testing equipment and is very time-consuming. To solve this problem, this paper proposes a Built-In Self-Test (BIST) method for membrane MEMS piezoresistive sensor. With the proposed method, an on-chip electric signal can be used as the test stimuli, and process defects of piezoresistive sensor can be diagnosed by analyzing the output response of piezoresistive sensor on chip. The simulation shows that the proposed MEMS BIST scheme can effectively replace the physical testing stimuli with electric signal, thus reduce the dependence on external signal sources and the cost of manufacturing devices.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"56 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123220024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131579
M. Stucchi, F. Fodor, E. Marinissen
Resistance measurements of vertical interconnect elements by cross-bridge Kelvin resistors can yield values far below the expected value, if that resistance is calculated with the simple formula based on resistivity, interconnect length, and cross-sectional area; for small resistors, the measured value can even become negative. Analysis of current and potential distributions inside the simulated structures helps both to understand the causes of these non-realistic resistance values and to improve the design of the CBKR structures for preventing underestimation of the vertical interconnect resistance.
{"title":"Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios","authors":"M. Stucchi, F. Fodor, E. Marinissen","doi":"10.1109/ETS48528.2020.9131579","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131579","url":null,"abstract":"Resistance measurements of vertical interconnect elements by cross-bridge Kelvin resistors can yield values far below the expected value, if that resistance is calculated with the simple formula based on resistivity, interconnect length, and cross-sectional area; for small resistors, the measured value can even become negative. Analysis of current and potential distributions inside the simulated structures helps both to understand the causes of these non-realistic resistance values and to improve the design of the CBKR structures for preventing underestimation of the vertical interconnect resistance.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114509503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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