Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131578
Amir Alipour, V. Beroulle, B. Cambou, J. Danger, G. D. Natale, D. Hély, S. Guilley, Naghmeh Karimi
Physically Unclonable Functions (PUFs) allow to extract unique fingerprints from silicon chips. The applications are numerous: chip identification, chip master key extraction, authentication protocol, unique seeding, etc. However, secure usage of PUF requires some precautions. This paper reviews industrial concerns associated with PUF operation, including those occurring before and after market. Namely, starting from PUF “secure” specifications, aligned with state-of-the-art standards, we explore innovative techniques to handle enrollment and subsequent PUF queries, in nominal as well as in adversarial environment.
{"title":"PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community","authors":"Amir Alipour, V. Beroulle, B. Cambou, J. Danger, G. D. Natale, D. Hély, S. Guilley, Naghmeh Karimi","doi":"10.1109/ETS48528.2020.9131578","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131578","url":null,"abstract":"Physically Unclonable Functions (PUFs) allow to extract unique fingerprints from silicon chips. The applications are numerous: chip identification, chip master key extraction, authentication protocol, unique seeding, etc. However, secure usage of PUF requires some precautions. This paper reviews industrial concerns associated with PUF operation, including those occurring before and after market. Namely, starting from PUF “secure” specifications, aligned with state-of-the-art standards, we explore innovative techniques to handle enrollment and subsequent PUF queries, in nominal as well as in adversarial environment.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130174933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131579
M. Stucchi, F. Fodor, E. Marinissen
Resistance measurements of vertical interconnect elements by cross-bridge Kelvin resistors can yield values far below the expected value, if that resistance is calculated with the simple formula based on resistivity, interconnect length, and cross-sectional area; for small resistors, the measured value can even become negative. Analysis of current and potential distributions inside the simulated structures helps both to understand the causes of these non-realistic resistance values and to improve the design of the CBKR structures for preventing underestimation of the vertical interconnect resistance.
{"title":"Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios","authors":"M. Stucchi, F. Fodor, E. Marinissen","doi":"10.1109/ETS48528.2020.9131579","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131579","url":null,"abstract":"Resistance measurements of vertical interconnect elements by cross-bridge Kelvin resistors can yield values far below the expected value, if that resistance is calculated with the simple formula based on resistivity, interconnect length, and cross-sectional area; for small resistors, the measured value can even become negative. Analysis of current and potential distributions inside the simulated structures helps both to understand the causes of these non-realistic resistance values and to improve the design of the CBKR structures for preventing underestimation of the vertical interconnect resistance.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114509503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131585
Bartosz Kaczmarek, Grzegorz Mrugalski, N. Mukherjee, J. Rajski, Lukasz Rybak, J. Tyszer
As the use of electronic components grows rapidly in the automotive industry, the number of complex safety-critical devices used in advanced driver assistance systems or autonomous cars is rising with high-end models containing more than 200 embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that address challenges posed by high quality and long-term reliability requirements mandated, for example, by the ISO 26262 standard. The paper presents test pattern generation schemes for a scan-based logic BIST optimizing test coverage and test time during in-system test applications for automotive ICs. As a part of overall safety, they help in ensuring reliable operations of vehicle's electronics throughout their lifecycles. The proposed schemes can be deployed in different modes of in-system testing, including key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes.
{"title":"Test Sequence-Optimized BIST for Automotive Applications","authors":"Bartosz Kaczmarek, Grzegorz Mrugalski, N. Mukherjee, J. Rajski, Lukasz Rybak, J. Tyszer","doi":"10.1109/ETS48528.2020.9131585","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131585","url":null,"abstract":"As the use of electronic components grows rapidly in the automotive industry, the number of complex safety-critical devices used in advanced driver assistance systems or autonomous cars is rising with high-end models containing more than 200 embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that address challenges posed by high quality and long-term reliability requirements mandated, for example, by the ISO 26262 standard. The paper presents test pattern generation schemes for a scan-based logic BIST optimizing test coverage and test time during in-system test applications for automotive ICs. As a part of overall safety, they help in ensuring reliable operations of vehicle's electronics throughout their lifecycles. The proposed schemes can be deployed in different modes of in-system testing, including key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134403138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131592
G. D. Natale, O. Keren
A hardware-based control flow monitoring technique enables to detect both errors in the control flow and the instruction stream being executed on a processor. However, as was shown in recent papers, these techniques fail to detect malicious carefully-tuned manipulation of the instruction stream in a basic block. This paper presents a non-linear encoder and checker that can cope with this weakness.
{"title":"Nonlinear Codes for Control Flow Checking","authors":"G. D. Natale, O. Keren","doi":"10.1109/ETS48528.2020.9131592","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131592","url":null,"abstract":"A hardware-based control flow monitoring technique enables to detect both errors in the control flow and the instruction stream being executed on a processor. However, as was shown in recent papers, these techniques fail to detect malicious carefully-tuned manipulation of the instruction stream in a basic block. This paper presents a non-linear encoder and checker that can cope with this weakness.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131265175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131572
{"title":"Copyright","authors":"","doi":"10.1109/ets48528.2020.9131572","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131572","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116882603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131569
{"title":"ETS 2020 Foreword","authors":"","doi":"10.1109/ets48528.2020.9131569","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131569","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"508 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123199258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131577
Mehmet Ince, S. Ozev
With the increasing complexity of electronic components in critical applications, pressure on single components to have zero defects is also increasing. Thus there is a need to explore built-in self-test and other non-traditional test techniques for mixed-signal circuits, such as data converters, phase locked loops and power converters. In this paper, we present an extremely low cost, digital built-in self-test methodology for Low Dropout Regulators (LDO), specifically used for defect detection. The technique relies on perturbing the LDO loop at the reference voltage input via pseudo random binary sequence which has white noise characteristics and cross correlating the output of LDO with input excitation using only digital circuits, thus inducing low power and area overhead. The built-in self-test technique together with an LDO is designed using 65nm TMSC technology. Transistor level structural fault simulations display that all inserted faults can be detected even if they do not change the DC level of the LDO output.
{"title":"Digital Defect Based Built-in Self-Test for Low Dropout Voltage Regulators","authors":"Mehmet Ince, S. Ozev","doi":"10.1109/ETS48528.2020.9131577","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131577","url":null,"abstract":"With the increasing complexity of electronic components in critical applications, pressure on single components to have zero defects is also increasing. Thus there is a need to explore built-in self-test and other non-traditional test techniques for mixed-signal circuits, such as data converters, phase locked loops and power converters. In this paper, we present an extremely low cost, digital built-in self-test methodology for Low Dropout Regulators (LDO), specifically used for defect detection. The technique relies on perturbing the LDO loop at the reference voltage input via pseudo random binary sequence which has white noise characteristics and cross correlating the output of LDO with input excitation using only digital circuits, thus inducing low power and area overhead. The built-in self-test technique together with an LDO is designed using 65nm TMSC technology. Transistor level structural fault simulations display that all inserted faults can be detected even if they do not change the DC level of the LDO output.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130230611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131557
A. Bosio, S. Carlo, P. Girard, Ernesto Sánchez, A. Savino, L. Sekanina, Marcello Traiola, Z. Vašíček, A. Virazel
Today, the concept of approximation in computing is becoming more and more a “hot topic” to investigate how computing systems can be more energy efficient, faster, and less complex. Intuitively, instead of performing exact computations and, consequently, requiring a high amount of resources, Approximate Computing aims at selectively relaxing the specifications, trading accuracy off for efficiency. While Approximate Computing gives several promises when looking at systems' performance, energy efficiency and complexity, it poses significant challenges regarding the design, the verification, the test and the in-field reliability of Approximate Computing systems. This tutorial paper covers these aspects leveraging the experience of the authors in the field to present state-of-the-art solutions to apply during the different development phases of an Approximate Computing system.
{"title":"Design, Verification, Test and In-Field Implications of Approximate Computing Systems","authors":"A. Bosio, S. Carlo, P. Girard, Ernesto Sánchez, A. Savino, L. Sekanina, Marcello Traiola, Z. Vašíček, A. Virazel","doi":"10.1109/ETS48528.2020.9131557","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131557","url":null,"abstract":"Today, the concept of approximation in computing is becoming more and more a “hot topic” to investigate how computing systems can be more energy efficient, faster, and less complex. Intuitively, instead of performing exact computations and, consequently, requiring a high amount of resources, Approximate Computing aims at selectively relaxing the specifications, trading accuracy off for efficiency. While Approximate Computing gives several promises when looking at systems' performance, energy efficiency and complexity, it poses significant challenges regarding the design, the verification, the test and the in-field reliability of Approximate Computing systems. This tutorial paper covers these aspects leveraging the experience of the authors in the field to present state-of-the-art solutions to apply during the different development phases of an Approximate Computing system.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125317659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131598
Katherine Shu-Min Li, Peter Yi-Yu Liao, Leon Chou, Ken Chau-Cheung Cheng, Andrew Yi-Ann Huang, Sying-Jyan Wang, G. Han
Wafermap defect pattern detection and diagnosis provide useful clue to yield learning. However, most wafermaps have no special spatial patterns and are full of noises, which make pattern recognition difficult. Specially, recognizing scratch and line types of defect patterns is a challenging problem for process and test engineers and it takes a lot of manpower to identify such patterns, as potential defective dies may exist on the scratch contour and become discontinuity points. However, such potential defective dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the obscure defective dies in potential scratch patterns and mark them as faulty. As a result, the quality and reliability of products can be significantly improved and cost of final test can be reduced. In this paper, we propose a systematic methodology to search for potential scratch/line defect types in wafers. A five-phase method is developed to enhance wafermaps such that automatic defect pattern recognition can be carried with high accuracy. Experimental results show the proposed method can achieve more than 89% prediction accuracy for scratch/line types, and higher than 94% for all common wafer defect types.
{"title":"PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques","authors":"Katherine Shu-Min Li, Peter Yi-Yu Liao, Leon Chou, Ken Chau-Cheung Cheng, Andrew Yi-Ann Huang, Sying-Jyan Wang, G. Han","doi":"10.1109/ETS48528.2020.9131598","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131598","url":null,"abstract":"Wafermap defect pattern detection and diagnosis provide useful clue to yield learning. However, most wafermaps have no special spatial patterns and are full of noises, which make pattern recognition difficult. Specially, recognizing scratch and line types of defect patterns is a challenging problem for process and test engineers and it takes a lot of manpower to identify such patterns, as potential defective dies may exist on the scratch contour and become discontinuity points. However, such potential defective dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the obscure defective dies in potential scratch patterns and mark them as faulty. As a result, the quality and reliability of products can be significantly improved and cost of final test can be reduced. In this paper, we propose a systematic methodology to search for potential scratch/line defect types in wafers. A five-phase method is developed to enhance wafermaps such that automatic defect pattern recognition can be carried with high accuracy. Experimental results show the proposed method can achieve more than 89% prediction accuracy for scratch/line types, and higher than 94% for all common wafer defect types.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126307812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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