Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131564
Jong-Yun Yun, B. Nadeau-Dostie, Martin Keim, C. Dray, E. M. Boujamaa
eMRAM (embedded Magnetoresistive Random Access Memory) is an attractive solution in many non-volatile memory applications because of its small size, fast operation speed, and good endurance. However, due to a relatively small on/off resistance separation, it is a challenge to set an optimal reference resistance to reliably differentiate between a read memory data “1” and “0”. Several trimming circuits are described in the literature to finely adjust a reference resistance value. These circuits are controlled from chip inputs causing time-consuming tests and off-chip engineering analysis. This paper presents a fully automated on-chip trimming process leveraging existing memory BIST (Built-In Self-Test) resources. It analyzes a massive amount of array property data with a minimal number of tests and optimizes the reference trim settings on-chip without the need for any external intervention.
{"title":"MBIST Support for Reliable eMRAM Sensing","authors":"Jong-Yun Yun, B. Nadeau-Dostie, Martin Keim, C. Dray, E. M. Boujamaa","doi":"10.1109/ETS48528.2020.9131564","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131564","url":null,"abstract":"eMRAM (embedded Magnetoresistive Random Access Memory) is an attractive solution in many non-volatile memory applications because of its small size, fast operation speed, and good endurance. However, due to a relatively small on/off resistance separation, it is a challenge to set an optimal reference resistance to reliably differentiate between a read memory data “1” and “0”. Several trimming circuits are described in the literature to finely adjust a reference resistance value. These circuits are controlled from chip inputs causing time-consuming tests and off-chip engineering analysis. This paper presents a fully automated on-chip trimming process leveraging existing memory BIST (Built-In Self-Test) resources. It analyzes a massive amount of array property data with a minimal number of tests and optimizes the reference trim settings on-chip without the need for any external intervention.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117186504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131563
Hassan Ebrahimi, H. Kerkhoff
The dependability of highly dependable systems relies on the reliability of its components and interconnections. One of the most challenging faults that threatens the reliability of interconnections in a system are intermittent resistive faults (IRFs). They may occur randomly in time, duration and amplitude in every interconnection. The occurrence rate can vary from a few nanoseconds to months. As a result, evoking and detecting such faults is a major challenge. In this paper, IRF detection at the chip level has been tackled by utilising a fully digital insitu IRF monitor. This paper introduces a new algorithm for inserting IRF monitors in a design. The goal of this algorithm is to minimise the number of IRF monitors while providing a high fault coverage for IRFs. The algorithm has been validated using software-based fault injection. The simulation results show that the proposed algorithm improves the IRF coverage at the chip level at the cost of a small area and power-consumption overhead.
{"title":"A New Monitor Insertion Algorithm for Intermittent Fault Detection","authors":"Hassan Ebrahimi, H. Kerkhoff","doi":"10.1109/ETS48528.2020.9131563","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131563","url":null,"abstract":"The dependability of highly dependable systems relies on the reliability of its components and interconnections. One of the most challenging faults that threatens the reliability of interconnections in a system are intermittent resistive faults (IRFs). They may occur randomly in time, duration and amplitude in every interconnection. The occurrence rate can vary from a few nanoseconds to months. As a result, evoking and detecting such faults is a major challenge. In this paper, IRF detection at the chip level has been tackled by utilising a fully digital insitu IRF monitor. This paper introduces a new algorithm for inserting IRF monitors in a design. The goal of this algorithm is to minimise the number of IRF monitors while providing a high fault coverage for IRFs. The algorithm has been validated using software-based fault injection. The simulation results show that the proposed algorithm improves the IRF coverage at the chip level at the cost of a small area and power-consumption overhead.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123019897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131581
S. Sunter
Automotive applications are driving the need for a systematic way to decrease analog test escape rates to 0 DPPM, while providing functional safety. This tutorial briefly reviews the history of analog fault simulation, from academic simulation of basic shorts and opens, to the advent of industrial analog defect/fault simulators. Then it addresses the two biggest problems: no industry-accepted fault model, and impractically long simulation time. The solutions are the proposed IEEE P2427 standard for analog defect coverage, for which a brief summary of its requirements is provided, and a variety of methods to reduce total simulation time, such as defect collapsing, simulating only the most likely defects or likelihood-weighted randomly selection of defects, and parallel simulation.
{"title":"Analog Fault Simulation - a Hot Topic!","authors":"S. Sunter","doi":"10.1109/ETS48528.2020.9131581","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131581","url":null,"abstract":"Automotive applications are driving the need for a systematic way to decrease analog test escape rates to 0 DPPM, while providing functional safety. This tutorial briefly reviews the history of analog fault simulation, from academic simulation of basic shorts and opens, to the advent of industrial analog defect/fault simulators. Then it addresses the two biggest problems: no industry-accepted fault model, and impractically long simulation time. The solutions are the proposed IEEE P2427 standard for analog defect coverage, for which a brief summary of its requirements is provided, and a variety of methods to reduce total simulation time, such as defect collapsing, simulating only the most likely defects or likelihood-weighted randomly selection of defects, and parallel simulation.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115109785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131575
J. Tyszer, P. Maxwell
{"title":"ETS 2019 Best Paper","authors":"J. Tyszer, P. Maxwell","doi":"10.1109/ets48528.2020.9131575","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131575","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126926056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131584
{"title":"ETS 2020 Sponsors","authors":"","doi":"10.1109/ets48528.2020.9131584","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131584","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122318289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131570
{"title":"Title Page","authors":"","doi":"10.1109/ets48528.2020.9131570","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131570","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122197561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131587
Manhong Zhu, Jia Li, Weibing Wang, Dapeng Chen
Nowadays, MEMS testing has become a growing problem because it usually needs specific and sophisticated testing equipment and is very time-consuming. To solve this problem, this paper proposes a Built-In Self-Test (BIST) method for membrane MEMS piezoresistive sensor. With the proposed method, an on-chip electric signal can be used as the test stimuli, and process defects of piezoresistive sensor can be diagnosed by analyzing the output response of piezoresistive sensor on chip. The simulation shows that the proposed MEMS BIST scheme can effectively replace the physical testing stimuli with electric signal, thus reduce the dependence on external signal sources and the cost of manufacturing devices.
{"title":"A Built-In Self-Test Method For MEMS Piezoresistive Sensor","authors":"Manhong Zhu, Jia Li, Weibing Wang, Dapeng Chen","doi":"10.1109/ETS48528.2020.9131587","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131587","url":null,"abstract":"Nowadays, MEMS testing has become a growing problem because it usually needs specific and sophisticated testing equipment and is very time-consuming. To solve this problem, this paper proposes a Built-In Self-Test (BIST) method for membrane MEMS piezoresistive sensor. With the proposed method, an on-chip electric signal can be used as the test stimuli, and process defects of piezoresistive sensor can be diagnosed by analyzing the output response of piezoresistive sensor on chip. The simulation shows that the proposed MEMS BIST scheme can effectively replace the physical testing stimuli with electric signal, thus reduce the dependence on external signal sources and the cost of manufacturing devices.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"56 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123220024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131597
Daniel Oliveira, S. Blanchard, Nathan Debardeleben, F. Santos, Gabriel Piscoya Dávila, P. Navaux, C. Cazzaniga, C. Frost, R. Baumann, P. Rech
The high performance, high efficiency, and low cost of Commercial Off-The-Shelf (COTS) devices make them attractive for applications with strict reliability constraints. Today, COTS devices are adopted in HPC and safety-critical applications such as autonomous driving. Unfortunately, the cheap natural Boron widely used in COTS chip manufacturing process makes them highly susceptible to thermal (low energy) neutrons. In this paper, we demonstrate that thermal neutrons are a significant threat to COTS device reliability. For our study, we consider an AMD APU, three NVIDIA GPUs, an Intel accelerator, and an FPGA executing a relevant set of algorithms. We consider different scenarios that impact the thermal neutron flux such as weather, concrete walls and floors, and HPC liquid cooling systems. We show that thermal neutrons FIT rate could be comparable to the high energy neutron FIT rate.
{"title":"Thermal Neutrons: a Possible Threat for Supercomputers and Safety Critical Applications","authors":"Daniel Oliveira, S. Blanchard, Nathan Debardeleben, F. Santos, Gabriel Piscoya Dávila, P. Navaux, C. Cazzaniga, C. Frost, R. Baumann, P. Rech","doi":"10.1109/ETS48528.2020.9131597","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131597","url":null,"abstract":"The high performance, high efficiency, and low cost of Commercial Off-The-Shelf (COTS) devices make them attractive for applications with strict reliability constraints. Today, COTS devices are adopted in HPC and safety-critical applications such as autonomous driving. Unfortunately, the cheap natural Boron widely used in COTS chip manufacturing process makes them highly susceptible to thermal (low energy) neutrons. In this paper, we demonstrate that thermal neutrons are a significant threat to COTS device reliability. For our study, we consider an AMD APU, three NVIDIA GPUs, an Intel accelerator, and an FPGA executing a relevant set of algorithms. We consider different scenarios that impact the thermal neutron flux such as weather, concrete walls and floors, and HPC liquid cooling systems. We show that thermal neutrons FIT rate could be comparable to the high energy neutron FIT rate.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124943992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131601
S. Mhamdi, P. Girard, A. Virazel, A. Bosio, A. Ladhar
In this paper, we propose a new framework for cell-aware defect diagnosis of customer returns based on supervised learning. The proposed method comprehensively deals with static and dynamic defects that may occur in real circuits. A Naive Bayes classifier is used to precisely identify defect candidates. Results obtained on benchmark circuits, and comparison with a commercial cell-aware diagnosis tool, demonstrate the efficiency of the proposed approach in terms of accuracy and resolution.
{"title":"Learning-Based Cell-Aware Defect Diagnosis of Customer Returns","authors":"S. Mhamdi, P. Girard, A. Virazel, A. Bosio, A. Ladhar","doi":"10.1109/ETS48528.2020.9131601","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131601","url":null,"abstract":"In this paper, we propose a new framework for cell-aware defect diagnosis of customer returns based on supervised learning. The proposed method comprehensively deals with static and dynamic defects that may occur in real circuits. A Naive Bayes classifier is used to precisely identify defect candidates. Results obtained on benchmark circuits, and comparison with a commercial cell-aware diagnosis tool, demonstrate the efficiency of the proposed approach in terms of accuracy and resolution.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126991525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131599
A. Gaita, Georgian Nicolae, E. David, Andi Buzo, C. Burileanu, G. Pelz
This paper proposes a method for speeding-up the verification process of integrated circuits, featuring waveform clustering of circuit response signals. The main objective is to automatically separate the signals into distinct groups that potentially exhibit visual similarities in order to aid the visual inspection/verification. As a first step, the proposed method extracts SIFT-like features by finding stable points of the signal over the scale space and computing robust descriptors able to describe their neighborhood. The resulted descriptors are quantized in order to be used in the clustering process as bag-of-words histograms. We demonstrate the validity of our method on a circuit waveform database containing several thousands of signals belonging to ten electrical tests.
{"title":"A SIFT-based Waveform Clustering Method for aiding analog/mixed-signal IC Verification","authors":"A. Gaita, Georgian Nicolae, E. David, Andi Buzo, C. Burileanu, G. Pelz","doi":"10.1109/ETS48528.2020.9131599","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131599","url":null,"abstract":"This paper proposes a method for speeding-up the verification process of integrated circuits, featuring waveform clustering of circuit response signals. The main objective is to automatically separate the signals into distinct groups that potentially exhibit visual similarities in order to aid the visual inspection/verification. As a first step, the proposed method extracts SIFT-like features by finding stable points of the signal over the scale space and computing robust descriptors able to describe their neighborhood. The resulted descriptors are quantized in order to be used in the clustering process as bag-of-words histograms. We demonstrate the validity of our method on a circuit waveform database containing several thousands of signals belonging to ten electrical tests.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114976553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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