Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131593
Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Nektar Xama, Jhon Gomez, G. Gielen
In this work, a novel outlier detection method is presented in which the data from the visual inspection of manufactured wafers are combined with the data from the electrical test. Three different implementations are built with increasing complexity in order to detect outliers that are not detected by a traditional outlier detection method such as the Dynamic Part Average Testing (DPAT). The screening parameters are constructed as a reformulation of the DPAT formulas, integrating information from visual inspection and the layout of the used product. The proposed VEDPAT algorithms are applied to a total of 25 wafers spread over 5 lots in order to compare their effectiveness. The results show that a method that combines the available information with the layout is able to effectively screen out outliers at the expense of only a very small yield loss. Also, details and microscope pictures of the false alarms and outliers detected by the method are presented.
{"title":"Latent Defect Screening with Visually-Enhanced Dynamic Part Average Testing","authors":"Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Nektar Xama, Jhon Gomez, G. Gielen","doi":"10.1109/ETS48528.2020.9131593","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131593","url":null,"abstract":"In this work, a novel outlier detection method is presented in which the data from the visual inspection of manufactured wafers are combined with the data from the electrical test. Three different implementations are built with increasing complexity in order to detect outliers that are not detected by a traditional outlier detection method such as the Dynamic Part Average Testing (DPAT). The screening parameters are constructed as a reformulation of the DPAT formulas, integrating information from visual inspection and the layout of the used product. The proposed VEDPAT algorithms are applied to a total of 25 wafers spread over 5 lots in order to compare their effectiveness. The results show that a method that combines the available information with the layout is able to effectively screen out outliers at the expense of only a very small yield loss. Also, details and microscope pictures of the false alarms and outliers detected by the method are presented.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131058268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131574
B. Deveautour, Marcello Traiola, A. Virazel, P. Girard
In the last decade, Approximate Computing has become a trend topic for several error tolerant applications. In this context, the use of such paradigm for reducing the area and power cost of conventional fault tolerant schemes (i.e. Triple Modular Redundancy) has been investigated recently. Unfortunately, existing solutions cannot ensure the same level of reliability compared to conventional TMR. In this paper, we propose a novel fully robust approximation-based solution suitable for safety-critical applications that can reduce the cost compared to conventional TMR structures. This solution is based on the use of four approximate modules with an overall smaller area overhead compared to a TMR made of three precise modules. The main constraint is that, for a given output of the precise module, at least three approximate modules (among four) can feed the voter with the same output. In order to build our Quadruple Approximate Modular Redundancy (QAMR) structure, we use a simple and random process whose goal is to remove different outputs with the corresponding fan-in logic from each approximate module in such a way that the above constraint is satisfied. The majority voter and its mode of operation remains the same as in the TMR. To validate our approach, we conducted experiments and results demonstrate that it is possible to achieve the fault tolerance of a full TMR approach while reducing the area overhead up to 24.28%.
{"title":"QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction","authors":"B. Deveautour, Marcello Traiola, A. Virazel, P. Girard","doi":"10.1109/ETS48528.2020.9131574","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131574","url":null,"abstract":"In the last decade, Approximate Computing has become a trend topic for several error tolerant applications. In this context, the use of such paradigm for reducing the area and power cost of conventional fault tolerant schemes (i.e. Triple Modular Redundancy) has been investigated recently. Unfortunately, existing solutions cannot ensure the same level of reliability compared to conventional TMR. In this paper, we propose a novel fully robust approximation-based solution suitable for safety-critical applications that can reduce the cost compared to conventional TMR structures. This solution is based on the use of four approximate modules with an overall smaller area overhead compared to a TMR made of three precise modules. The main constraint is that, for a given output of the precise module, at least three approximate modules (among four) can feed the voter with the same output. In order to build our Quadruple Approximate Modular Redundancy (QAMR) structure, we use a simple and random process whose goal is to remove different outputs with the corresponding fan-in logic from each approximate module in such a way that the above constraint is satisfied. The majority voter and its mode of operation remains the same as in the TMR. To validate our approach, we conducted experiments and results demonstrate that it is possible to achieve the fault tolerance of a full TMR approach while reducing the area overhead up to 24.28%.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134413556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131604
M. Fieback, S. Nagarajan, R. Bishnoi, M. Tahoori, M. Taouil, S. Hamdioui
Today's von Neumann computing systems are facing major challenges making them not suitable for evolving ultralow power (e.g., edge computing) applications. Therefore, alternative architectures that make use of post-CMOS devices are under investigation. One of these architectures is computation-in-memory (CIM) based on memristive devices; it performs (parallel) computing within the memory core, which prevents data-movement and results in low energy consumption, at the cost of some modification in memory design. Hence, a CIM die can work either in memory configuration or in computation configuration. One implementation of this architecture is based on Scouting logic; it allows the execution of logic operations within the memory. This paper discusses fault modeling and testing of CIM architectures, applied to a Scouting logic-based architecture. It demonstrates that unique faults can occur in the CIM die while in the computation configuration, and that these faults cannot be detected by just testing the CIM die in the memory configuration, thus leading to test escapes. The paper demonstrates how an efficient test can be developed that detects all faults in both configurations. Moreover, it shows that testing the die in the computation configuration reduces the overall test time while improving the outgoing product quality.
{"title":"Testing Scouting Logic-Based Computation-in-Memory Architectures","authors":"M. Fieback, S. Nagarajan, R. Bishnoi, M. Tahoori, M. Taouil, S. Hamdioui","doi":"10.1109/ETS48528.2020.9131604","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131604","url":null,"abstract":"Today's von Neumann computing systems are facing major challenges making them not suitable for evolving ultralow power (e.g., edge computing) applications. Therefore, alternative architectures that make use of post-CMOS devices are under investigation. One of these architectures is computation-in-memory (CIM) based on memristive devices; it performs (parallel) computing within the memory core, which prevents data-movement and results in low energy consumption, at the cost of some modification in memory design. Hence, a CIM die can work either in memory configuration or in computation configuration. One implementation of this architecture is based on Scouting logic; it allows the execution of logic operations within the memory. This paper discusses fault modeling and testing of CIM architectures, applied to a Scouting logic-based architecture. It demonstrates that unique faults can occur in the CIM die while in the computation configuration, and that these faults cannot be detected by just testing the CIM die in the memory configuration, thus leading to test escapes. The paper demonstrates how an efficient test can be developed that detects all faults in both configurations. Moreover, it shows that testing the die in the computation configuration reduces the overall test time while improving the outgoing product quality.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130937498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131568
F. A. D. Silva, A. Bagbaba, Sandro Sartoni, R. Cantoro, M. Reorda, S. Hamdioui, C. Sauer
The development of Integrated Circuits for the Automotive sector imposes on major challenges. ISO26262 compliance, as part of this process, entails complex analysis for the evaluation of potential random hardware faults. This paper proposes a systematic approach to identify faults that do not disrupt safety-critical functionalities and consequently can be considered Safe. By deploying code coverage and Formal verification techniques, our methodology enables the classification of faults that are unclassified by other technologies, improving ISO26262 compliance. Our results, in combination with Fault Simulation, achieved a Diagnostic Coverage of 93% in a CAN Controller. These figures allow an initial assessment for an ASIL B configuration of the IP.
{"title":"Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs","authors":"F. A. D. Silva, A. Bagbaba, Sandro Sartoni, R. Cantoro, M. Reorda, S. Hamdioui, C. Sauer","doi":"10.1109/ETS48528.2020.9131568","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131568","url":null,"abstract":"The development of Integrated Circuits for the Automotive sector imposes on major challenges. ISO26262 compliance, as part of this process, entails complex analysis for the evaluation of potential random hardware faults. This paper proposes a systematic approach to identify faults that do not disrupt safety-critical functionalities and consequently can be considered Safe. By deploying code coverage and Formal verification techniques, our methodology enables the classification of faults that are unclassified by other technologies, improving ISO26262 compliance. Our results, in combination with Fault Simulation, achieved a Diagnostic Coverage of 93% in a CAN Controller. These figures allow an initial assessment for an ASIL B configuration of the IP.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114146646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131573
J. Laufenberg, T. Kropf, O. Bringmann
Modeling and validation of complex and highly connected systems involved in safety-critical tasks are great challenges today with little support in automation. A graph structure models the system and the faults component-by-component in the proposed approach and specifies valid systems. Automated generation and execution of test cases for every valid combination of components is done as well as monitoring and assessment of the system behavior. The integrated fault description provides faults from single bit-flip to comprehensive scenarios. The simulation is supervised and executed by the graph, which adapts the faults automatically during simulation with respect to the simulation state.
{"title":"Automated Graph-Based Fault Injection Into Virtual Prototypes for Robustness Evaluation","authors":"J. Laufenberg, T. Kropf, O. Bringmann","doi":"10.1109/ETS48528.2020.9131573","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131573","url":null,"abstract":"Modeling and validation of complex and highly connected systems involved in safety-critical tasks are great challenges today with little support in automation. A graph structure models the system and the faults component-by-component in the proposed approach and specifies valid systems. Automated generation and execution of test cases for every valid combination of components is done as well as monitoring and assessment of the system behavior. The integrated fault description provides faults from single bit-flip to comprehensive scenarios. The simulation is supervised and executed by the graph, which adapts the faults automatically during simulation with respect to the simulation state.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134391595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131554
Rana Elnaggar, Siyuan Chen, P. Song, K. Chakrabarty
Heterogeneous SoCs integrate FPGAs and microprocessor cores on the same fabric to accelerate applications such as cryptography and deep learning. Since FPGAs share resources with the microprocessor cores, they can launch non-cacheable SDRAM transactions through direct FPGA-to-microprocessor SDRAM interface. Therefore, if the FPGA 3rd party IPs (3PIPs) are malicious, they can launch rowhammer attacks on the SDRAM. Today's countermeasures based on performance counters cannot detect these attacks because memory transactions from FPGAs do not pass through the cache. In addition, countermeasures that count the frequency of activation of memory rows require structural changes to the memory controller or DRAM chips. Moreover, today's countermeasures cannot identify the IP that launches the attack. We present a security solution that monitors the SDRAM transactions from IPs on the FPGA to each bank of the microprocessor SDRAM through the FPGA-to-microprocessor SDRAM interface. The proposed monitor is implemented on the FPGA fabric. It can detect attempts to launch a rowhammer attack before it causes bit flips in the SDRAM. It utilizes only 1% of the adaptive logic modules (ALMs) available in an Intel Cyclone V FPGA to monitor the transactions from one IP.
异构soc将fpga和微处理器内核集成在同一结构上，以加速密码学和深度学习等应用。由于fpga与微处理器内核共享资源，它们可以通过直接fpga到微处理器的SDRAM接口启动不可缓存的SDRAM事务。因此，如果FPGA第三方ip (3pip)是恶意的，他们可以对SDRAM发起rowhammer攻击。目前基于性能计数器的对策无法检测到这些攻击，因为来自fpga的内存事务不通过缓存。此外，计算存储器行激活频率的对策需要对存储器控制器或DRAM芯片进行结构更改。此外，今天的对策无法识别发起攻击的IP。我们提出了一种安全解决方案，通过FPGA到微处理器SDRAM接口监控从FPGA上的ip到微处理器SDRAM的每组SDRAM事务。提出的监视器是在FPGA结构上实现的。它可以在引起SDRAM中的位翻转之前检测到发起打滑锤攻击的企图。它仅利用英特尔Cyclone V FPGA中可用的1%的自适应逻辑模块(alm)来监视来自一个IP的事务。
{"title":"Detection of Rowhammer Attacks in SoCs with FPGAs","authors":"Rana Elnaggar, Siyuan Chen, P. Song, K. Chakrabarty","doi":"10.1109/ETS48528.2020.9131554","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131554","url":null,"abstract":"Heterogeneous SoCs integrate FPGAs and microprocessor cores on the same fabric to accelerate applications such as cryptography and deep learning. Since FPGAs share resources with the microprocessor cores, they can launch non-cacheable SDRAM transactions through direct FPGA-to-microprocessor SDRAM interface. Therefore, if the FPGA 3rd party IPs (3PIPs) are malicious, they can launch rowhammer attacks on the SDRAM. Today's countermeasures based on performance counters cannot detect these attacks because memory transactions from FPGAs do not pass through the cache. In addition, countermeasures that count the frequency of activation of memory rows require structural changes to the memory controller or DRAM chips. Moreover, today's countermeasures cannot identify the IP that launches the attack. We present a security solution that monitors the SDRAM transactions from IPs on the FPGA to each bank of the microprocessor SDRAM through the FPGA-to-microprocessor SDRAM interface. The proposed monitor is implemented on the FPGA fabric. It can detect attempts to launch a rowhammer attack before it causes bit flips in the SDRAM. It utilizes only 1% of the adaptive logic modules (ALMs) available in an Intel Cyclone V FPGA to monitor the transactions from one IP.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133517399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131576
Rezgar Sadeghi, Z. Navabi
In very deep sub-micrometer technology nodes, signal integrity of interconnects has been drastically jeopardized by crosstalk noise. To make a communication link reliable against crosstalk faults, different detection, correction, and avoidance methods have been proposed at the cost of redundant spatial and information overheads. In this paper, we propose a crosstalk prediction hardware based on an abstract model deduced from low-level interconnect evaluation for new technologies. This predictor monitors the data pattern to be sent through a communication bus and predicts those likely subjected to the crosstalk fault. Thus, to prevent crosstalk faults, the predictor dynamically engages an avoidance or detection mechanism. Top-level buses are the target of the proposed method. Simulation results reveal that the proposed communication channel is more efficient in terms of crosstalk alleviation as well as area and performance overhead compared to the state of the art reliability methods.
{"title":"Built-In Predictors for Dynamic Crosstalk Avoidance","authors":"Rezgar Sadeghi, Z. Navabi","doi":"10.1109/ETS48528.2020.9131576","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131576","url":null,"abstract":"In very deep sub-micrometer technology nodes, signal integrity of interconnects has been drastically jeopardized by crosstalk noise. To make a communication link reliable against crosstalk faults, different detection, correction, and avoidance methods have been proposed at the cost of redundant spatial and information overheads. In this paper, we propose a crosstalk prediction hardware based on an abstract model deduced from low-level interconnect evaluation for new technologies. This predictor monitors the data pattern to be sent through a communication bus and predicts those likely subjected to the crosstalk fault. Thus, to prevent crosstalk faults, the predictor dynamically engages an avoidance or detection mechanism. Top-level buses are the target of the proposed method. Simulation results reveal that the proposed communication channel is more efficient in terms of crosstalk alleviation as well as area and performance overhead compared to the state of the art reliability methods.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123658768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131564
Jong-Yun Yun, B. Nadeau-Dostie, Martin Keim, C. Dray, E. M. Boujamaa
eMRAM (embedded Magnetoresistive Random Access Memory) is an attractive solution in many non-volatile memory applications because of its small size, fast operation speed, and good endurance. However, due to a relatively small on/off resistance separation, it is a challenge to set an optimal reference resistance to reliably differentiate between a read memory data “1” and “0”. Several trimming circuits are described in the literature to finely adjust a reference resistance value. These circuits are controlled from chip inputs causing time-consuming tests and off-chip engineering analysis. This paper presents a fully automated on-chip trimming process leveraging existing memory BIST (Built-In Self-Test) resources. It analyzes a massive amount of array property data with a minimal number of tests and optimizes the reference trim settings on-chip without the need for any external intervention.
{"title":"MBIST Support for Reliable eMRAM Sensing","authors":"Jong-Yun Yun, B. Nadeau-Dostie, Martin Keim, C. Dray, E. M. Boujamaa","doi":"10.1109/ETS48528.2020.9131564","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131564","url":null,"abstract":"eMRAM (embedded Magnetoresistive Random Access Memory) is an attractive solution in many non-volatile memory applications because of its small size, fast operation speed, and good endurance. However, due to a relatively small on/off resistance separation, it is a challenge to set an optimal reference resistance to reliably differentiate between a read memory data “1” and “0”. Several trimming circuits are described in the literature to finely adjust a reference resistance value. These circuits are controlled from chip inputs causing time-consuming tests and off-chip engineering analysis. This paper presents a fully automated on-chip trimming process leveraging existing memory BIST (Built-In Self-Test) resources. It analyzes a massive amount of array property data with a minimal number of tests and optimizes the reference trim settings on-chip without the need for any external intervention.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117186504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131563
Hassan Ebrahimi, H. Kerkhoff
The dependability of highly dependable systems relies on the reliability of its components and interconnections. One of the most challenging faults that threatens the reliability of interconnections in a system are intermittent resistive faults (IRFs). They may occur randomly in time, duration and amplitude in every interconnection. The occurrence rate can vary from a few nanoseconds to months. As a result, evoking and detecting such faults is a major challenge. In this paper, IRF detection at the chip level has been tackled by utilising a fully digital insitu IRF monitor. This paper introduces a new algorithm for inserting IRF monitors in a design. The goal of this algorithm is to minimise the number of IRF monitors while providing a high fault coverage for IRFs. The algorithm has been validated using software-based fault injection. The simulation results show that the proposed algorithm improves the IRF coverage at the chip level at the cost of a small area and power-consumption overhead.
{"title":"A New Monitor Insertion Algorithm for Intermittent Fault Detection","authors":"Hassan Ebrahimi, H. Kerkhoff","doi":"10.1109/ETS48528.2020.9131563","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131563","url":null,"abstract":"The dependability of highly dependable systems relies on the reliability of its components and interconnections. One of the most challenging faults that threatens the reliability of interconnections in a system are intermittent resistive faults (IRFs). They may occur randomly in time, duration and amplitude in every interconnection. The occurrence rate can vary from a few nanoseconds to months. As a result, evoking and detecting such faults is a major challenge. In this paper, IRF detection at the chip level has been tackled by utilising a fully digital insitu IRF monitor. This paper introduces a new algorithm for inserting IRF monitors in a design. The goal of this algorithm is to minimise the number of IRF monitors while providing a high fault coverage for IRFs. The algorithm has been validated using software-based fault injection. The simulation results show that the proposed algorithm improves the IRF coverage at the chip level at the cost of a small area and power-consumption overhead.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123019897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131581
S. Sunter
Automotive applications are driving the need for a systematic way to decrease analog test escape rates to 0 DPPM, while providing functional safety. This tutorial briefly reviews the history of analog fault simulation, from academic simulation of basic shorts and opens, to the advent of industrial analog defect/fault simulators. Then it addresses the two biggest problems: no industry-accepted fault model, and impractically long simulation time. The solutions are the proposed IEEE P2427 standard for analog defect coverage, for which a brief summary of its requirements is provided, and a variety of methods to reduce total simulation time, such as defect collapsing, simulating only the most likely defects or likelihood-weighted randomly selection of defects, and parallel simulation.
{"title":"Analog Fault Simulation - a Hot Topic!","authors":"S. Sunter","doi":"10.1109/ETS48528.2020.9131581","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131581","url":null,"abstract":"Automotive applications are driving the need for a systematic way to decrease analog test escape rates to 0 DPPM, while providing functional safety. This tutorial briefly reviews the history of analog fault simulation, from academic simulation of basic shorts and opens, to the advent of industrial analog defect/fault simulators. Then it addresses the two biggest problems: no industry-accepted fault model, and impractically long simulation time. The solutions are the proposed IEEE P2427 standard for analog defect coverage, for which a brief summary of its requirements is provided, and a variety of methods to reduce total simulation time, such as defect collapsing, simulating only the most likely defects or likelihood-weighted randomly selection of defects, and parallel simulation.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115109785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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