Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131567
Min-Chun Hu, Zhan Gao, Santosh Malagi, J. Swenton, J. Huisken, K. Goossens, Cheng-Wen Wu, E. Marinissen
Cell-aware test (CAT) explicitly targets faults caused by cell-internal short and open defects and has been shown to significantly reduce test escape rates. CAT library cell characterization is typically done for only two defect resistance values: one representing hard opens and another one representing hard shorts. In this paper, similar to fishermen tightening the mesh size of their nets to catch small fish, we perform library characterization as efficiently as possible for a set of resistances representing increasingly weaker defects, and then adjust our ATPG flow to explicitly target faults caused by the weakest still-detectable variant of each potential defect. We implemented this novel approach in an experimental ATPG tool flow script, using functions of Cadence's Modus as building blocks. To assess the effectiveness of our approach, we formulate a new dedicated test metric: the weakest fault coverage wfc. Compared to conventional CAT targeting hard defects only, experimental results show that our new approach enhances detection of weakest faults and significantly reduces wfc escapes =1-wfc, while maintaining its original (hard-defect) fault coverage fc, of course at the expense of (acceptable) increases in the required number of test patterns and associated test generation time.
{"title":"Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults","authors":"Min-Chun Hu, Zhan Gao, Santosh Malagi, J. Swenton, J. Huisken, K. Goossens, Cheng-Wen Wu, E. Marinissen","doi":"10.1109/ETS48528.2020.9131567","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131567","url":null,"abstract":"Cell-aware test (CAT) explicitly targets faults caused by cell-internal short and open defects and has been shown to significantly reduce test escape rates. CAT library cell characterization is typically done for only two defect resistance values: one representing hard opens and another one representing hard shorts. In this paper, similar to fishermen tightening the mesh size of their nets to catch small fish, we perform library characterization as efficiently as possible for a set of resistances representing increasingly weaker defects, and then adjust our ATPG flow to explicitly target faults caused by the weakest still-detectable variant of each potential defect. We implemented this novel approach in an experimental ATPG tool flow script, using functions of Cadence's Modus as building blocks. To assess the effectiveness of our approach, we formulate a new dedicated test metric: the weakest fault coverage wfc. Compared to conventional CAT targeting hard defects only, experimental results show that our new approach enhances detection of weakest faults and significantly reduces wfc escapes =1-wfc, while maintaining its original (hard-defect) fault coverage fc, of course at the expense of (acceptable) increases in the required number of test patterns and associated test generation time.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128225161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131571
M. Portolan, Vincent Reynaud, P. Maistri, R. Leveugle
The complexity of modern Systems-on-Chips is steadily increasing, which poses hard challenges for testing. In order to be able to face those challenges, several standards have been proposed through history, such as the latest IEEE 1687 on Reconfigurable Scan Networks (RSNs), which allows dynamic configuration of the test infrastructure for an easier access to embedded instruments and data. This ease of access, however, may constitute a serious threat from the point of view of security, as it may be used by an attacker as an entry point to the internal state of the circuit, especially if the test infrastructure is reused for life-time testing. Some approaches exist to protect the access, but their performances and security levels are limited by the legacy view of test as a static process. In this paper, we propose an innovative solution that exploits the dynamic nature of the IEEE 1687 standard to obtain an Authentication-based Secure Access framework able to provide a trusted and personalized interface to the test infrastructure depending on user-defined security levels.
{"title":"Dynamic Authentication-Based Secure Access to Test Infrastructure","authors":"M. Portolan, Vincent Reynaud, P. Maistri, R. Leveugle","doi":"10.1109/ETS48528.2020.9131571","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131571","url":null,"abstract":"The complexity of modern Systems-on-Chips is steadily increasing, which poses hard challenges for testing. In order to be able to face those challenges, several standards have been proposed through history, such as the latest IEEE 1687 on Reconfigurable Scan Networks (RSNs), which allows dynamic configuration of the test infrastructure for an easier access to embedded instruments and data. This ease of access, however, may constitute a serious threat from the point of view of security, as it may be used by an attacker as an entry point to the internal state of the circuit, especially if the test infrastructure is reused for life-time testing. Some approaches exist to protect the access, but their performances and security levels are limited by the legacy view of test as a static process. In this paper, we propose an innovative solution that exploits the dynamic nature of the IEEE 1687 standard to obtain an Authentication-based Secure Access framework able to provide a trusted and personalized interface to the test infrastructure depending on user-defined security levels.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128651318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131589
{"title":"Blank Page","authors":"","doi":"10.1109/ets48528.2020.9131589","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131589","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131219025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131590
Farimah Farahmandi, O. Sinanoglu, R. D. Blanton, S. Pagliarini
The current state of the integrated circuit (IC) ecosystem is that only a handful of foundries are at the forefront, continuously pushing the state of the art in transistor miniaturization. Establishing and maintaining a FinFET-capable foundry is a billion dollar endeavor. This scenario dictates that many companies and governments have to develop their systems and products by relying on 3rd party IC fabrication. The major caveat within this practice is that the procured silicon cannot be blindly trusted: a malicious foundry can effectively modify the layout of the IC, reverse engineer its IPs, and overproduce the entire chip. The Hardware Security community has proposed many countermeasures to these threats. Notably, obfuscation has gained a lot of traction - here, the intent is to hide the functionality from the untrusted foundry such that the aforementioned threats are hindered or mitigated. In this paper, we summarize the research efforts of three independent research groups towards achieving trustworthy ICs, even when fabricated in untrusted offshore foundries. We extensively address the use of logic locking and its many variants, as well as the use of high-level synthesis (HLS) as an obfuscation approach of its own.
{"title":"Design Obfuscation versus Test","authors":"Farimah Farahmandi, O. Sinanoglu, R. D. Blanton, S. Pagliarini","doi":"10.1109/ETS48528.2020.9131590","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131590","url":null,"abstract":"The current state of the integrated circuit (IC) ecosystem is that only a handful of foundries are at the forefront, continuously pushing the state of the art in transistor miniaturization. Establishing and maintaining a FinFET-capable foundry is a billion dollar endeavor. This scenario dictates that many companies and governments have to develop their systems and products by relying on 3rd party IC fabrication. The major caveat within this practice is that the procured silicon cannot be blindly trusted: a malicious foundry can effectively modify the layout of the IC, reverse engineer its IPs, and overproduce the entire chip. The Hardware Security community has proposed many countermeasures to these threats. Notably, obfuscation has gained a lot of traction - here, the intent is to hide the functionality from the untrusted foundry such that the aforementioned threats are hindered or mitigated. In this paper, we summarize the research efforts of three independent research groups towards achieving trustworthy ICs, even when fabricated in untrusted offshore foundries. We extensively address the use of logic locking and its many variants, as well as the use of high-level synthesis (HLS) as an obfuscation approach of its own.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130081585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131582
S. Nair, Christopher Münch, M. Tahoori
Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), as one of the most promising emerging memory technology for on-chip memory, offers many advantageous features such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Additionally, its resistive storage concept can be utilized for Compute-in-Memory (CiM), where bit-wise logical operations can be performed within the memory without the need for transferring the data from the memory to the processor and back. However, these new CiM operations are impacted by defects, resulting in faults which are different from the conventional memory faults. Hence, these CiM specific faults need to be modeled and appropriate test strategies need to be derived to ensure correct functionality of the CiM enabled memories. In this paper, we first perform extensive defect injection in the CiM bit-cell and build fault models based on the impact of the defects. We also compare CiM specific faults to normal memory faults based on this technology. From this model, we derive an efficient test algorithm to fully cover CiM related faults, which cannot be found with conventional memory test algorithms.
{"title":"Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory","authors":"S. Nair, Christopher Münch, M. Tahoori","doi":"10.1109/ETS48528.2020.9131582","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131582","url":null,"abstract":"Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), as one of the most promising emerging memory technology for on-chip memory, offers many advantageous features such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Additionally, its resistive storage concept can be utilized for Compute-in-Memory (CiM), where bit-wise logical operations can be performed within the memory without the need for transferring the data from the memory to the processor and back. However, these new CiM operations are impacted by defects, resulting in faults which are different from the conventional memory faults. Hence, these CiM specific faults need to be modeled and appropriate test strategies need to be derived to ensure correct functionality of the CiM enabled memories. In this paper, we first perform extensive defect injection in the CiM bit-cell and build fault models based on the impact of the defects. We also compare CiM specific faults to normal memory faults based on this technology. From this model, we derive an efficient test algorithm to fully cover CiM related faults, which cannot be found with conventional memory test algorithms.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130514476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131602
Nektar Xama, Jakob Raymaekers, M. Andraud, Jhon Gomez, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, G. Gielen
With tightening automotive IC production test requirements, test escape rates need to decrease down to the 10 PPB level. To achieve this for mixed-signal ICs, advanced multivariate statistical techniques are needed, as the defects in the test escapes become increasingly more difficult to detect. Therefore, this paper proposes applying a cascade of advanced statistical techniques to identify measurements that can be used as predictors to flag future potential failures at test time with minimal misclassification of good devices. The approach uses measurement data from the ATE wafer probe tests and is also able to identify the likely location of the defect using only these measurements. The cascade has four steps: 1) remove bias and spatial patterns within the data, 2) divide the different tests into relevant groups, 3) reduce the dimensionality of each group, and 4) perform multiple regression to find the predictor values and use these values to compute an outlier score for each chip under test. As there is a risk of overfitting the outlier score, the number of predictors used is kept to a minimum. The effectiveness of the proposed methodology is demonstrated using test data from an industrial production chip with eight field-return cases. Predictors have been found that retroactively allowed the identification of these chips, with an average of 5% false classification of good devices, i.e. devices not returned from the field. In addition, the selected predictors corresponded to where the defects are located according to failure analysis of the field returns.
{"title":"Avoiding Mixed-Signal Field Returns by Outlier Detection of Hard-to-Detect Defects based on Multivariate Statistics","authors":"Nektar Xama, Jakob Raymaekers, M. Andraud, Jhon Gomez, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, G. Gielen","doi":"10.1109/ETS48528.2020.9131602","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131602","url":null,"abstract":"With tightening automotive IC production test requirements, test escape rates need to decrease down to the 10 PPB level. To achieve this for mixed-signal ICs, advanced multivariate statistical techniques are needed, as the defects in the test escapes become increasingly more difficult to detect. Therefore, this paper proposes applying a cascade of advanced statistical techniques to identify measurements that can be used as predictors to flag future potential failures at test time with minimal misclassification of good devices. The approach uses measurement data from the ATE wafer probe tests and is also able to identify the likely location of the defect using only these measurements. The cascade has four steps: 1) remove bias and spatial patterns within the data, 2) divide the different tests into relevant groups, 3) reduce the dimensionality of each group, and 4) perform multiple regression to find the predictor values and use these values to compute an outlier score for each chip under test. As there is a risk of overfitting the outlier score, the number of predictors used is kept to a minimum. The effectiveness of the proposed methodology is demonstrated using test data from an industrial production chip with eight field-return cases. Predictors have been found that retroactively allowed the identification of these chips, with an average of 5% false classification of good devices, i.e. devices not returned from the field. In addition, the selected predictors corresponded to where the defects are located according to failure analysis of the field returns.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126092653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131560
M. Elshamy, G. D. Natale, Antonios Pavlidis, M. Louërat, H. Stratigopoulos
We present a Hardware Trojan (HT) attack scenario for analog circuits. The characteristic of this HT is that it does not reside inside the victim analog circuit. Instead, it resides on an independent digital circuit on the same die where it is triggered, yet its payload is applied only to the analog circuit after being transferred via the common test infrastructure and the test interface of the analog circuit. This HT attack cannot be detected or prevented in the analog domain and it exploits the dense digital circuit to hide effectively its footprint.
{"title":"Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism","authors":"M. Elshamy, G. D. Natale, Antonios Pavlidis, M. Louërat, H. Stratigopoulos","doi":"10.1109/ETS48528.2020.9131560","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131560","url":null,"abstract":"We present a Hardware Trojan (HT) attack scenario for analog circuits. The characteristic of this HT is that it does not reside inside the victim analog circuit. Instead, it resides on an independent digital circuit on the same die where it is triggered, yet its payload is applied only to the analog circuit after being transferred via the common test infrastructure and the test interface of the analog circuit. This HT attack cannot be detected or prevented in the analog domain and it exploits the dense digital circuit to hide effectively its footprint.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116359249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131562
Bruno E. Forlin, R. Husemann, L. Carro, C. Reinbrecht, S. Hamdioui, M. Taouil
Physically Unclonable Functions (PUFs) are security primitives that provide trustworthy hardware for key-generation and device authentication. Among them, in contrast to dedicated PUFs, intrinsic PUFs are created from existing hardware components that exploit their variability through software. In this work we focus on GPUs and present G-PUF, a PUF implemented entirely in software on CUDA and hence does not require hardware modifications. Our results show that G-PUF has comparable characteristics to SRAM and DRAM PUFs in terms of uniformity 55.61% and reliability 90.09%.
{"title":"G-PUF: An Intrinsic PUF Based on GPU Error Signatures","authors":"Bruno E. Forlin, R. Husemann, L. Carro, C. Reinbrecht, S. Hamdioui, M. Taouil","doi":"10.1109/ETS48528.2020.9131562","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131562","url":null,"abstract":"Physically Unclonable Functions (PUFs) are security primitives that provide trustworthy hardware for key-generation and device authentication. Among them, in contrast to dedicated PUFs, intrinsic PUFs are created from existing hardware components that exploit their variability through software. In this work we focus on GPUs and present G-PUF, a PUF implemented entirely in software on CUDA and hence does not require hardware modifications. Our results show that G-PUF has comparable characteristics to SRAM and DRAM PUFs in terms of uniformity 55.61% and reliability 90.09%.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125422819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131586
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, S. Reddy, M. Kassab, J. Rajski
A novel method to efficiently and accurately prognosticate the pattern count at different input compression ratios with the Embedded Deterministic Test (EDT) compression technology is proposed. With this method the total ATPG run time can be significantly reduced compared to the currently used trial-and-error method.
{"title":"Efficient Prognostication of Pattern Count with Different Input Compression Ratios","authors":"Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, S. Reddy, M. Kassab, J. Rajski","doi":"10.1109/ETS48528.2020.9131586","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131586","url":null,"abstract":"A novel method to efficiently and accurately prognosticate the pattern count at different input compression ratios with the Embedded Deterministic Test (EDT) compression technology is proposed. With this method the total ATPG run time can be significantly reduced compared to the currently used trial-and-error method.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125157379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131591
Ching-Yuan Chen, C. Cheng, Jiun-Lang Huang, K. Chakrabarty
For high-performance integrated circuits with tight timing budgets, full-scan based transition delay fault (TDF) testing is mandatory to ensure high test quality. However, the discrepancy between the scan test mode and the functional mode is problematic. For example, the elevated switching activity during scan test application may degrade circuit performance and lead to overkill. In this paper, we address this problem by generating functional-like TDF test patterns. First, a Bayesian-based circuit model is constructed; the result is an enumeration of circuit states that closely mimics the functional mode. During test generation, the model guides the backtrace and fault propagation procedures more effectively than the conventional SCOAP or COP measures because reconvergent fanout is implicitly included in the model. Experimental results on processor benchmarks, including a MIPS32 and a RISC-V processor, show that the TDF test set generated using the Bayesian-based circuit model not only is more functional-like, but also achieves higher fault coverage.
{"title":"Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model","authors":"Ching-Yuan Chen, C. Cheng, Jiun-Lang Huang, K. Chakrabarty","doi":"10.1109/ETS48528.2020.9131591","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131591","url":null,"abstract":"For high-performance integrated circuits with tight timing budgets, full-scan based transition delay fault (TDF) testing is mandatory to ensure high test quality. However, the discrepancy between the scan test mode and the functional mode is problematic. For example, the elevated switching activity during scan test application may degrade circuit performance and lead to overkill. In this paper, we address this problem by generating functional-like TDF test patterns. First, a Bayesian-based circuit model is constructed; the result is an enumeration of circuit states that closely mimics the functional mode. During test generation, the model guides the backtrace and fault propagation procedures more effectively than the conventional SCOAP or COP measures because reconvergent fanout is implicitly included in the model. Experimental results on processor benchmarks, including a MIPS32 and a RISC-V processor, show that the TDF test set generated using the Bayesian-based circuit model not only is more functional-like, but also achieves higher fault coverage.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122252616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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