Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131595
M. Portolan, J. Rearick, Martin Keim
This paper introduces a standards-based framework which enables two types of test re-use: direct re-use of test patterns written for low-level components of a system, and access by high-level tests of test features embedded within the low-level components. The underlying mechanism for both is the encapsulation, retargeting, and transformation of test procedures through successive layers of hardware interfaces, as codified in two standards being developed by IEEE Working Groups (P1687.1 and P2654). Examples demonstrate the steps in the process and illustrate both the challenges and opportunities of this approach.
{"title":"Linking Chip, Board, and System Test via Standards","authors":"M. Portolan, J. Rearick, Martin Keim","doi":"10.1109/ETS48528.2020.9131595","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131595","url":null,"abstract":"This paper introduces a standards-based framework which enables two types of test re-use: direct re-use of test patterns written for low-level components of a system, and access by high-level tests of test features embedded within the low-level components. The underlying mechanism for both is the encapsulation, retargeting, and transformation of test procedures through successive layers of hardware interfaces, as codified in two standards being developed by IEEE Working Groups (P1687.1 and P2654). Examples demonstrate the steps in the process and illustrate both the challenges and opportunities of this approach.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122372973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131602
Nektar Xama, Jakob Raymaekers, M. Andraud, Jhon Gomez, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, G. Gielen
With tightening automotive IC production test requirements, test escape rates need to decrease down to the 10 PPB level. To achieve this for mixed-signal ICs, advanced multivariate statistical techniques are needed, as the defects in the test escapes become increasingly more difficult to detect. Therefore, this paper proposes applying a cascade of advanced statistical techniques to identify measurements that can be used as predictors to flag future potential failures at test time with minimal misclassification of good devices. The approach uses measurement data from the ATE wafer probe tests and is also able to identify the likely location of the defect using only these measurements. The cascade has four steps: 1) remove bias and spatial patterns within the data, 2) divide the different tests into relevant groups, 3) reduce the dimensionality of each group, and 4) perform multiple regression to find the predictor values and use these values to compute an outlier score for each chip under test. As there is a risk of overfitting the outlier score, the number of predictors used is kept to a minimum. The effectiveness of the proposed methodology is demonstrated using test data from an industrial production chip with eight field-return cases. Predictors have been found that retroactively allowed the identification of these chips, with an average of 5% false classification of good devices, i.e. devices not returned from the field. In addition, the selected predictors corresponded to where the defects are located according to failure analysis of the field returns.
{"title":"Avoiding Mixed-Signal Field Returns by Outlier Detection of Hard-to-Detect Defects based on Multivariate Statistics","authors":"Nektar Xama, Jakob Raymaekers, M. Andraud, Jhon Gomez, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, G. Gielen","doi":"10.1109/ETS48528.2020.9131602","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131602","url":null,"abstract":"With tightening automotive IC production test requirements, test escape rates need to decrease down to the 10 PPB level. To achieve this for mixed-signal ICs, advanced multivariate statistical techniques are needed, as the defects in the test escapes become increasingly more difficult to detect. Therefore, this paper proposes applying a cascade of advanced statistical techniques to identify measurements that can be used as predictors to flag future potential failures at test time with minimal misclassification of good devices. The approach uses measurement data from the ATE wafer probe tests and is also able to identify the likely location of the defect using only these measurements. The cascade has four steps: 1) remove bias and spatial patterns within the data, 2) divide the different tests into relevant groups, 3) reduce the dimensionality of each group, and 4) perform multiple regression to find the predictor values and use these values to compute an outlier score for each chip under test. As there is a risk of overfitting the outlier score, the number of predictors used is kept to a minimum. The effectiveness of the proposed methodology is demonstrated using test data from an industrial production chip with eight field-return cases. Predictors have been found that retroactively allowed the identification of these chips, with an average of 5% false classification of good devices, i.e. devices not returned from the field. In addition, the selected predictors corresponded to where the defects are located according to failure analysis of the field returns.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126092653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131594
David Knichel, Thorben Moos, A. Moradi
Side-channel analysis (SCA) attacks - especially power analysis - are powerful ways to extract the secrets stored in and processed by cryptographic devices. In recent years, researchers have shown interest in utilizing on-chip measurement facilities to perform such SCA attacks remotely. It was shown that simple voltage-monitoring sensors can be constructed from digital elements and put on multi-tenant FPGAs to perform remote attacks on neighbouring cryptographic co-processors. A similar threat is the unsuspecting integration of third-party IP-Cores into an IC design. Even if the function of an acquired IP-Core is not security critical by itself, it may contain an on-chip sensor as a Trojan that can eavesdrop on cryptographic operations across the whole device. In contrast to all FPGA-based investigations reported in the literature so far, we examine the efficiency of such on-chip sensors as a source of information leakage in an ASIC-based case study for the first time. To this end, in addition to a cryptographic core (lightweight block cipher PRESENT) we designed and implemented a voltage-monitoring sensor on an ASIC fabricated by a 40 nm commercial standard cell library. Despite the physical distance between the sensor and the PRESENT core, we show the possibility of fully recovering the secret key of the PRESENT core by processing the sensor's output. Our results imply that the hidden insertion of such a sensor - for example by a malicious third party IP-Core vendor - can endanger the security of embedded systems which deal with sensitive information, even if the device cannot be physically accessed by the adversary.
{"title":"The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs","authors":"David Knichel, Thorben Moos, A. Moradi","doi":"10.1109/ETS48528.2020.9131594","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131594","url":null,"abstract":"Side-channel analysis (SCA) attacks - especially power analysis - are powerful ways to extract the secrets stored in and processed by cryptographic devices. In recent years, researchers have shown interest in utilizing on-chip measurement facilities to perform such SCA attacks remotely. It was shown that simple voltage-monitoring sensors can be constructed from digital elements and put on multi-tenant FPGAs to perform remote attacks on neighbouring cryptographic co-processors. A similar threat is the unsuspecting integration of third-party IP-Cores into an IC design. Even if the function of an acquired IP-Core is not security critical by itself, it may contain an on-chip sensor as a Trojan that can eavesdrop on cryptographic operations across the whole device. In contrast to all FPGA-based investigations reported in the literature so far, we examine the efficiency of such on-chip sensors as a source of information leakage in an ASIC-based case study for the first time. To this end, in addition to a cryptographic core (lightweight block cipher PRESENT) we designed and implemented a voltage-monitoring sensor on an ASIC fabricated by a 40 nm commercial standard cell library. Despite the physical distance between the sensor and the PRESENT core, we show the possibility of fully recovering the secret key of the PRESENT core by processing the sensor's output. Our results imply that the hidden insertion of such a sensor - for example by a malicious third party IP-Core vendor - can endanger the security of embedded systems which deal with sensitive information, even if the device cannot be physically accessed by the adversary.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114893796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131582
S. Nair, Christopher Münch, M. Tahoori
Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), as one of the most promising emerging memory technology for on-chip memory, offers many advantageous features such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Additionally, its resistive storage concept can be utilized for Compute-in-Memory (CiM), where bit-wise logical operations can be performed within the memory without the need for transferring the data from the memory to the processor and back. However, these new CiM operations are impacted by defects, resulting in faults which are different from the conventional memory faults. Hence, these CiM specific faults need to be modeled and appropriate test strategies need to be derived to ensure correct functionality of the CiM enabled memories. In this paper, we first perform extensive defect injection in the CiM bit-cell and build fault models based on the impact of the defects. We also compare CiM specific faults to normal memory faults based on this technology. From this model, we derive an efficient test algorithm to fully cover CiM related faults, which cannot be found with conventional memory test algorithms.
{"title":"Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory","authors":"S. Nair, Christopher Münch, M. Tahoori","doi":"10.1109/ETS48528.2020.9131582","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131582","url":null,"abstract":"Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), as one of the most promising emerging memory technology for on-chip memory, offers many advantageous features such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Additionally, its resistive storage concept can be utilized for Compute-in-Memory (CiM), where bit-wise logical operations can be performed within the memory without the need for transferring the data from the memory to the processor and back. However, these new CiM operations are impacted by defects, resulting in faults which are different from the conventional memory faults. Hence, these CiM specific faults need to be modeled and appropriate test strategies need to be derived to ensure correct functionality of the CiM enabled memories. In this paper, we first perform extensive defect injection in the CiM bit-cell and build fault models based on the impact of the defects. We also compare CiM specific faults to normal memory faults based on this technology. From this model, we derive an efficient test algorithm to fully cover CiM related faults, which cannot be found with conventional memory test algorithms.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130514476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131589
{"title":"Blank Page","authors":"","doi":"10.1109/ets48528.2020.9131589","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131589","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131219025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ets48528.2020.9131561
Anonymous
{"title":"Half Title","authors":"Anonymous","doi":"10.1109/ets48528.2020.9131561","DOIUrl":"https://doi.org/10.1109/ets48528.2020.9131561","url":null,"abstract":"","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"30 25","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141207530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131568
F. A. D. Silva, A. Bagbaba, Sandro Sartoni, R. Cantoro, M. Reorda, S. Hamdioui, C. Sauer
The development of Integrated Circuits for the Automotive sector imposes on major challenges. ISO26262 compliance, as part of this process, entails complex analysis for the evaluation of potential random hardware faults. This paper proposes a systematic approach to identify faults that do not disrupt safety-critical functionalities and consequently can be considered Safe. By deploying code coverage and Formal verification techniques, our methodology enables the classification of faults that are unclassified by other technologies, improving ISO26262 compliance. Our results, in combination with Fault Simulation, achieved a Diagnostic Coverage of 93% in a CAN Controller. These figures allow an initial assessment for an ASIL B configuration of the IP.
{"title":"Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs","authors":"F. A. D. Silva, A. Bagbaba, Sandro Sartoni, R. Cantoro, M. Reorda, S. Hamdioui, C. Sauer","doi":"10.1109/ETS48528.2020.9131568","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131568","url":null,"abstract":"The development of Integrated Circuits for the Automotive sector imposes on major challenges. ISO26262 compliance, as part of this process, entails complex analysis for the evaluation of potential random hardware faults. This paper proposes a systematic approach to identify faults that do not disrupt safety-critical functionalities and consequently can be considered Safe. By deploying code coverage and Formal verification techniques, our methodology enables the classification of faults that are unclassified by other technologies, improving ISO26262 compliance. Our results, in combination with Fault Simulation, achieved a Diagnostic Coverage of 93% in a CAN Controller. These figures allow an initial assessment for an ASIL B configuration of the IP.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114146646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131573
J. Laufenberg, T. Kropf, O. Bringmann
Modeling and validation of complex and highly connected systems involved in safety-critical tasks are great challenges today with little support in automation. A graph structure models the system and the faults component-by-component in the proposed approach and specifies valid systems. Automated generation and execution of test cases for every valid combination of components is done as well as monitoring and assessment of the system behavior. The integrated fault description provides faults from single bit-flip to comprehensive scenarios. The simulation is supervised and executed by the graph, which adapts the faults automatically during simulation with respect to the simulation state.
{"title":"Automated Graph-Based Fault Injection Into Virtual Prototypes for Robustness Evaluation","authors":"J. Laufenberg, T. Kropf, O. Bringmann","doi":"10.1109/ETS48528.2020.9131573","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131573","url":null,"abstract":"Modeling and validation of complex and highly connected systems involved in safety-critical tasks are great challenges today with little support in automation. A graph structure models the system and the faults component-by-component in the proposed approach and specifies valid systems. Automated generation and execution of test cases for every valid combination of components is done as well as monitoring and assessment of the system behavior. The integrated fault description provides faults from single bit-flip to comprehensive scenarios. The simulation is supervised and executed by the graph, which adapts the faults automatically during simulation with respect to the simulation state.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134391595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131554
Rana Elnaggar, Siyuan Chen, P. Song, K. Chakrabarty
Heterogeneous SoCs integrate FPGAs and microprocessor cores on the same fabric to accelerate applications such as cryptography and deep learning. Since FPGAs share resources with the microprocessor cores, they can launch non-cacheable SDRAM transactions through direct FPGA-to-microprocessor SDRAM interface. Therefore, if the FPGA 3rd party IPs (3PIPs) are malicious, they can launch rowhammer attacks on the SDRAM. Today's countermeasures based on performance counters cannot detect these attacks because memory transactions from FPGAs do not pass through the cache. In addition, countermeasures that count the frequency of activation of memory rows require structural changes to the memory controller or DRAM chips. Moreover, today's countermeasures cannot identify the IP that launches the attack. We present a security solution that monitors the SDRAM transactions from IPs on the FPGA to each bank of the microprocessor SDRAM through the FPGA-to-microprocessor SDRAM interface. The proposed monitor is implemented on the FPGA fabric. It can detect attempts to launch a rowhammer attack before it causes bit flips in the SDRAM. It utilizes only 1% of the adaptive logic modules (ALMs) available in an Intel Cyclone V FPGA to monitor the transactions from one IP.
异构soc将fpga和微处理器内核集成在同一结构上，以加速密码学和深度学习等应用。由于fpga与微处理器内核共享资源，它们可以通过直接fpga到微处理器的SDRAM接口启动不可缓存的SDRAM事务。因此，如果FPGA第三方ip (3pip)是恶意的，他们可以对SDRAM发起rowhammer攻击。目前基于性能计数器的对策无法检测到这些攻击，因为来自fpga的内存事务不通过缓存。此外，计算存储器行激活频率的对策需要对存储器控制器或DRAM芯片进行结构更改。此外，今天的对策无法识别发起攻击的IP。我们提出了一种安全解决方案，通过FPGA到微处理器SDRAM接口监控从FPGA上的ip到微处理器SDRAM的每组SDRAM事务。提出的监视器是在FPGA结构上实现的。它可以在引起SDRAM中的位翻转之前检测到发起打滑锤攻击的企图。它仅利用英特尔Cyclone V FPGA中可用的1%的自适应逻辑模块(alm)来监视来自一个IP的事务。
{"title":"Detection of Rowhammer Attacks in SoCs with FPGAs","authors":"Rana Elnaggar, Siyuan Chen, P. Song, K. Chakrabarty","doi":"10.1109/ETS48528.2020.9131554","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131554","url":null,"abstract":"Heterogeneous SoCs integrate FPGAs and microprocessor cores on the same fabric to accelerate applications such as cryptography and deep learning. Since FPGAs share resources with the microprocessor cores, they can launch non-cacheable SDRAM transactions through direct FPGA-to-microprocessor SDRAM interface. Therefore, if the FPGA 3rd party IPs (3PIPs) are malicious, they can launch rowhammer attacks on the SDRAM. Today's countermeasures based on performance counters cannot detect these attacks because memory transactions from FPGAs do not pass through the cache. In addition, countermeasures that count the frequency of activation of memory rows require structural changes to the memory controller or DRAM chips. Moreover, today's countermeasures cannot identify the IP that launches the attack. We present a security solution that monitors the SDRAM transactions from IPs on the FPGA to each bank of the microprocessor SDRAM through the FPGA-to-microprocessor SDRAM interface. The proposed monitor is implemented on the FPGA fabric. It can detect attempts to launch a rowhammer attack before it causes bit flips in the SDRAM. It utilizes only 1% of the adaptive logic modules (ALMs) available in an Intel Cyclone V FPGA to monitor the transactions from one IP.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133517399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1109/ETS48528.2020.9131576
Rezgar Sadeghi, Z. Navabi
In very deep sub-micrometer technology nodes, signal integrity of interconnects has been drastically jeopardized by crosstalk noise. To make a communication link reliable against crosstalk faults, different detection, correction, and avoidance methods have been proposed at the cost of redundant spatial and information overheads. In this paper, we propose a crosstalk prediction hardware based on an abstract model deduced from low-level interconnect evaluation for new technologies. This predictor monitors the data pattern to be sent through a communication bus and predicts those likely subjected to the crosstalk fault. Thus, to prevent crosstalk faults, the predictor dynamically engages an avoidance or detection mechanism. Top-level buses are the target of the proposed method. Simulation results reveal that the proposed communication channel is more efficient in terms of crosstalk alleviation as well as area and performance overhead compared to the state of the art reliability methods.
{"title":"Built-In Predictors for Dynamic Crosstalk Avoidance","authors":"Rezgar Sadeghi, Z. Navabi","doi":"10.1109/ETS48528.2020.9131576","DOIUrl":"https://doi.org/10.1109/ETS48528.2020.9131576","url":null,"abstract":"In very deep sub-micrometer technology nodes, signal integrity of interconnects has been drastically jeopardized by crosstalk noise. To make a communication link reliable against crosstalk faults, different detection, correction, and avoidance methods have been proposed at the cost of redundant spatial and information overheads. In this paper, we propose a crosstalk prediction hardware based on an abstract model deduced from low-level interconnect evaluation for new technologies. This predictor monitors the data pattern to be sent through a communication bus and predicts those likely subjected to the crosstalk fault. Thus, to prevent crosstalk faults, the predictor dynamically engages an avoidance or detection mechanism. Top-level buses are the target of the proposed method. Simulation results reveal that the proposed communication channel is more efficient in terms of crosstalk alleviation as well as area and performance overhead compared to the state of the art reliability methods.","PeriodicalId":267309,"journal":{"name":"2020 IEEE European Test Symposium (ETS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123658768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：