Pub Date : 2013-10-01DOI: 10.1109/SIITME.2013.6743640
Andreea Bozesan, Flavius Opritoiu, M. Vladutiu
This paper introduces a novel hardware implementation of the IDEA NXT encryption algorithm resistant to attacks, and proposes a strategy for testing the implementation on an Altera DE2 FPGA. The proposed design is analysed with respect to execution time and throughput, revealing its effectiveness in comparison to conventional approaches. Also, its performance in terms of execution time and throughput is presented by comparison to the DES, IDEA and AES cryptographic algorithms, which have been extensively used in the past few decades, and also to other implementations of the NXT algorithm previously developed. The IDEA NXT crypto-algorithm surfaced only a few years ago and little work was done so far to prove its theoretical strengths or to bring improvements, and that is what this study tries to cover.
{"title":"Hardware implementation of the IDEA NXT crypto-algorithm","authors":"Andreea Bozesan, Flavius Opritoiu, M. Vladutiu","doi":"10.1109/SIITME.2013.6743640","DOIUrl":"https://doi.org/10.1109/SIITME.2013.6743640","url":null,"abstract":"This paper introduces a novel hardware implementation of the IDEA NXT encryption algorithm resistant to attacks, and proposes a strategy for testing the implementation on an Altera DE2 FPGA. The proposed design is analysed with respect to execution time and throughput, revealing its effectiveness in comparison to conventional approaches. Also, its performance in terms of execution time and throughput is presented by comparison to the DES, IDEA and AES cryptographic algorithms, which have been extensively used in the past few decades, and also to other implementations of the NXT algorithm previously developed. The IDEA NXT crypto-algorithm surfaced only a few years ago and little work was done so far to prove its theoretical strengths or to bring improvements, and that is what this study tries to cover.","PeriodicalId":267846,"journal":{"name":"2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126876052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/SIITME.2013.6743676
M. Nicolae, L. Lucaci, I. Moise
The paper presents a novel architecture based on frequent utilization of PDAs and mobile phones as human machine interface (HMI) in controlling various systems. There are two main considerations discussed. One is with regards to real-time constraints in the context of industrial process control. The second is the possibility of transferring some tasks from the process controller towards the Android device (tablet or smart phone). Therefore, after analyzing the current implementations together with their limitations, we designed an evaluation framework. The main goal of the new structure will be to analyze the limitations of balancing processing load between process controller and Android device's resources. The structure is comprised of a cheap Android tablet connected to an embedded module via an USB cable. The embedded module has as his core a state-of-art ARM Cortex M4F processor for industrial applications. The proposed solution provides the advantages derived from both components. The implementation required driver development, considerations which are also presented briefly.
{"title":"Embedding Android devices in automation systems","authors":"M. Nicolae, L. Lucaci, I. Moise","doi":"10.1109/SIITME.2013.6743676","DOIUrl":"https://doi.org/10.1109/SIITME.2013.6743676","url":null,"abstract":"The paper presents a novel architecture based on frequent utilization of PDAs and mobile phones as human machine interface (HMI) in controlling various systems. There are two main considerations discussed. One is with regards to real-time constraints in the context of industrial process control. The second is the possibility of transferring some tasks from the process controller towards the Android device (tablet or smart phone). Therefore, after analyzing the current implementations together with their limitations, we designed an evaluation framework. The main goal of the new structure will be to analyze the limitations of balancing processing load between process controller and Android device's resources. The structure is comprised of a cheap Android tablet connected to an embedded module via an USB cable. The embedded module has as his core a state-of-art ARM Cortex M4F processor for industrial applications. The proposed solution provides the advantages derived from both components. The implementation required driver development, considerations which are also presented briefly.","PeriodicalId":267846,"journal":{"name":"2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116939356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/SIITME.2013.6743639
A. Bonyár, Balazs Wimmer, I. Csarnovics
Gold nanoparticles (Au NPs) were generated by thermally annealing gold thin films (5-30 nm) which were sputtered on glass substrates. The conditions of the thermal annealing (temperature and annealing time) were varied in order to generate nanoparticles in different sizes. The size and distribution of the nanoparticles were characterized by atomic force microscopy (AFM). The Au NP modified surface is intended to be used as sensor transducer element in a surface plasmon resonance imaging (SPRi) instrument. Thus we investigated the size of the generated NPs in function of the annealing parameters in order to reach optimal conditions for the NP signal amplification in the SPRi device.
{"title":"Investigation of thermally generated gold nanoparticles with AFM","authors":"A. Bonyár, Balazs Wimmer, I. Csarnovics","doi":"10.1109/SIITME.2013.6743639","DOIUrl":"https://doi.org/10.1109/SIITME.2013.6743639","url":null,"abstract":"Gold nanoparticles (Au NPs) were generated by thermally annealing gold thin films (5-30 nm) which were sputtered on glass substrates. The conditions of the thermal annealing (temperature and annealing time) were varied in order to generate nanoparticles in different sizes. The size and distribution of the nanoparticles were characterized by atomic force microscopy (AFM). The Au NP modified surface is intended to be used as sensor transducer element in a surface plasmon resonance imaging (SPRi) instrument. Thus we investigated the size of the generated NPs in function of the annealing parameters in order to reach optimal conditions for the NP signal amplification in the SPRi device.","PeriodicalId":267846,"journal":{"name":"2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128127393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/SIITME.2013.6743646
B. Illés
This paper presents a modeling approach of the Galden layer formation on the surface of Printed Circuit Boards (PCBs) during the Vapour Phase Soldering (VPS) process. The layer formation model is a supplement of a board level condensation model which calculates the condensate mass on the surface of the soldered PCB. The Galden layer formation model applies combined transport mechanisms including convective mass transport by the hydrostatic pressure difference in the layer and the gravity force; conductive and convective heat transport. The model applies the Finite Difference Method (FDM) and the three dimensional Forward Time Central Space (FTCS) method. The model can describe the dynamic formation and change of the Galden layer on the PCB surface and the change of the mass and energy flow in the condensate layer. This way the effect of the Galden layer changes on the heating of the soldered PCB can be investigated.
{"title":"Modeling Galden layer formation on PCB surface during Vapour Phase Soldering","authors":"B. Illés","doi":"10.1109/SIITME.2013.6743646","DOIUrl":"https://doi.org/10.1109/SIITME.2013.6743646","url":null,"abstract":"This paper presents a modeling approach of the Galden layer formation on the surface of Printed Circuit Boards (PCBs) during the Vapour Phase Soldering (VPS) process. The layer formation model is a supplement of a board level condensation model which calculates the condensate mass on the surface of the soldered PCB. The Galden layer formation model applies combined transport mechanisms including convective mass transport by the hydrostatic pressure difference in the layer and the gravity force; conductive and convective heat transport. The model applies the Finite Difference Method (FDM) and the three dimensional Forward Time Central Space (FTCS) method. The model can describe the dynamic formation and change of the Galden layer on the PCB surface and the change of the mass and energy flow in the condensate layer. This way the effect of the Galden layer changes on the heating of the soldered PCB can be investigated.","PeriodicalId":267846,"journal":{"name":"2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131773681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/SIITME.2013.6743675
C. Lung, A. Buchman
This paper presents an innovative implementation of a radio communication system, which is able to transmit analog and digital data. The main goal of this project is to implement a multiprocessor system, based on the FPGA technology, which can control multiple radio transceivers. In this configuration allow a various possibilities of communication: analogue (voice) communication and data transmission at different baud rates and frequency.
{"title":"Multifunctional communication system controller implemented in FPGA","authors":"C. Lung, A. Buchman","doi":"10.1109/SIITME.2013.6743675","DOIUrl":"https://doi.org/10.1109/SIITME.2013.6743675","url":null,"abstract":"This paper presents an innovative implementation of a radio communication system, which is able to transmit analog and digital data. The main goal of this project is to implement a multiprocessor system, based on the FPGA technology, which can control multiple radio transceivers. In this configuration allow a various possibilities of communication: analogue (voice) communication and data transmission at different baud rates and frequency.","PeriodicalId":267846,"journal":{"name":"2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128546940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/SIITME.2013.6743691
I. Plotog, G. Vărzaru, B. Mihailescu, M. Branzei, A. Bibiș, I. Cristea
The domains exempted by the RoHS EU Directive, as aerospace, where Sn63Pb37 eutectic solder alloy with low silver content addition are used, are characterized by a large range of working temperatures and high mechanical stress level. In the paper, the mechanical strength of solder joints produced using Lead and Lead-Free solder pastes into Vapor Phase Soldering processes characterized by different cooling rates, were benchmarked by temperature in respect to the concept of "Homologous temperature". The experiments were done by measuring the solder joints shear forces and keeping the surface of test boards at temperatures up to 398.15 K (125°C). The experiments results consist in qualitative/quantitative light microscopy analyses and values of solder joints shear forces. The results offer the possibility to create a data base useful to define a methodology for future qualification of lead-free solder alloys according to the RoHS EU Directive.
{"title":"Lead/Lead Free solder joints comparative shear tests function of working temperature and soldering thermal profile","authors":"I. Plotog, G. Vărzaru, B. Mihailescu, M. Branzei, A. Bibiș, I. Cristea","doi":"10.1109/SIITME.2013.6743691","DOIUrl":"https://doi.org/10.1109/SIITME.2013.6743691","url":null,"abstract":"The domains exempted by the RoHS EU Directive, as aerospace, where Sn63Pb37 eutectic solder alloy with low silver content addition are used, are characterized by a large range of working temperatures and high mechanical stress level. In the paper, the mechanical strength of solder joints produced using Lead and Lead-Free solder pastes into Vapor Phase Soldering processes characterized by different cooling rates, were benchmarked by temperature in respect to the concept of \"Homologous temperature\". The experiments were done by measuring the solder joints shear forces and keeping the surface of test boards at temperatures up to 398.15 K (125°C). The experiments results consist in qualitative/quantitative light microscopy analyses and values of solder joints shear forces. The results offer the possibility to create a data base useful to define a methodology for future qualification of lead-free solder alloys according to the RoHS EU Directive.","PeriodicalId":267846,"journal":{"name":"2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"10 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115183576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/SIITME.2013.6743651
S. Epure, R. Belea, L. Frangu
The research carried on in the field of dielectric nanomaterials requires a large amount of fast and accurate measurements, such as the current/voltage characteristics, which produce currents under the 1nA range. The size of the available devices forces them to be placed outside the measurement setup, allowing a large influence of the electric noise. Supplementary, they are unable to measure during the transient phenomena and expensive (“sourcemeters” available from different producers). This paper presents a more convenient solution (under 500 euros) for fast automatically measuring the characteristics in the range of 10pA to 1000nA. A major advantage of this device is its size (10×6×10cm), allowing it to fit into the shielding enclosure, together with the probe, needle manipulator and microscope. It allows the experimenter to specify the voltage range and the number of measuring points and it automatically provides the resulting data file, without raising neither the uncertainty level (under 10pA), nor the measuring time (down to 0.1 seconds per measuring point). The error is kept low through active guarding, mains synchronization, careful shielding and the use of extremely low bias amplifiers (3fA). The device communicates with the host computer via the galvanic isolated USB interface and does not require separate power supply (USB powered).
{"title":"Low-cost picoammeter for dielectrics","authors":"S. Epure, R. Belea, L. Frangu","doi":"10.1109/SIITME.2013.6743651","DOIUrl":"https://doi.org/10.1109/SIITME.2013.6743651","url":null,"abstract":"The research carried on in the field of dielectric nanomaterials requires a large amount of fast and accurate measurements, such as the current/voltage characteristics, which produce currents under the 1nA range. The size of the available devices forces them to be placed outside the measurement setup, allowing a large influence of the electric noise. Supplementary, they are unable to measure during the transient phenomena and expensive (“sourcemeters” available from different producers). This paper presents a more convenient solution (under 500 euros) for fast automatically measuring the characteristics in the range of 10pA to 1000nA. A major advantage of this device is its size (10×6×10cm), allowing it to fit into the shielding enclosure, together with the probe, needle manipulator and microscope. It allows the experimenter to specify the voltage range and the number of measuring points and it automatically provides the resulting data file, without raising neither the uncertainty level (under 10pA), nor the measuring time (down to 0.1 seconds per measuring point). The error is kept low through active guarding, mains synchronization, careful shielding and the use of extremely low bias amplifiers (3fA). The device communicates with the host computer via the galvanic isolated USB interface and does not require separate power supply (USB powered).","PeriodicalId":267846,"journal":{"name":"2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115600352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/SIITME.2013.6743644
R. Bátorfi, Richard Storcz, M. Ruszinkó
A solution for applying through hole (TH) components in mixed assembly is the pin-in-paste (PIP) technology, when solder paste is deposited onto the plated through holes and the components are placed into the holes through the paste. An important factor in defining the quality of TH soldering is the hole filling, which strongly relies on the capillary force. In our experiments, our aim was to define an optimal paste amount for rectangular and circular pins, for different diameter plated through holes, using two types of SAC solder paste, reflow soldered by vapour phase technology.
{"title":"Investigating hole filling in pin-in-paste technology for vapour phase soldering","authors":"R. Bátorfi, Richard Storcz, M. Ruszinkó","doi":"10.1109/SIITME.2013.6743644","DOIUrl":"https://doi.org/10.1109/SIITME.2013.6743644","url":null,"abstract":"A solution for applying through hole (TH) components in mixed assembly is the pin-in-paste (PIP) technology, when solder paste is deposited onto the plated through holes and the components are placed into the holes through the paste. An important factor in defining the quality of TH soldering is the hole filling, which strongly relies on the capillary force. In our experiments, our aim was to define an optimal paste amount for rectangular and circular pins, for different diameter plated through holes, using two types of SAC solder paste, reflow soldered by vapour phase technology.","PeriodicalId":267846,"journal":{"name":"2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126953585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/SIITME.2013.6743681
A. Taut, O. Pop, A. Grama, C. Farcas
This paper presents a study and the design with the technical aspects of implementing electronic ballast used for lighting and keeping the power of a lamp while restricting and controlling the input current during its activity. The electronic ballast circuit proposed is based on two power converters, like a boost converter with power factor correction (PFC) and an a half bridge converter with resonant circuit in order to turn on one or more lamps. Taking into account the practical and technological constraints, the necessary frequency converter must be based on a DC voltage source, a capacitive divider and a series-resonant single-phase power inverter (half-bridge converter). The need for a boost converter is explained by the fact that the half bridge converter feeds with DC voltage and the presence of a simple rectifier would not solve the problems caused by distortions on the supply network. The result obtained validates the operation of the circuit and the paper presents the waveforms for output voltage and current and the total harmonic distortion and power factor correction on input AC voltage.
{"title":"Electronic ballast in half-bridge configuration with power factor correction","authors":"A. Taut, O. Pop, A. Grama, C. Farcas","doi":"10.1109/SIITME.2013.6743681","DOIUrl":"https://doi.org/10.1109/SIITME.2013.6743681","url":null,"abstract":"This paper presents a study and the design with the technical aspects of implementing electronic ballast used for lighting and keeping the power of a lamp while restricting and controlling the input current during its activity. The electronic ballast circuit proposed is based on two power converters, like a boost converter with power factor correction (PFC) and an a half bridge converter with resonant circuit in order to turn on one or more lamps. Taking into account the practical and technological constraints, the necessary frequency converter must be based on a DC voltage source, a capacitive divider and a series-resonant single-phase power inverter (half-bridge converter). The need for a boost converter is explained by the fact that the half bridge converter feeds with DC voltage and the presence of a simple rectifier would not solve the problems caused by distortions on the supply network. The result obtained validates the operation of the circuit and the paper presents the waveforms for output voltage and current and the total harmonic distortion and power factor correction on input AC voltage.","PeriodicalId":267846,"journal":{"name":"2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126517443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/SIITME.2013.6743638
D. Bonfert, D. Hemmetzberger, G. Klink, K. Bock, P. Svasta, C. Ionescu
Carbon nanotubes (CNT) have remarkable electrical, mechanical, thermal and optical properties. CNT-polymer composites are therefore alternative materials for applications, like flexible electrodes in displays, electronic paper, antistatic coatings. But these materials can also be used as sensors, due to their special properties. The paper describes the behavior of CNT-based thick film layers on foils due to electrical, thermal, optical, and mechanical stimuli. Possible applications as sensor materials are further described.
{"title":"Sensing properties of carbon nanotube based thick film layers on foils","authors":"D. Bonfert, D. Hemmetzberger, G. Klink, K. Bock, P. Svasta, C. Ionescu","doi":"10.1109/SIITME.2013.6743638","DOIUrl":"https://doi.org/10.1109/SIITME.2013.6743638","url":null,"abstract":"Carbon nanotubes (CNT) have remarkable electrical, mechanical, thermal and optical properties. CNT-polymer composites are therefore alternative materials for applications, like flexible electrodes in displays, electronic paper, antistatic coatings. But these materials can also be used as sensors, due to their special properties. The paper describes the behavior of CNT-based thick film layers on foils due to electrical, thermal, optical, and mechanical stimuli. Possible applications as sensor materials are further described.","PeriodicalId":267846,"journal":{"name":"2013 IEEE 19th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131402276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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