Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062469
S. Muthukrishnan, C. Hale, N. Peachey
The article presents a novel method of protecting RF ports designed to handle high (>30dBm) power levels. An Enhancement mode (E-mode) pHEMT clamp consists of Field effect transistor (FET) with a resistor connected between gate and source. Our design consists of two such clamps connected in back to back configuration. The structure was connected to the Transmit (TX) port of a WiFi front end module (WiFi FEM). Transmission line pulsing (TLP) and Human Body Model (HBM) testing was used to characterize the clamp. The low capacitance (<100fF) along with high trigger voltage (±21V) makes this clamp a suitable candidate for protecting high power RF ports.
{"title":"A Novel Clamp Based ESD Protection Structure for High Power RF Ports in GaAs pHEMT Process","authors":"S. Muthukrishnan, C. Hale, N. Peachey","doi":"10.1109/CSICS.2011.6062469","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062469","url":null,"abstract":"The article presents a novel method of protecting RF ports designed to handle high (>30dBm) power levels. An Enhancement mode (E-mode) pHEMT clamp consists of Field effect transistor (FET) with a resistor connected between gate and source. Our design consists of two such clamps connected in back to back configuration. The structure was connected to the Transmit (TX) port of a WiFi front end module (WiFi FEM). Transmission line pulsing (TLP) and Human Body Model (HBM) testing was used to characterize the clamp. The low capacitance (<100fF) along with high trigger voltage (±21V) makes this clamp a suitable candidate for protecting high power RF ports.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116798890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062476
M. Gavell, M. Ferndahl, S. Gunnarsson, H. Zirath
This paper presents the design and characterization of a multifunctional receiver with integrated ×4 frequency multiplier for the LO generation, image reject mixer and low noise amplifier into a single chip MMIC. Noise figure has been measured to 4.6 dB and power consumption to 140 mW. The image rejection is better than 47 dB, conversion gain 10 dB and IIP3 -12 dBm. This performance is far superior to any comparable existing published 53 GHz receiver. The process used is commercially available 0.15 µm GaAs mHEMT technology featuring ft=120 GHz and fmax=200 GHz.
{"title":"A 53 GHz Single Chip Receiver for Geostationary Atmospheric Measurements","authors":"M. Gavell, M. Ferndahl, S. Gunnarsson, H. Zirath","doi":"10.1109/CSICS.2011.6062476","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062476","url":null,"abstract":"This paper presents the design and characterization of a multifunctional receiver with integrated ×4 frequency multiplier for the LO generation, image reject mixer and low noise amplifier into a single chip MMIC. Noise figure has been measured to 4.6 dB and power consumption to 140 mW. The image rejection is better than 47 dB, conversion gain 10 dB and IIP3 -12 dBm. This performance is far superior to any comparable existing published 53 GHz receiver. The process used is commercially available 0.15 µm GaAs mHEMT technology featuring ft=120 GHz and fmax=200 GHz.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127352537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062462
M. Briere
Focusing on the application range between 20 and 1200 V, a survey is presented of the power electronic marketplace including the principle power device structures and IC technologies as well as circuit topologies used in the major applications. The relation between power device performance and system level capabilities are discussed. Recent results obtained using the commercial GaN- on-Si based HEMT development platform at International Rectifier, known as GaNpowIR®, will be presented.
{"title":"The Power Electronics Market and the Status of GaN Based Power Devices","authors":"M. Briere","doi":"10.1109/CSICS.2011.6062462","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062462","url":null,"abstract":"Focusing on the application range between 20 and 1200 V, a survey is presented of the power electronic marketplace including the principle power device structures and IC technologies as well as circuit topologies used in the major applications. The relation between power device performance and system level capabilities are discussed. Recent results obtained using the commercial GaN- on-Si based HEMT development platform at International Rectifier, known as GaNpowIR®, will be presented.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122275968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062471
V. Kaushal, M. Margala, I. Íñiguez-de-la-Torre, T. González, J. Mateos
In this paper, the utilization of recently proposed ballistic deflection transistors (BDT) is investigated for the realization of the complete family of logic functions. BDT performance is optimized through its structural modification which is followed by the Monte Carlo simulations for 2- input logic gate functionalities at room temperature. BDT is a quasi-ballistic planar device based on InGaAs/InAlAs/InP heterolayer. The faster non-scattering transport obtained in the two dimensional electron gas (2DEG) layer facilitates smaller transit time and high performance needed for high speed circuitry.
{"title":"Realization of Logic Operations Through Optimized Ballistic Deflection Transistors","authors":"V. Kaushal, M. Margala, I. Íñiguez-de-la-Torre, T. González, J. Mateos","doi":"10.1109/CSICS.2011.6062471","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062471","url":null,"abstract":"In this paper, the utilization of recently proposed ballistic deflection transistors (BDT) is investigated for the realization of the complete family of logic functions. BDT performance is optimized through its structural modification which is followed by the Monte Carlo simulations for 2- input logic gate functionalities at room temperature. BDT is a quasi-ballistic planar device based on InGaAs/InAlAs/InP heterolayer. The faster non-scattering transport obtained in the two dimensional electron gas (2DEG) layer facilitates smaller transit time and high performance needed for high speed circuitry.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116256998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062461
B. Lu, T. Palacios, D. Risbud, S. Bahl, David I. Anderson
In this paper we present a new measurement technique for extracting dynamic on-resistance (Rdson) of GaN transistors. Dynamic Rdson of commercial GaN transistors in soft-switching and hard-switching conditions have been measured. By comparing the dynamic Rdson in both switching schemes, it is found that the off-state drain voltage stress is the main cause for the increase of dynamic Rdson, while the switching losses in the hard-switching transient could cause additional trapping and degradation, possibly due to channel hot electrons/phonons.
{"title":"Extraction of Dynamic On-Resistance in GaN Transistors: Under Soft- and Hard-Switching Conditions","authors":"B. Lu, T. Palacios, D. Risbud, S. Bahl, David I. Anderson","doi":"10.1109/CSICS.2011.6062461","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062461","url":null,"abstract":"In this paper we present a new measurement technique for extracting dynamic on-resistance (Rdson) of GaN transistors. Dynamic Rdson of commercial GaN transistors in soft-switching and hard-switching conditions have been measured. By comparing the dynamic Rdson in both switching schemes, it is found that the off-state drain voltage stress is the main cause for the increase of dynamic Rdson, while the switching losses in the hard-switching transient could cause additional trapping and degradation, possibly due to channel hot electrons/phonons.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131488321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062439
J. Godin, A. Konczykowska, J. Dupuy, F. Jorge, A. Gnauck, M. Riet, J. Moulu, V. Nodjiadjim, P. Berdaguer, F. Blache
This paper reports on very high speed large swing digital-to-analog converter (DAC) suiting the generation of spectrally efficient optical transmission signals. 2-bit and 3-bit DACS with up to 4 Vpp swing, operating up to 50 GBaud, have been fabricated using our InP DHBT technology (FT ~280 GHz, FMAX ~270 GHz, BVCE0 ~5 V). These chips have been packaged and used to generate 16- and 64-QAM signals in optical transmission experiments at various bitrates.
{"title":"InP DHBT Very High Speed Power-DACs for Spectrally Efficient Optical Transmission Systems","authors":"J. Godin, A. Konczykowska, J. Dupuy, F. Jorge, A. Gnauck, M. Riet, J. Moulu, V. Nodjiadjim, P. Berdaguer, F. Blache","doi":"10.1109/CSICS.2011.6062439","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062439","url":null,"abstract":"This paper reports on very high speed large swing digital-to-analog converter (DAC) suiting the generation of spectrally efficient optical transmission signals. 2-bit and 3-bit DACS with up to 4 Vpp swing, operating up to 50 GBaud, have been fabricated using our InP DHBT technology (FT ~280 GHz, FMAX ~270 GHz, BVCE0 ~5 V). These chips have been packaged and used to generate 16- and 64-QAM signals in optical transmission experiments at various bitrates.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127559083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-04DOI: 10.1109/CSICS.2011.6062443
T. Kazior, R. Chelakara, W. Hoke, J. Bettencourt, T. Palacios, H. S. Lee
In this work we present recent results on the direct heterogeneous integration of GaN HEMTs and Si CMOS on a silicon substrate. GaN HEMTs whose DC and RF performance are comparable to GaN HEMTs on SiC substrates have been achieved. As a demonstration vehicle we designed and fabricated a GaN amplifier with pMOS gate bias control circuitry (a current mirror) and heterogeneous interconnects. This simple demonstration circuit is a building block for more advanced RF, mixed signal and power conditioning circuits, such as reconfigurable or linearized PAs with in-situ adaptive bias control, high power digital-to-analog converters (DACs), driver stages for on-wafer optoelectronics, and on-chip power distribution networks.
{"title":"High Performance Mixed Signal and RF Circuits Enabled by the Direct Monolithic Heterogeneous Integration of GaN HEMTs and Si CMOS on a Silicon Substrate","authors":"T. Kazior, R. Chelakara, W. Hoke, J. Bettencourt, T. Palacios, H. S. Lee","doi":"10.1109/CSICS.2011.6062443","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062443","url":null,"abstract":"In this work we present recent results on the direct heterogeneous integration of GaN HEMTs and Si CMOS on a silicon substrate. GaN HEMTs whose DC and RF performance are comparable to GaN HEMTs on SiC substrates have been achieved. As a demonstration vehicle we designed and fabricated a GaN amplifier with pMOS gate bias control circuitry (a current mirror) and heterogeneous interconnects. This simple demonstration circuit is a building block for more advanced RF, mixed signal and power conditioning circuits, such as reconfigurable or linearized PAs with in-situ adaptive bias control, high power digital-to-analog converters (DACs), driver stages for on-wafer optoelectronics, and on-chip power distribution networks.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124060801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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