Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062477
R. Makon, R. Driad, J. Rosenzweig, V. Hurm, C. Schubert, H. Walcher, M. Schlechtweg, O. Ambacher
Key components and architecture options are being actively investigated to realize next generation transport technology in optical networks. Serial transmission systems using a single wavelength have, so far, provided cost effective solutions and therefore remain desirable. For 100 Gbit/s Ethernet, this option will, however, depend on the availability of the electronic and optical components. Due to its high speed and high breakdown voltage, the InP double-heterojunction bipolar transistor (DHBT) technology is particularly suited for signal processing and high-speed communication systems. This contribution describes our InP DHBT based integrated circuit (IC) technology developed for 100 Gbit/s class mixed-signal ICs. Using this technology, we fabricated and succeeded in 112 Gbit/s testing of key electronic components, including a multiplexer (MUX), a distributed amplifier, and an integrated clock and data recovery (CDR)/1:2 demultiplexer (DEMUX), with very clear eye waveforms. These high-speed building block ICs are described and the main results are presented.
{"title":"Ultra-High-Speed Transmitter and Receiver ICs for 100 Gbit/s Ethernet Using InP DHBTs","authors":"R. Makon, R. Driad, J. Rosenzweig, V. Hurm, C. Schubert, H. Walcher, M. Schlechtweg, O. Ambacher","doi":"10.1109/CSICS.2011.6062477","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062477","url":null,"abstract":"Key components and architecture options are being actively investigated to realize next generation transport technology in optical networks. Serial transmission systems using a single wavelength have, so far, provided cost effective solutions and therefore remain desirable. For 100 Gbit/s Ethernet, this option will, however, depend on the availability of the electronic and optical components. Due to its high speed and high breakdown voltage, the InP double-heterojunction bipolar transistor (DHBT) technology is particularly suited for signal processing and high-speed communication systems. This contribution describes our InP DHBT based integrated circuit (IC) technology developed for 100 Gbit/s class mixed-signal ICs. Using this technology, we fabricated and succeeded in 112 Gbit/s testing of key electronic components, including a multiplexer (MUX), a distributed amplifier, and an integrated clock and data recovery (CDR)/1:2 demultiplexer (DEMUX), with very clear eye waveforms. These high-speed building block ICs are described and the main results are presented.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"357 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115941033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062493
L. Liu, A. Alt, H. Benedickter, C. Bolognesi
Appropriately designed InP/GaInAs -based pHEMTs with relatively conservative indium channel mole fractions are prime contenders for high-performance low-power dissipation mm-wave MMICs. A clear and distinct advantage of InP -based HEMT technology is that it is long since space-qualified, leveraging decades of InP fabrication and reliability know-how. As a first demonstrator of low-power operation, we demonstrate an X-band low-noise amplifier (LNA) featuring a 9 dB gain and a 1.5 dB noise figure, while operating with a record ultralow 0.6 mW total power dissipation. A second demonstrator MMIC consists of a wideband amplifier delivering 10 dB of gain between 35-82 GHz, with a total power dissipation of 2.59 mW, corresponding to consumption of 8.6 µW per micron of total amplifier gate periphery (or 57% of the lowest power density ever achieved with ABCS HEMTs). Clearly, given consideration to the still conservative x = 68% channel indium mole fraction, much room remains for the ultimate optimization of InP/GaInAs -based conventional HEMTs for low-power dissipation MMICs covering the application spectrum from X- to W- bands.
{"title":"InP/GaInAs pHEMT Ultralow-Power Consumption MMICs","authors":"L. Liu, A. Alt, H. Benedickter, C. Bolognesi","doi":"10.1109/CSICS.2011.6062493","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062493","url":null,"abstract":"Appropriately designed InP/GaInAs -based pHEMTs with relatively conservative indium channel mole fractions are prime contenders for high-performance low-power dissipation mm-wave MMICs. A clear and distinct advantage of InP -based HEMT technology is that it is long since space-qualified, leveraging decades of InP fabrication and reliability know-how. As a first demonstrator of low-power operation, we demonstrate an X-band low-noise amplifier (LNA) featuring a 9 dB gain and a 1.5 dB noise figure, while operating with a record ultralow 0.6 mW total power dissipation. A second demonstrator MMIC consists of a wideband amplifier delivering 10 dB of gain between 35-82 GHz, with a total power dissipation of 2.59 mW, corresponding to consumption of 8.6 µW per micron of total amplifier gate periphery (or 57% of the lowest power density ever achieved with ABCS HEMTs). Clearly, given consideration to the still conservative x = 68% channel indium mole fraction, much room remains for the ultimate optimization of InP/GaInAs -based conventional HEMTs for low-power dissipation MMICs covering the application spectrum from X- to W- bands.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124966319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062486
A. Khalil, E. Oran, C. Hay, M. Koechlin
This paper describes the design and implementation of a new class of fully integrated oscillators in standard MMIC technology. Each oscillator comprises of a rectangular waveguide cavity resonator, a loop amplifier, and a phase shifter. Several cavities are constructed on standards GaAs substrate with quality factors of 120-170 between 40-50 GHz. The phase noise of a 52 GHz MMIC oscillator is -122 dBc/Hz at 1MHz offset.
{"title":"MMIC Cavity Oscillators","authors":"A. Khalil, E. Oran, C. Hay, M. Koechlin","doi":"10.1109/CSICS.2011.6062486","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062486","url":null,"abstract":"This paper describes the design and implementation of a new class of fully integrated oscillators in standard MMIC technology. Each oscillator comprises of a rectangular waveguide cavity resonator, a loop amplifier, and a phase shifter. Several cavities are constructed on standards GaAs substrate with quality factors of 120-170 between 40-50 GHz. The phase noise of a 52 GHz MMIC oscillator is -122 dBc/Hz at 1MHz offset.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125011145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062433
P. Page, C. Steinbeiser, T. Landon, G. Burgin, R. Hajji, R. Branson, O. Krutko, J. Delaney, L. Witkowski
A two stage high power amplifier consisting of a 325W High Voltage HBT (HVHBT) Doherty final and a 20W LDMOS Doherty driver has been developed for use in wireless basestation applications. The lineup achieved greater than 54% PAE at 75W (48.77dBm) average output power with 30dB gain while achieving -55dBc linearized ACPR at 5MHz offset using a 2C11 WCDMA input signal with 6.5dB PAR signal. The DPD friendly characteristics of the HVHBT Doherty final enable use of a non-linear Doherty driver while maintaining the same ease of correction for the overall lineup.
{"title":"325W HVHBT Doherty Final and LDMOS Doherty Driver with 30dB Gain and 54% PAE Linearized to -55dBc for 2c11 6.5dB PAR","authors":"P. Page, C. Steinbeiser, T. Landon, G. Burgin, R. Hajji, R. Branson, O. Krutko, J. Delaney, L. Witkowski","doi":"10.1109/CSICS.2011.6062433","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062433","url":null,"abstract":"A two stage high power amplifier consisting of a 325W High Voltage HBT (HVHBT) Doherty final and a 20W LDMOS Doherty driver has been developed for use in wireless basestation applications. The lineup achieved greater than 54% PAE at 75W (48.77dBm) average output power with 30dB gain while achieving -55dBc linearized ACPR at 5MHz offset using a 2C11 WCDMA input signal with 6.5dB PAR signal. The DPD friendly characteristics of the HVHBT Doherty final enable use of a non-linear Doherty driver while maintaining the same ease of correction for the overall lineup.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126959251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062488
O. Inac, Donghyup Shin, Gabriel M. Rebeiz
An X-band phased-array RF integrated circuit with built-in self-test (BIST) capabilities is presented. The BIST is accomplished using a miniature capacitive coupler at the input of each channel and an on-chip I/Q vector receiver. Measurements done with BIST system agree well with S-parameter data and provide the amplitude and phase response over phase states and over frequency. To our knowledge, this is the first implementation of an on-chip BIST and with high accuracy.
{"title":"A Phased Array RFIC with Built-In Self-Test Using an Integrated Vector Signal Analyzer","authors":"O. Inac, Donghyup Shin, Gabriel M. Rebeiz","doi":"10.1109/CSICS.2011.6062488","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062488","url":null,"abstract":"An X-band phased-array RF integrated circuit with built-in self-test (BIST) capabilities is presented. The BIST is accomplished using a miniature capacitive coupler at the input of each channel and an on-chip I/Q vector receiver. Measurements done with BIST system agree well with S-parameter data and provide the amplitude and phase response over phase states and over frequency. To our knowledge, this is the first implementation of an on-chip BIST and with high accuracy.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127077845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062479
M. Nagatani, H. Nosaka, K. Sano, K. Murata, K. Kurishima, M. Ida
This paper presents a 60-GS/s 6-bit digital-to-analog converter (DAC) for beyond-100-Gb/s/ch optical communications systems. The DAC was designed and fabricated using our in-house 0.5-im InP HBT technology, which yields a peak ft of 290 GHz, a peak fmax of 320 GHz, and a BVCEO of approximately 4 V. We used a simple R-2R ladder-based current-steering architecture to achieve both high-speed and low-power operation, and a timing alignment technique to suppress glitch noise and improve dynamic linearity. The DAC can provide clear multilevel signals for quadrature amplitude modulation (QAM) transmission at a sampling rate of up to 60 GS/s (60 Gbaud). To our knowledge, our DAC offers the highest sampling rate of any previously reported DAC, and it can be applied to 400-Gb/s/ch-class optical communications systems.
{"title":"A 60-GS/s 6-Bit DAC in 0.5-µm InP HBT Technology for Optical Communications Systems","authors":"M. Nagatani, H. Nosaka, K. Sano, K. Murata, K. Kurishima, M. Ida","doi":"10.1109/CSICS.2011.6062479","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062479","url":null,"abstract":"This paper presents a 60-GS/s 6-bit digital-to-analog converter (DAC) for beyond-100-Gb/s/ch optical communications systems. The DAC was designed and fabricated using our in-house 0.5-im InP HBT technology, which yields a peak ft of 290 GHz, a peak fmax of 320 GHz, and a BVCEO of approximately 4 V. We used a simple R-2R ladder-based current-steering architecture to achieve both high-speed and low-power operation, and a timing alignment technique to suppress glitch noise and improve dynamic linearity. The DAC can provide clear multilevel signals for quadrature amplitude modulation (QAM) transmission at a sampling rate of up to 60 GS/s (60 Gbaud). To our knowledge, our DAC offers the highest sampling rate of any previously reported DAC, and it can be applied to 400-Gb/s/ch-class optical communications systems.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129534557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062460
B. Hughes, Y. Yoon, D. Zehnder, K. Boutros
A 2:1 351 V hard-switched boost converter was constructed using high-voltage GaN high-electron-mobility transistors grown on Si substrates and GaN Schottky diodes grown on Sapphire substrates. The high speed and low on-resistance of the GaN devices enables extremely fast switching times and low losses, resulting in a high conversion efficiency of 95% with 425-W output power at 1 MHz. The boost converter has a power density of 175 W/in3. To our knowledge, these results are the best reported on GaN devices, and the highest for 1MHz switching.
{"title":"A 95% Efficient Normally-Off GaN-on-Si HEMT Hybrid-IC Boost-Converter with 425-W Output Power at 1 MHz","authors":"B. Hughes, Y. Yoon, D. Zehnder, K. Boutros","doi":"10.1109/CSICS.2011.6062460","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062460","url":null,"abstract":"A 2:1 351 V hard-switched boost converter was constructed using high-voltage GaN high-electron-mobility transistors grown on Si substrates and GaN Schottky diodes grown on Sapphire substrates. The high speed and low on-resistance of the GaN devices enables extremely fast switching times and low losses, resulting in a high conversion efficiency of 95% with 425-W output power at 1 MHz. The boost converter has a power density of 175 W/in3. To our knowledge, these results are the best reported on GaN devices, and the highest for 1MHz switching.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122662449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062481
K. Kobayashi
This paper describes a compact GaN MMIC cascode feedback amplifier design which achieves up to 8-Watts of power and IP3 greater than +51 dBm across a decade of BW. The design is made of 0.25um GaN HEMT technology with fT~50 GHz and BVgd > 60V. A 40V-750mA high-bias design achieves an OIP3 of 51.9 dBm, P1dB of 38.5 dBm, and NF ~ 3dB at 2 GHz. A 40V-500mA medium-bias design achieves a lower NF ~ 2.5 dB, an OIP3 of 48.4 dBm and a P1dB of 36.8 dBm. This combination of high linear IP3 and low NF exceeds that achieved by many state-of-the-art PHEMT, HBT and HFET technologies for decade-BW MMIC amplifiers operating in the S- and C-band frequency regime. The cascode approach is used to distribute voltage and self-heating in order to lower the Tj and NF while providing high linearity by operating from a higher supply voltage. These results suggest promise for next generation CATV, FTTX, software defined radio and BTS applications which demand higher linearity and BW to satisfy the high data throughput systems of the future.
{"title":"An 8-Watt 250-3000 MHz Low Noise GaN MMIC Feedback Amplifier with > +50 dBm OIP3","authors":"K. Kobayashi","doi":"10.1109/CSICS.2011.6062481","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062481","url":null,"abstract":"This paper describes a compact GaN MMIC cascode feedback amplifier design which achieves up to 8-Watts of power and IP3 greater than +51 dBm across a decade of BW. The design is made of 0.25um GaN HEMT technology with fT~50 GHz and BVgd > 60V. A 40V-750mA high-bias design achieves an OIP3 of 51.9 dBm, P1dB of 38.5 dBm, and NF ~ 3dB at 2 GHz. A 40V-500mA medium-bias design achieves a lower NF ~ 2.5 dB, an OIP3 of 48.4 dBm and a P1dB of 36.8 dBm. This combination of high linear IP3 and low NF exceeds that achieved by many state-of-the-art PHEMT, HBT and HFET technologies for decade-BW MMIC amplifiers operating in the S- and C-band frequency regime. The cascode approach is used to distribute voltage and self-heating in order to lower the Tj and NF while providing high linearity by operating from a higher supply voltage. These results suggest promise for next generation CATV, FTTX, software defined radio and BTS applications which demand higher linearity and BW to satisfy the high data throughput systems of the future.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116072557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062453
K. Murata, T. Saida, I. Ogawa, R. Kasahara, Y. Muramoto, H. Fukuyama, K. Sano, H. Nosaka, H. Kawakami
This paper describes device and integration technologies for 100-Gbit/s polarization division multiplexed quadrature phase shift keying integrated coherent receiver front-end. The silica-based planar lightwave circuits for the optical passive circuits, InP-based photodiode for the opto-electrical conversion, and InP HBT for the transimpedance amplification are used to achieve high-performance. A module-level hybrid integration technology based on a chip-scale packaged O/E converter is applied as the integration technology. The fabricated receiver front-end has a wide dynamic range of around 20dB with a constant local power of 13.5 dBm and an excellent common-mode rejection ratio of better than -25dB up to 25GHz.
{"title":"100-Gbit/s PDM-QPSK Integrated Coherent Receiver Front-End for Optical Communications","authors":"K. Murata, T. Saida, I. Ogawa, R. Kasahara, Y. Muramoto, H. Fukuyama, K. Sano, H. Nosaka, H. Kawakami","doi":"10.1109/CSICS.2011.6062453","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062453","url":null,"abstract":"This paper describes device and integration technologies for 100-Gbit/s polarization division multiplexed quadrature phase shift keying integrated coherent receiver front-end. The silica-based planar lightwave circuits for the optical passive circuits, InP-based photodiode for the opto-electrical conversion, and InP HBT for the transimpedance amplification are used to achieve high-performance. A module-level hybrid integration technology based on a chip-scale packaged O/E converter is applied as the integration technology. The fabricated receiver front-end has a wide dynamic range of around 20dB with a constant local power of 13.5 dBm and an excellent common-mode rejection ratio of better than -25dB up to 25GHz.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126433100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062494
V. Radisic, K. Leong, S. Sarkozy, X. Mei, W. Yoshida, Po-Hsin Liu, R. Lai
In this paper, a 210 GHz solid-state power amplifier (SSPA) module is presented. The amplifier MMIC uses sub-50 nm InP HEMT transistors, coplanar waveguide (CPW) technology, and on-chip electromagnetic transitions to waveguide. Two levels of power combining were used on-chip to achieve total transistor output periphery of 0.96 mm. The first level is a 1:4 CPW Dolph-Chebychev transformer. The second level is a two-way, novel dual transition to the waveguide. In this method, two amplifiers were placed on the MMIC die, each with independent transition to the waveguide, where their output power is combined. This method reduced the combining loss compared to traditional coupler methods. The SSPA module demonstrated saturated output power ¡Y 60 mW from 205 to 225 GHz and peak output power of 75 mW at 210 GHz, representing a significant increase in SSPA output power at these frequencies compared to the prior state-of-the-art.
{"title":"A 75 mW 210 GHz Power Amplifier Module","authors":"V. Radisic, K. Leong, S. Sarkozy, X. Mei, W. Yoshida, Po-Hsin Liu, R. Lai","doi":"10.1109/CSICS.2011.6062494","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062494","url":null,"abstract":"In this paper, a 210 GHz solid-state power amplifier (SSPA) module is presented. The amplifier MMIC uses sub-50 nm InP HEMT transistors, coplanar waveguide (CPW) technology, and on-chip electromagnetic transitions to waveguide. Two levels of power combining were used on-chip to achieve total transistor output periphery of 0.96 mm. The first level is a 1:4 CPW Dolph-Chebychev transformer. The second level is a two-way, novel dual transition to the waveguide. In this method, two amplifiers were placed on the MMIC die, each with independent transition to the waveguide, where their output power is combined. This method reduced the combining loss compared to traditional coupler methods. The SSPA module demonstrated saturated output power ¡Y 60 mW from 205 to 225 GHz and peak output power of 75 mW at 210 GHz, representing a significant increase in SSPA output power at these frequencies compared to the prior state-of-the-art.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114402402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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