Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062454
A. Bar-Cohen, J. Albrecht, J. Maurer
Near-junction thermal management is critical to achieving the promise of electronic and photonic devices using wide bandgap materials. In such devices, including GaN HEMTs in PAs, the thermal resistance associated with the "near-junction" region dominates the heat removal path and is often as large as the thermal resistance of all the other elements in the resistance chain. As part of DARPA's portfolio in Thermal Management Technologies (TMT), efforts are underway to develop transformative, paradigm-changing cooling techniques. This paper will briefly review the thermal management needs of WBG devices and DARPA's Thermal Management Technologies portfolio, with emphasis on the goals and status of these efforts relative to the current State-of-the-Art. Attention will then turn to promising options in near-junction cooling and the challenges inherent in realizing their potential for WBG device thermal management.
{"title":"Near-Junction Thermal Management for Wide Bandgap Devices","authors":"A. Bar-Cohen, J. Albrecht, J. Maurer","doi":"10.1109/CSICS.2011.6062454","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062454","url":null,"abstract":"Near-junction thermal management is critical to achieving the promise of electronic and photonic devices using wide bandgap materials. In such devices, including GaN HEMTs in PAs, the thermal resistance associated with the \"near-junction\" region dominates the heat removal path and is often as large as the thermal resistance of all the other elements in the resistance chain. As part of DARPA's portfolio in Thermal Management Technologies (TMT), efforts are underway to develop transformative, paradigm-changing cooling techniques. This paper will briefly review the thermal management needs of WBG devices and DARPA's Thermal Management Technologies portfolio, with emphasis on the goals and status of these efforts relative to the current State-of-the-Art. Attention will then turn to promising options in near-junction cooling and the challenges inherent in realizing their potential for WBG device thermal management.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123258990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062430
O. Inac, B. Cetinoneri, M. Uzunkol, Y. Atesal, Gabriel M. Rebeiz
This paper presents low-noise amplifiers (LNA) at 45¿C95 GHz, a frequency doubler at 180 GHz, active and passive mixers at 130¿C180 GHz fabricated in 45-nm Semiconductor-On-Insulator (SOI) CMOS process for digital and mixed-signal applications. The measured ft and fmax of a 30¡A1-¿Im transistor are 200 GHz at 0.3 mA/¿Im current density, referenced to the top metal layer. The measured gain and NF of LNAs are 15¿C11 dB and 3.3¿C6.0 dB at 45¿C95 GHz. The balanced doubler results in an output power of 1 mW and 8 dB conversion loss at 180 GHz. Passive double-balanced and active single-balanced mixers achieve conversion loss of 12¿C13 dB at 130¿C180 GHz, and 4 dB with 3-dB bandwidth of 145¿C161 GHz, respectively. This work shows that 45-nm SOI CMOS process results in state-of-the-art performance for millimeter-wave applications.
{"title":"Millimeter-Wave and THz Circuits in 45-nm SOI CMOS","authors":"O. Inac, B. Cetinoneri, M. Uzunkol, Y. Atesal, Gabriel M. Rebeiz","doi":"10.1109/CSICS.2011.6062430","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062430","url":null,"abstract":"This paper presents low-noise amplifiers (LNA) at 45¿C95 GHz, a frequency doubler at 180 GHz, active and passive mixers at 130¿C180 GHz fabricated in 45-nm Semiconductor-On-Insulator (SOI) CMOS process for digital and mixed-signal applications. The measured ft and fmax of a 30¡A1-¿Im transistor are 200 GHz at 0.3 mA/¿Im current density, referenced to the top metal layer. The measured gain and NF of LNAs are 15¿C11 dB and 3.3¿C6.0 dB at 45¿C95 GHz. The balanced doubler results in an output power of 1 mW and 8 dB conversion loss at 180 GHz. Passive double-balanced and active single-balanced mixers achieve conversion loss of 12¿C13 dB at 130¿C180 GHz, and 4 dB with 3-dB bandwidth of 145¿C161 GHz, respectively. This work shows that 45-nm SOI CMOS process results in state-of-the-art performance for millimeter-wave applications.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123095812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062496
A. Tessmann, H. Massler, U. Lewark, S. Wagner, I. Kallfass, A. Leuther
Two fully integrated H-band (220-325 GHz) submillimeter-wave monolithic integrated circuit (S-MMIC) heterodyne receivers have been successfully developed, based on a 50 nm metamorphic high electron mobility transistor (mHEMT) technology. A fabricated fundamental down-conversion receiver achieved a conversion gain of more than 11 dB in the frequency range from 270 to 310 GHz with an LO power of only 12 dBm. Furthermore, a subharmonic receiver S-MMIC was developed, consisting of an active frequency multiplier by three, a two stage driver amplifier, a single-ended resistive mixer, and a four-stage low-noise amplifier, demonstrating a conversion gain of more than 12 dB from 290 to 320 GHz with a subharmonic LO-power of 8 dBm. Grounded coplanar waveguide (GCPW) topology in combination with cascode transistors resulted in a very compact die size of less than 1.25 mm^2.
{"title":"Fully Integrated 300 GHz Receiver S-MMICs in 50 nm Metamorphic HEMT Technology","authors":"A. Tessmann, H. Massler, U. Lewark, S. Wagner, I. Kallfass, A. Leuther","doi":"10.1109/CSICS.2011.6062496","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062496","url":null,"abstract":"Two fully integrated H-band (220-325 GHz) submillimeter-wave monolithic integrated circuit (S-MMIC) heterodyne receivers have been successfully developed, based on a 50 nm metamorphic high electron mobility transistor (mHEMT) technology. A fabricated fundamental down-conversion receiver achieved a conversion gain of more than 11 dB in the frequency range from 270 to 310 GHz with an LO power of only 12 dBm. Furthermore, a subharmonic receiver S-MMIC was developed, consisting of an active frequency multiplier by three, a two stage driver amplifier, a single-ended resistive mixer, and a four-stage low-noise amplifier, demonstrating a conversion gain of more than 12 dB from 290 to 320 GHz with a subharmonic LO-power of 8 dBm. Grounded coplanar waveguide (GCPW) topology in combination with cascode transistors resulted in a very compact die size of less than 1.25 mm^2.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122328506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062478
S. Yamanaka, Takayuki Kobayashi, M. Nagatani
This paper describes high-speed and high-spectral efficiency optical transmission technologies that focus on channel rates beyond 100 Gb/s. Quadrature amplitude modulation (QAM) is adopted to achieve high spectral efficiency. First, we review recent progress in optical QAM transmission technologies. High-speed digital-to-analog converters (DACs) are key components for generating optical QAM signals. We recently developed a high-speed DAC fabricated by indium phosphide (InP) heterojunction bipolar transistors (HBTs) technology. It has a resolution of 6 bits and operates at up to 28 Gs/s. We performed a 25 GHz-spaced eleven-channel 171 Gb/s 16-QAM transmission experiment using our DAC. We achieved the record spectral efficiency-distance product of 9216 b/s/Hz-km (6.4 b/s/Hz x 1440 km) using the optical 16-QAM format.
{"title":"High-Order Multi-Level Optical Transmission for beyond 100 Gb/s Using High-Speed DACs","authors":"S. Yamanaka, Takayuki Kobayashi, M. Nagatani","doi":"10.1109/CSICS.2011.6062478","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062478","url":null,"abstract":"This paper describes high-speed and high-spectral efficiency optical transmission technologies that focus on channel rates beyond 100 Gb/s. Quadrature amplitude modulation (QAM) is adopted to achieve high spectral efficiency. First, we review recent progress in optical QAM transmission technologies. High-speed digital-to-analog converters (DACs) are key components for generating optical QAM signals. We recently developed a high-speed DAC fabricated by indium phosphide (InP) heterojunction bipolar transistors (HBTs) technology. It has a resolution of 6 bits and operates at up to 28 Gs/s. We performed a 25 GHz-spaced eleven-channel 171 Gb/s 16-QAM transmission experiment using our DAC. We achieved the record spectral efficiency-distance product of 9216 b/s/Hz-km (6.4 b/s/Hz x 1440 km) using the optical 16-QAM format.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126037661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062442
M. Choe, Kang-Jin Lee, M. Seo, M. Teshome
Abstract- In this work we present recent results on high-speed, multi-Nyquist Digital-to-Analog Converter (DAC) capable of RF signal generation well above 10GHz. The DAC is implemented Teledyne's InP double heterojunction bipolar transistor (DHBT) with 0.5im emitter width. The technology offers four level of gold interconnect with BCB dielectric, and thin-film resistor and MIM capacitor are available. Return-to-Zero (RZ) current switches are added to current steering DAC for high frequency wideband applications to achieve higher than 1GHz bandwidth. When clocked at 2.3GHz, the DAC output measures better than 60dB spurious-free dynamic range (SFDR) at 1GHz output frequency. With 2.7GHz data clock and 8.1GHz RZ clock, the measured performance is >50dBc SFDR at 8GHz output frequency. The chip measures 1450 x 2100im including bonding pads and dissipates 1.6 watt power.
{"title":"DC - 10GHz RF Digital to Analog Converter","authors":"M. Choe, Kang-Jin Lee, M. Seo, M. Teshome","doi":"10.1109/CSICS.2011.6062442","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062442","url":null,"abstract":"Abstract- In this work we present recent results on high-speed, multi-Nyquist Digital-to-Analog Converter (DAC) capable of RF signal generation well above 10GHz. The DAC is implemented Teledyne's InP double heterojunction bipolar transistor (DHBT) with 0.5im emitter width. The technology offers four level of gold interconnect with BCB dielectric, and thin-film resistor and MIM capacitor are available. Return-to-Zero (RZ) current switches are added to current steering DAC for high frequency wideband applications to achieve higher than 1GHz bandwidth. When clocked at 2.3GHz, the DAC output measures better than 60dB spurious-free dynamic range (SFDR) at 1GHz output frequency. With 2.7GHz data clock and 8.1GHz RZ clock, the measured performance is >50dBc SFDR at 8GHz output frequency. The chip measures 1450 x 2100im including bonding pads and dissipates 1.6 watt power.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132368314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062468
J. Dobes, M. Grábner
Novel two HEMT models are suggested in the paper with improved accuracy of higher-order derivatives, which is very important for modeling radio-frequency devices as mixers, etc. The proposed modifications of the models are based on empirical relations for the transconductance dependence on gate-source voltage. Moreover, a way is suggested how to extract the model parameters of various nonlinear HEMT models from a measured multibias s-parameter data set. The proposed extraction procedure is based on a three-step identification procedure that uses robust optimization methods. Finally, various HEMT models -- including the proposed ones -- are compared in terms of the root-mean-square error of DC characteristics and multibias s-parameters.
{"title":"Novel HEMT Models with Improved Higher-Order Derivatives and Extracting Their Parameters Using Multibias S-Parameters","authors":"J. Dobes, M. Grábner","doi":"10.1109/CSICS.2011.6062468","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062468","url":null,"abstract":"Novel two HEMT models are suggested in the paper with improved accuracy of higher-order derivatives, which is very important for modeling radio-frequency devices as mixers, etc. The proposed modifications of the models are based on empirical relations for the transconductance dependence on gate-source voltage. Moreover, a way is suggested how to extract the model parameters of various nonlinear HEMT models from a measured multibias s-parameter data set. The proposed extraction procedure is based on a three-step identification procedure that uses robust optimization methods. Finally, various HEMT models -- including the proposed ones -- are compared in terms of the root-mean-square error of DC characteristics and multibias s-parameters.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131184383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062473
S. Mahon
A new technique is proposed for the design of linear and power amplifiers at mm-wave frequencies where load-pull of large transistor output cells is difficult. The technique transforms the load-pull data on a small, standard foundry transistor layout to a pair of common-gate contours for the intrinsic device; one gate-source and one gate-drain. These are then recombined as an intrinsic drain-source contour for a larger and arbitrary transistor layout. A driver amplifier for the ETSI 42 GHz point-to-point radio band has been designed using the proposed technique. The fabricated MMIC consumes 1.5 watts and has a gain of 25 dB, and OIP3 of 36 dBm, OIP5 of 28 dBm and P1dB of 23 dBm which is believed to be the best reported result to date.
{"title":"A 42 GHz Amplifier Designed Using Common-Gate Load Pull","authors":"S. Mahon","doi":"10.1109/CSICS.2011.6062473","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062473","url":null,"abstract":"A new technique is proposed for the design of linear and power amplifiers at mm-wave frequencies where load-pull of large transistor output cells is difficult. The technique transforms the load-pull data on a small, standard foundry transistor layout to a pair of common-gate contours for the intrinsic device; one gate-source and one gate-drain. These are then recombined as an intrinsic drain-source contour for a larger and arbitrary transistor layout. A driver amplifier for the ETSI 42 GHz point-to-point radio band has been designed using the proposed technique. The fabricated MMIC consumes 1.5 watts and has a gain of 25 dB, and OIP3 of 36 dBm, OIP5 of 28 dBm and P1dB of 23 dBm which is believed to be the best reported result to date.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114344646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062434
H. T. Than, G. Sun, G. S. Cuellar, J. Zeng, N. T. Schultz, M. E. Moya, Y. Chung, B. Deckman, M. DeLisio
This paper describes the design and performance of a C-band amplifier with over 600 Watts of saturated output power. This amplifier is intended for use in commercial broadcast satellite uplink base stations. The amplifier uses spatial power combining to combine the output powers of sixteen internally matched 45-W GaAs FETs. The amplifier also comprises pre-amplification and driver amplification stages, a level control variable attenuator, and a predistortion linearizer. The unit also includes a power supply as well as a user monitor and control interface. We will present various measures of this amplifier's linearity performance, demonstrating its suitability for use in broadcast applications.
{"title":"A 600-W C-Band Amplifier Using Spatially Combined GaAs FETs","authors":"H. T. Than, G. Sun, G. S. Cuellar, J. Zeng, N. T. Schultz, M. E. Moya, Y. Chung, B. Deckman, M. DeLisio","doi":"10.1109/CSICS.2011.6062434","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062434","url":null,"abstract":"This paper describes the design and performance of a C-band amplifier with over 600 Watts of saturated output power. This amplifier is intended for use in commercial broadcast satellite uplink base stations. The amplifier uses spatial power combining to combine the output powers of sixteen internally matched 45-W GaAs FETs. The amplifier also comprises pre-amplification and driver amplification stages, a level control variable attenuator, and a predistortion linearizer. The unit also includes a power supply as well as a user monitor and control interface. We will present various measures of this amplifier's linearity performance, demonstrating its suitability for use in broadcast applications.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114611533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062444
Jerry Wang, J. Stanback, K. Fujii
An AlGaAs/InGaAs pHEMT process employing Deep-UV Phase-Shift lithography to create 0.15uM Y-shape gates has been developed and released to manufacturing. The gate formation process has high throughput and low cost compared to E-beam lithography and excellent process control has been achieved. Typical Fet characteristics are: peak fT=86Ghz, Vp=-1.0V, Gmmax=520mS/mm, Imax=575mA/mm, and BVdg=14 volts. A 9-section traveling wave amplifier (TWA) with 10dB gain up to 88 Ghz has been manufactured in this process.
{"title":"0.15uM Y-Gate pHEMT Process Using Deep-UV Phase-Shift Lithography","authors":"Jerry Wang, J. Stanback, K. Fujii","doi":"10.1109/CSICS.2011.6062444","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062444","url":null,"abstract":"An AlGaAs/InGaAs pHEMT process employing Deep-UV Phase-Shift lithography to create 0.15uM Y-shape gates has been developed and released to manufacturing. The gate formation process has high throughput and low cost compared to E-beam lithography and excellent process control has been achieved. Typical Fet characteristics are: peak fT=86Ghz, Vp=-1.0V, Gmmax=520mS/mm, Imax=575mA/mm, and BVdg=14 volts. A 9-section traveling wave amplifier (TWA) with 10dB gain up to 88 Ghz has been manufactured in this process.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114466618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/CSICS.2011.6062463
M. Parlak, J. Buckwalter
This paper presents a single-pole double-throw (SPDT), transmit/receive (T/R) switch operating from DC to 60 GHz. The SPDT switch is based on a series-shunt circuit with broadband input and output matching circuits and is implemented in a partially-depleted, 45-nm silicon-on-insulator (SOI) process. A buried oxide (BOX) layer is demonstrated to minimize substrate coupling. The switch exhibits a measured insertion loss of less than 1.7 dB at 45 GHz and less than 2.5 dB at 60 GHz with an isolation of greater than 25 dB at 45 GHz. To our knowledge, this is the lowest insertion loss demonstrated for an SPDT switch at 60 GHz in a CMOS process. With a control voltage of 1.2 V, the measured P1dB and IIP3 are 7.1 dBm and 18.2 dBm, respectively. The active chip area is 0.18×0.22 mm2.
{"title":"A 2.5-dB Insertion Loss, DC-60 GHz CMOS SPDT Switch in 45-nm SOI","authors":"M. Parlak, J. Buckwalter","doi":"10.1109/CSICS.2011.6062463","DOIUrl":"https://doi.org/10.1109/CSICS.2011.6062463","url":null,"abstract":"This paper presents a single-pole double-throw (SPDT), transmit/receive (T/R) switch operating from DC to 60 GHz. The SPDT switch is based on a series-shunt circuit with broadband input and output matching circuits and is implemented in a partially-depleted, 45-nm silicon-on-insulator (SOI) process. A buried oxide (BOX) layer is demonstrated to minimize substrate coupling. The switch exhibits a measured insertion loss of less than 1.7 dB at 45 GHz and less than 2.5 dB at 60 GHz with an isolation of greater than 25 dB at 45 GHz. To our knowledge, this is the lowest insertion loss demonstrated for an SPDT switch at 60 GHz in a CMOS process. With a control voltage of 1.2 V, the measured P1dB and IIP3 are 7.1 dBm and 18.2 dBm, respectively. The active chip area is 0.18×0.22 mm2.","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129585575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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