In this paper a low power continuous-time 4th order low pass Butterworth filter operating at power supply of 0.5 V is presented. A 3-dB bandwidth of 1 MHz using technology node of 0.18 μm is achieved. In order to achieve necessary head-room, the filter uses pseudo-differential bulk-driven transconductor. A master-slave based common mode feedback(CMFB) circuit sets the output common mode voltage of transconductor. The simulation results show that the filter has a dynamic range of 54 dB and consumes a total power of 36 μW when operating at a supply voltage of 0.5 V. The Figure of Merit (FOM) achieved by the filter is 0.05 fJ, lowest among similar low-voltage filters found in the literature. The simulation result show that the 3-dB bandwidth variation for process, voltage and temperature is less than ±10%.
{"title":"0.5 V, Low Power, 1 MHz Low Pass Filter in 0.18 µm CMOS Process","authors":"H. VasanthaM., T. Laxminidhi","doi":"10.1109/ISED.2012.46","DOIUrl":"https://doi.org/10.1109/ISED.2012.46","url":null,"abstract":"In this paper a low power continuous-time 4th order low pass Butterworth filter operating at power supply of 0.5 V is presented. A 3-dB bandwidth of 1 MHz using technology node of 0.18 μm is achieved. In order to achieve necessary head-room, the filter uses pseudo-differential bulk-driven transconductor. A master-slave based common mode feedback(CMFB) circuit sets the output common mode voltage of transconductor. The simulation results show that the filter has a dynamic range of 54 dB and consumes a total power of 36 μW when operating at a supply voltage of 0.5 V. The Figure of Merit (FOM) achieved by the filter is 0.05 fJ, lowest among similar low-voltage filters found in the literature. The simulation result show that the 3-dB bandwidth variation for process, voltage and temperature is less than ±10%.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125479839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Maiti, Subhadip Kundu, Arpita Dutta, S. Chattopadhyay
In modern deep sub-micron technology, it is very crucial to have quality product with low power test and desired level of fault coverage. In this paper, we address a technique to reduce test length with efficiently managed scan power and higher test quality, targeting to achieve a desired level of fault coverage with all essential (marked) faults being covered as well. This can aid in achieving a trade-off between test time and quality assurance of the product. It can provide a level of confidence about the correctness of system functionalities for the amount of test effort incorporated. Experimental results of our approach on ISCAS'89 benchmark circuits show a good reduction in test length with improved fault coverage. It also makes the resulting test set power aware.
{"title":"Confidence Based Power Aware Testing","authors":"T. Maiti, Subhadip Kundu, Arpita Dutta, S. Chattopadhyay","doi":"10.1109/ISED.2012.22","DOIUrl":"https://doi.org/10.1109/ISED.2012.22","url":null,"abstract":"In modern deep sub-micron technology, it is very crucial to have quality product with low power test and desired level of fault coverage. In this paper, we address a technique to reduce test length with efficiently managed scan power and higher test quality, targeting to achieve a desired level of fault coverage with all essential (marked) faults being covered as well. This can aid in achieving a trade-off between test time and quality assurance of the product. It can provide a level of confidence about the correctness of system functionalities for the amount of test effort incorporated. Experimental results of our approach on ISCAS'89 benchmark circuits show a good reduction in test length with improved fault coverage. It also makes the resulting test set power aware.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126614073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As more and more functions are integrated on a System-On-Chip (SoC), the number of on-chip peripherals is increasing sharply. Most of these peripheral functions use an internal scratchpad memory for temporary storage of data. Hence, the area and power penalty due to a large number of these scratchpad memories distributed across the die is significant. This paper proposes a centralized scratchpad memory architecture which can be used by different peripherals in a SoC on need basis. Since the use cases on embedded platforms do not require usage of all peripherals simultaneously, the memory footprint in a shared configuration is considerably less compared to cumulative memory of individual modules. Each peripheral has to request for allocation of a chunk of memory for read-write operations. Finally, the peripheral releases the memory after its usage is complete. This paper discusses the micro-architectural details of the memory controller including the several integration challenges. We have shown that such a centralized scheme significantly reduces the area and leakage power consumption of scratchpad memories in several network processor SoCs ranging from 20% to 60%.
{"title":"Dynamic Sharing of On-Chip Scratchpad Memory on Embedded Platforms","authors":"Sandip Ghosh, P. Ghosh, Sourav Roy","doi":"10.1109/ISED.2012.31","DOIUrl":"https://doi.org/10.1109/ISED.2012.31","url":null,"abstract":"As more and more functions are integrated on a System-On-Chip (SoC), the number of on-chip peripherals is increasing sharply. Most of these peripheral functions use an internal scratchpad memory for temporary storage of data. Hence, the area and power penalty due to a large number of these scratchpad memories distributed across the die is significant. This paper proposes a centralized scratchpad memory architecture which can be used by different peripherals in a SoC on need basis. Since the use cases on embedded platforms do not require usage of all peripherals simultaneously, the memory footprint in a shared configuration is considerably less compared to cumulative memory of individual modules. Each peripheral has to request for allocation of a chunk of memory for read-write operations. Finally, the peripheral releases the memory after its usage is complete. This paper discusses the micro-architectural details of the memory controller including the several integration challenges. We have shown that such a centralized scheme significantly reduces the area and leakage power consumption of scratchpad memories in several network processor SoCs ranging from 20% to 60%.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"332 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121255168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses the problem of application mapping for Mesh-of-Tree (MoT) based Network-on-Chip. It proposes a new mapping technique based on discrete Particle Swarm Optimization (PSO) to map the cores of the core graph to the routers. The results have been compared with techniques reported in the literature for a number of benchmark applications. The reported strategy produces results superior to those obtained via existing approaches within a reasonable CPU time.
{"title":"Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization","authors":"P. Sahu, Ashish Sharma, S. Chattopadhyay","doi":"10.1109/ISED.2012.17","DOIUrl":"https://doi.org/10.1109/ISED.2012.17","url":null,"abstract":"This paper addresses the problem of application mapping for Mesh-of-Tree (MoT) based Network-on-Chip. It proposes a new mapping technique based on discrete Particle Swarm Optimization (PSO) to map the cores of the core graph to the routers. The results have been compared with techniques reported in the literature for a number of benchmark applications. The reported strategy produces results superior to those obtained via existing approaches within a reasonable CPU time.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"52 1-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132563614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes an analytical model for the bottom gate structure comprising contacts at above the semiconductor and/or insulator layer in organic thin film transistor (OTFT) on the basis of contact resistance effect. These devices suffer from limitations such as contact resistance, low mobility regions and low mobility of charge carriers. In lieu of that, contact resistance and contact effect are demonstrated by two-dimensional device simulation. The current equations are derived from linear to saturation regime by considering overlapping region among the contacts, active layer, and effective channel between the contacts. To validate the proposed analytical model a comparative analysis is carried out with the device simulation and experimental results and observed a good agreement.
{"title":"Analysis of Contact Resistance Effect on Performance of Organic Thin Film Transistors","authors":"B. Kumar, B. Kaushik, Y. S. Negi","doi":"10.1109/ISED.2012.64","DOIUrl":"https://doi.org/10.1109/ISED.2012.64","url":null,"abstract":"This paper proposes an analytical model for the bottom gate structure comprising contacts at above the semiconductor and/or insulator layer in organic thin film transistor (OTFT) on the basis of contact resistance effect. These devices suffer from limitations such as contact resistance, low mobility regions and low mobility of charge carriers. In lieu of that, contact resistance and contact effect are demonstrated by two-dimensional device simulation. The current equations are derived from linear to saturation regime by considering overlapping region among the contacts, active layer, and effective channel between the contacts. To validate the proposed analytical model a comparative analysis is carried out with the device simulation and experimental results and observed a good agreement.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132809408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fractional calculus is considered as an effective tool in representing differential equations and systems. Fractional differential equations are generalizations of ordinary differential equations to an arbitrary non integer order. The idea of Fractional Differential Equations are used to analyse the semiconductor equations. Application of fractional calculus will add additional nonlinearity and can be used to model more complex phenomena. In this work, the fractional calculus computations are done using matrix approach and algorithams are implemented in MATLAB. The pn junction characteristics is simulated for fractional orders. As the order reaches its integer equivalents, normal semiconductor behaviour is obtained, validating the simulated results. The pn junction characteristics is simulated for fractional order and deviation from the actual characteristics for various fractional orders are analysed.
{"title":"Fractional Interpretation of Anomalous Diffusion and Semiconductor Equations","authors":"Rohith G., Ajayan K.K.","doi":"10.1109/ISED.2012.25","DOIUrl":"https://doi.org/10.1109/ISED.2012.25","url":null,"abstract":"Fractional calculus is considered as an effective tool in representing differential equations and systems. Fractional differential equations are generalizations of ordinary differential equations to an arbitrary non integer order. The idea of Fractional Differential Equations are used to analyse the semiconductor equations. Application of fractional calculus will add additional nonlinearity and can be used to model more complex phenomena. In this work, the fractional calculus computations are done using matrix approach and algorithams are implemented in MATLAB. The pn junction characteristics is simulated for fractional orders. As the order reaches its integer equivalents, normal semiconductor behaviour is obtained, validating the simulated results. The pn junction characteristics is simulated for fractional order and deviation from the actual characteristics for various fractional orders are analysed.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133978327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I-V characteristic is one of the important results produced by a device simulator. In this article, a novel and interactive matrix based algorithm is presented to draw the device structure in 2-D or 3-D style and to plot the I-V characteristic of the device for user specified doping and biasing conditions. Algorithm creates 2-D or 3-D matrix of the device from device description mentioned by the user. This device matrix undergoes many different operations, and various mathematical computations are performed, using which I-V characteristic is plotted. This approach gives a novel idea of basic device level tool development. The students and device level engineers can find this work useful which offers them an interactive and instant way to draw I-V characteristics of the device. The algorithm implementation is modular and matrix based, which is done using MATLAB®.
{"title":"Design of a Static Current Simulator Using Device Matrix Approach","authors":"D. Bharti, Abhijit R. Asati","doi":"10.1109/ISED.2012.38","DOIUrl":"https://doi.org/10.1109/ISED.2012.38","url":null,"abstract":"I-V characteristic is one of the important results produced by a device simulator. In this article, a novel and interactive matrix based algorithm is presented to draw the device structure in 2-D or 3-D style and to plot the I-V characteristic of the device for user specified doping and biasing conditions. Algorithm creates 2-D or 3-D matrix of the device from device description mentioned by the user. This device matrix undergoes many different operations, and various mathematical computations are performed, using which I-V characteristic is plotted. This approach gives a novel idea of basic device level tool development. The students and device level engineers can find this work useful which offers them an interactive and instant way to draw I-V characteristics of the device. The algorithm implementation is modular and matrix based, which is done using MATLAB®.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115532104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jamil Galadanci, R. Shafik, J. Mathew, A. Acharyya, D. Pradhan
Maintaining good glycemic control is a continuous challenge for type-1 diabetic patients. The current means of insulin therapy are seen to subject patients to hyper- and hypoglycemic episodes. With the advancement of computer science and technology, an artificial pancreas, a computerized device that will automatically control patient's blood glucose level by providing the substitute for the insulin supply functionality of a healthy pancreas was proposed. The main challenge faced by the development of this device is a fully closed-loop control system. In this paper we proposed an artificial pancreas system with an adaptive closed-loop control strategy that computes the appropriate insulin infusion rate and thereby keeping the patient's blood glucose concentration within normoglycemic range. The adaptability is achieved through a rigorous pattern recognition technique with patient-specific glucose readings obtained through glucose monitor at a given sampling step. The performance of the control strategy is assessed using the simulation results carried out under various physiological disturbances and meal intake.
{"title":"A Closed-Loop Control Strategy for Glucose Control in Artificial Pancreas Systems","authors":"Jamil Galadanci, R. Shafik, J. Mathew, A. Acharyya, D. Pradhan","doi":"10.1109/ISED.2012.76","DOIUrl":"https://doi.org/10.1109/ISED.2012.76","url":null,"abstract":"Maintaining good glycemic control is a continuous challenge for type-1 diabetic patients. The current means of insulin therapy are seen to subject patients to hyper- and hypoglycemic episodes. With the advancement of computer science and technology, an artificial pancreas, a computerized device that will automatically control patient's blood glucose level by providing the substitute for the insulin supply functionality of a healthy pancreas was proposed. The main challenge faced by the development of this device is a fully closed-loop control system. In this paper we proposed an artificial pancreas system with an adaptive closed-loop control strategy that computes the appropriate insulin infusion rate and thereby keeping the patient's blood glucose concentration within normoglycemic range. The adaptability is achieved through a rigorous pattern recognition technique with patient-specific glucose readings obtained through glucose monitor at a given sampling step. The performance of the control strategy is assessed using the simulation results carried out under various physiological disturbances and meal intake.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124396051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Sen, M. Dutta, Debajyoty Banik, D. Singh, B. Sikdar
This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the reversible QCA structure (RQCA) introduced in this paper. A fault tolerant architecture of reversible ALU is also synthesized. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.
{"title":"Design of Fault Tolerant Reversible Arithmetic Logic Unit in QCA","authors":"B. Sen, M. Dutta, Debajyoty Banik, D. Singh, B. Sikdar","doi":"10.1109/ISED.2012.50","DOIUrl":"https://doi.org/10.1109/ISED.2012.50","url":null,"abstract":"This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the reversible QCA structure (RQCA) introduced in this paper. A fault tolerant architecture of reversible ALU is also synthesized. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128985354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to extensive use of network services and applications, most of the enterprise networks today deploy policy based security devices (e.g. routers, firewalls, IPSec etc.) for controlling accesses to network resources based on organizational security policy. The organizational network security policy is becoming more fine-grained, where access control list (ACL) configuration depends on various constraints like, service priority, time, location etc. The major challenge that the network administrators are facing today is to determine the correct access control configurations that satisfy the organizational policy. Throughout the last two decades, a significant amount of research has been done in formally verifying the correctness and consistency of access control policy configurations in enterprise network. However, this bottom-up analysis may not be useful because of its high state-space requirement for large scale networks. In addition, this approach requires repairing sequences of misconfigurations iteratively to meet a specific requirement. This paper presents a framework for synthesizing correct and conflict-free ACL configuration model, given the global organizational security policy and underlying network topology. This framework includes two major functions: (i) deriving the conflict-free model of the organizational security policy, and (ii) extraction of the correct ACL distributions for the network. The framework formally models the organizational security policy and generates the conflict-free policy model by resolving the policy rule conflicts. Then, ACL model is extracted based on the conflict-free policy model and the underlying network topology. The efficacy of the proposed framework has been demonstrated through a case study.
{"title":"Policy Based ACL Configuration Synthesis in Enterprise Networks: A Formal Approach","authors":"Soumyadev Maity, P. Bera, Soumya K. Ghosh","doi":"10.1109/ISED.2012.72","DOIUrl":"https://doi.org/10.1109/ISED.2012.72","url":null,"abstract":"Due to extensive use of network services and applications, most of the enterprise networks today deploy policy based security devices (e.g. routers, firewalls, IPSec etc.) for controlling accesses to network resources based on organizational security policy. The organizational network security policy is becoming more fine-grained, where access control list (ACL) configuration depends on various constraints like, service priority, time, location etc. The major challenge that the network administrators are facing today is to determine the correct access control configurations that satisfy the organizational policy. Throughout the last two decades, a significant amount of research has been done in formally verifying the correctness and consistency of access control policy configurations in enterprise network. However, this bottom-up analysis may not be useful because of its high state-space requirement for large scale networks. In addition, this approach requires repairing sequences of misconfigurations iteratively to meet a specific requirement. This paper presents a framework for synthesizing correct and conflict-free ACL configuration model, given the global organizational security policy and underlying network topology. This framework includes two major functions: (i) deriving the conflict-free model of the organizational security policy, and (ii) extraction of the correct ACL distributions for the network. The framework formally models the organizational security policy and generates the conflict-free policy model by resolving the policy rule conflicts. Then, ACL model is extracted based on the conflict-free policy model and the underlying network topology. The efficacy of the proposed framework has been demonstrated through a case study.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116904319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：