Rohit Srivastava, Nandini Mudgil, Gaurav Gupta, H. Mondal
With growing complexity of semiconductor devices due to increase in the functionality along with reduced time to market requirements, the semiconductor companies strive to deliver zero defect products and the associated software in short development cycles. In reduced product development cycle customers expect a quality device and reliable software like device drivers, protocol stacks and other middleware package from semiconductor suppliers. The SoC verification infrastructure reuse has the potential to significantly reduce verification cycle time and reduce overall time to market for SoC delivery. In this paper the approach of using the low level software device drivers for front-end SoC functional verification and validation is taken. The same device drivers also run under the customer's application. This approach enables the verification environment to cover system level scenario testing with the added advantage of checking all possible future issues that may occur at customer end if escaped. In this technique the reusable verification stimulus is written on top of existing Verilog, SystemVerilog verification components and software device drivers. The observed benefits of this technique are reduced time required for setting up simulation and emulation testbench, low level driver validation and ease of stimulus generation for complex scenarios. The advantage with this approach is the early verification of device driver software hence reducing the device driver and related software development cycle time. This methodology led to around 50% reduction in emulation testbench setup time. Initial applications are also enabled on this infrastructure for the customer demos.
{"title":"SoC Time to Market Improvement through Device Driver Reuse: An Industrial Experience","authors":"Rohit Srivastava, Nandini Mudgil, Gaurav Gupta, H. Mondal","doi":"10.1109/ISED.2012.61","DOIUrl":"https://doi.org/10.1109/ISED.2012.61","url":null,"abstract":"With growing complexity of semiconductor devices due to increase in the functionality along with reduced time to market requirements, the semiconductor companies strive to deliver zero defect products and the associated software in short development cycles. In reduced product development cycle customers expect a quality device and reliable software like device drivers, protocol stacks and other middleware package from semiconductor suppliers. The SoC verification infrastructure reuse has the potential to significantly reduce verification cycle time and reduce overall time to market for SoC delivery. In this paper the approach of using the low level software device drivers for front-end SoC functional verification and validation is taken. The same device drivers also run under the customer's application. This approach enables the verification environment to cover system level scenario testing with the added advantage of checking all possible future issues that may occur at customer end if escaped. In this technique the reusable verification stimulus is written on top of existing Verilog, SystemVerilog verification components and software device drivers. The observed benefits of this technique are reduced time required for setting up simulation and emulation testbench, low level driver validation and ease of stimulus generation for complex scenarios. The advantage with this approach is the early verification of device driver software hence reducing the device driver and related software development cycle time. This methodology led to around 50% reduction in emulation testbench setup time. Initial applications are also enabled on this infrastructure for the customer demos.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125385534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Improving the Noise margin is one of the important challenge in every state of the art SRAM design. Due to the Process variations like threshold voltage variations, supply voltage variations etc.. in scaled technologies, stable operation of the bit cell is critical to obtain with high yield in low-voltage SRAM. In this paper a new assist technique (Read assist and write assist) is proposed to enhance the read and write margins of the 6T SRAM bit cell and the same write assist circuit is applicable to enhance the write margin of the 8T SRAM bit cell. The simulations are performed in 90nm TSMC process Technology node and the read and write margin simulation results are compared with different SRAM circuits like 6T SRAM bit cell with cell ratio of 1, 2, 3 and Dynamic word line swing technique and 8T SRAM bit cell. The effect of temperature and threshold voltage values on Read and Write margins are observed. By using the proposed read assist technique the read margin is improved by 2.375 times for 6T cell and with write assist technique the write margin is improved by 1.89 times for 6T and 8T cells.
{"title":"A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell","authors":"Santhosh Keshavarapu, Saumya Jain, M. Pattanaik","doi":"10.1109/ISED.2012.55","DOIUrl":"https://doi.org/10.1109/ISED.2012.55","url":null,"abstract":"Improving the Noise margin is one of the important challenge in every state of the art SRAM design. Due to the Process variations like threshold voltage variations, supply voltage variations etc.. in scaled technologies, stable operation of the bit cell is critical to obtain with high yield in low-voltage SRAM. In this paper a new assist technique (Read assist and write assist) is proposed to enhance the read and write margins of the 6T SRAM bit cell and the same write assist circuit is applicable to enhance the write margin of the 8T SRAM bit cell. The simulations are performed in 90nm TSMC process Technology node and the read and write margin simulation results are compared with different SRAM circuits like 6T SRAM bit cell with cell ratio of 1, 2, 3 and Dynamic word line swing technique and 8T SRAM bit cell. The effect of temperature and threshold voltage values on Read and Write margins are observed. By using the proposed read assist technique the read margin is improved by 2.375 times for 6T cell and with write assist technique the write margin is improved by 1.89 times for 6T and 8T cells.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130644528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Synthetic Aperture Radar (SAR) is an all-weather remote sensing technology and occupies a great position in disaster observation and geological mapping. The main challenge for SAR processing is the huge volume of raw data, which demands tremendous computation. This limits the utilization of SAR, especially for real-time applications. On the other hand, recent developments in Graphics Processing Unit (GPU) technology, which obtain general processing capability, high parallel computation performance, and ultra wide memory bandwidth, offer a novel method for computationally intensive applications. This work proposes a parallel implementation of SAR imaging on GPU via Compute Unified Device Architecture (CUDA), and provides a potential solution for SAR real-time processing. The results show that the proposed method obtained a speedup of 31.72, compared to a CPU platform.
{"title":"GPU-based Parallel Implementation of SAR Imaging","authors":"Xingxing Jin, S. Ko","doi":"10.1109/ISED.2012.35","DOIUrl":"https://doi.org/10.1109/ISED.2012.35","url":null,"abstract":"Synthetic Aperture Radar (SAR) is an all-weather remote sensing technology and occupies a great position in disaster observation and geological mapping. The main challenge for SAR processing is the huge volume of raw data, which demands tremendous computation. This limits the utilization of SAR, especially for real-time applications. On the other hand, recent developments in Graphics Processing Unit (GPU) technology, which obtain general processing capability, high parallel computation performance, and ultra wide memory bandwidth, offer a novel method for computationally intensive applications. This work proposes a parallel implementation of SAR imaging on GPU via Compute Unified Device Architecture (CUDA), and provides a potential solution for SAR real-time processing. The results show that the proposed method obtained a speedup of 31.72, compared to a CPU platform.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128858616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Feature preserved enhancement is of great interest in medical ultrasound images. Speckle is a main factor which affects the quality, contrast resolution and most importantly texture information present in ultrasound images and can make the post-processing difficult. This paper presents a new enhancement approach which is based on discrete shearlet transform (DST) and thresholding scheme. The DST, a new efficient multiscale geometric representation with the different features of anisotropy, localization, directionality and multiscale, is employed to provide effective representation of the noisy coefficients. Thresholding schemes are applied to the noisy DST coefficients to improve the denoising efficiency and preserve the edge features effectively with this consideration that blurring associated with speckle reduction should be less and fine details are enhanced/preserved properly for the visual enhancement of ultrasound images. The presented algorithm also helps to improve the visual quality of the ultrasound images. Experimental results demonstrate the ability of proposed method for noise suppression, feature and edge preservation defined in terms of different performance measures.
{"title":"Enhancement of Medical Ultrasound Images Using Multiscale Discrete Shearlet Transform Based Thresholding","authors":"Deep Gupta, R. Anand, B. Tyagi","doi":"10.1109/ISED.2012.52","DOIUrl":"https://doi.org/10.1109/ISED.2012.52","url":null,"abstract":"Feature preserved enhancement is of great interest in medical ultrasound images. Speckle is a main factor which affects the quality, contrast resolution and most importantly texture information present in ultrasound images and can make the post-processing difficult. This paper presents a new enhancement approach which is based on discrete shearlet transform (DST) and thresholding scheme. The DST, a new efficient multiscale geometric representation with the different features of anisotropy, localization, directionality and multiscale, is employed to provide effective representation of the noisy coefficients. Thresholding schemes are applied to the noisy DST coefficients to improve the denoising efficiency and preserve the edge features effectively with this consideration that blurring associated with speckle reduction should be less and fine details are enhanced/preserved properly for the visual enhancement of ultrasound images. The presented algorithm also helps to improve the visual quality of the ultrasound images. Experimental results demonstrate the ability of proposed method for noise suppression, feature and edge preservation defined in terms of different performance measures.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129361635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Register file structures in modern microprocessors usually employ wide fan-in dynamic CMOS OR gates. Weak keepers have been traditionally used to resolve the low noise margin problem of dynamic CMOS design. Scaling trends and process variation issues in CMOS design have reduced the effectiveness of this weak PMOS keeper. On the other hand large sized PMOS keeper used in wide fan-in dynamic OR gate results in contention between the pull down network (PDN) and the keeper. As a consequence of contention there is an unnecessary increase in power dissipation and loss in performance. In this paper a process variation tolerant wide fan-in dynamic OR gate with a new keeper design is proposed which is capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay. Simulation results at 50 nm shows that the power dissipation and delay have been reduced by 40% and 35% respectively as compared to the wide fan-in dynamic OR gate with conventional keeper under different levels of process variation.
{"title":"A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate","authors":"V. Mahor, Akanksha Chouhan, M. Pattanaik","doi":"10.1109/ISED.2012.29","DOIUrl":"https://doi.org/10.1109/ISED.2012.29","url":null,"abstract":"Register file structures in modern microprocessors usually employ wide fan-in dynamic CMOS OR gates. Weak keepers have been traditionally used to resolve the low noise margin problem of dynamic CMOS design. Scaling trends and process variation issues in CMOS design have reduced the effectiveness of this weak PMOS keeper. On the other hand large sized PMOS keeper used in wide fan-in dynamic OR gate results in contention between the pull down network (PDN) and the keeper. As a consequence of contention there is an unnecessary increase in power dissipation and loss in performance. In this paper a process variation tolerant wide fan-in dynamic OR gate with a new keeper design is proposed which is capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay. Simulation results at 50 nm shows that the power dissipation and delay have been reduced by 40% and 35% respectively as compared to the wide fan-in dynamic OR gate with conventional keeper under different levels of process variation.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122672568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the ESL design flow, the crucial task of developing a golden model that correctly implements the natural-language top-level specification has received little attention so far. The major drawback of the current practice is the isolation of design and verification. Motivated by this and the recent advance of verification techniques for SystemC ESL models, we propose a novel methodology to develop a correct SystemC golden model from the top-level specification. The proposed methodology is driven by the requirements and the scenarios in the specification with design and verification going hand in hand. An early formalization of requirements and scenarios produces a set of properties and a testbench together with a code skeleton that will be successively extended to a full SystemC ESL model. The availability of properties and a testbench beforehand enables verification-driven development of the model. The advantages of the methodology are discussed and demonstrated by a case study.
{"title":"From Requirements and Scenarios to ESL Design in SystemC","authors":"H. M. Le, Daniel Große, R. Drechsler","doi":"10.1109/ISED.2012.36","DOIUrl":"https://doi.org/10.1109/ISED.2012.36","url":null,"abstract":"In the ESL design flow, the crucial task of developing a golden model that correctly implements the natural-language top-level specification has received little attention so far. The major drawback of the current practice is the isolation of design and verification. Motivated by this and the recent advance of verification techniques for SystemC ESL models, we propose a novel methodology to develop a correct SystemC golden model from the top-level specification. The proposed methodology is driven by the requirements and the scenarios in the specification with design and verification going hand in hand. An early formalization of requirements and scenarios produces a set of properties and a testbench together with a code skeleton that will be successively extended to a full SystemC ESL model. The availability of properties and a testbench beforehand enables verification-driven development of the model. The advantages of the methodology are discussed and demonstrated by a case study.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"294 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122789436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For getting high quality complex SoCs in market well in time requires many cross functional teams to work in tandem. One of the areas which we are focusing in this paper is collaboration between Validation and ATE teams. Validation needs to give production functional patterns to ATE to qualify the chip in mass production. These tests may be speed hunted patterns for Powerpc core or complex pattern for various IPs. Porting of validation testcases to ATE is a significant task and requires Logic Analyzer to capture signals. This causes significant delay in generating production ATE patterns. In this paper, we propose a new methodology where using scripts we can convert a validation test to ATE compatible testcase. One of the main advantage of this flow is that for pattern generation, there is no need to run the testcase either in simulation/emulation or to capture signals using Logic Analyzer. This flow also brings in a lot of debug capabilities and same test can be run across emulation, simulation, ATE and validation board. The new approach helps customer debug where customer failing scenarios can be converted into ATE patterns in matter of seconds.
{"title":"Bridging Validation and Automatic Test Equipment (ATE) Environment","authors":"A. Gupta, Gaurav Verma","doi":"10.1109/ISED.2012.39","DOIUrl":"https://doi.org/10.1109/ISED.2012.39","url":null,"abstract":"For getting high quality complex SoCs in market well in time requires many cross functional teams to work in tandem. One of the areas which we are focusing in this paper is collaboration between Validation and ATE teams. Validation needs to give production functional patterns to ATE to qualify the chip in mass production. These tests may be speed hunted patterns for Powerpc core or complex pattern for various IPs. Porting of validation testcases to ATE is a significant task and requires Logic Analyzer to capture signals. This causes significant delay in generating production ATE patterns. In this paper, we propose a new methodology where using scripts we can convert a validation test to ATE compatible testcase. One of the main advantage of this flow is that for pattern generation, there is no need to run the testcase either in simulation/emulation or to capture signals using Logic Analyzer. This flow also brings in a lot of debug capabilities and same test can be run across emulation, simulation, ATE and validation board. The new approach helps customer debug where customer failing scenarios can be converted into ATE patterns in matter of seconds.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129269348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. De, S. Kumari, V. Khare, S. S. Pal, Anindya Sadhukhan, V. Meshram, S. K. Thakur, S. Saha
The paper describes the design, development and testing of a three phase prototype Voltage Source Inverter (VSI) as part of the Superconducting Magnetic Energy Storage (SMES) system technology development at Variable Energy Cyclotron Centre (VECC), Kolkata. Following a Dynamic Voltage Restorer (DVR) topology the paper details the electrical aspects of the design and the mathematical model thus formulated. The block diagram of the digital control, implemented by a fixed point DSP based controller (DSC) has been explained with reporting of the test results on a nominal load. A generalized formulation has been attempted so as to allow designers to utilize it for future applications.
{"title":"Design, Development and Testing of a DSP Based Dynamic Voltage Restorer","authors":"A. De, S. Kumari, V. Khare, S. S. Pal, Anindya Sadhukhan, V. Meshram, S. K. Thakur, S. Saha","doi":"10.1109/ISED.2012.16","DOIUrl":"https://doi.org/10.1109/ISED.2012.16","url":null,"abstract":"The paper describes the design, development and testing of a three phase prototype Voltage Source Inverter (VSI) as part of the Superconducting Magnetic Energy Storage (SMES) system technology development at Variable Energy Cyclotron Centre (VECC), Kolkata. Following a Dynamic Voltage Restorer (DVR) topology the paper details the electrical aspects of the design and the mathematical model thus formulated. The block diagram of the digital control, implemented by a fixed point DSP based controller (DSC) has been explained with reporting of the test results on a nominal load. A generalized formulation has been attempted so as to allow designers to utilize it for future applications.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130489879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This research paper analyzes the performance of organic thin film transistor (OTFT) for two typical structures, viz., bottom gate top contact (BGTC) and bottom gate bottom contact (BGBC). The analysis is carried out for channel length (L) from 5 to 50 μm. A significant reduction in drain current for top contact is observed, however, it remains constant for the bottom contact device. Transconductance of the top contact device falls about 50% from 5 to 10 μm L, however, for bottom contact only 1% reduction is observed. Besides this, mobility in top contact is almost constant, whereas in bottom contact, mobility increases with larger channel lengths. Furthermore, total resistance decreases with higher gate bias, due to increase in carrier density within a channel and near contacts for both devices.
{"title":"Analysis of Top and Bottom Contact Organic Transistor Performance for Different Technology Nodes","authors":"P. Mittal, Y. S. Negi, R. Singh","doi":"10.1109/ISED.2012.60","DOIUrl":"https://doi.org/10.1109/ISED.2012.60","url":null,"abstract":"This research paper analyzes the performance of organic thin film transistor (OTFT) for two typical structures, viz., bottom gate top contact (BGTC) and bottom gate bottom contact (BGBC). The analysis is carried out for channel length (L) from 5 to 50 μm. A significant reduction in drain current for top contact is observed, however, it remains constant for the bottom contact device. Transconductance of the top contact device falls about 50% from 5 to 10 μm L, however, for bottom contact only 1% reduction is observed. Besides this, mobility in top contact is almost constant, whereas in bottom contact, mobility increases with larger channel lengths. Furthermore, total resistance decreases with higher gate bias, due to increase in carrier density within a channel and near contacts for both devices.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115895033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Agrawal, Pinalkumar Engineer, R. Velmurugan, S. Patkar
There is a continuous requirement of enhancing the computation speed with minimum resources to improve performance of signal processing algorithm. This paper proposes an architecture and implementation of a modified color histogram based Particle filter for object tracking in video. This architecture implements weight calculation and histogram calculation in a highly parallel form. The proposed architecture occupies less resource saving by effective memory utilization. The performance of the algorithm is demonstrated using a single object scenario.
{"title":"FPGA Implementation of Particle Filter Based Object Tracking in Video","authors":"S. Agrawal, Pinalkumar Engineer, R. Velmurugan, S. Patkar","doi":"10.1109/ISED.2012.41","DOIUrl":"https://doi.org/10.1109/ISED.2012.41","url":null,"abstract":"There is a continuous requirement of enhancing the computation speed with minimum resources to improve performance of signal processing algorithm. This paper proposes an architecture and implementation of a modified color histogram based Particle filter for object tracking in video. This architecture implements weight calculation and histogram calculation in a highly parallel form. The proposed architecture occupies less resource saving by effective memory utilization. The performance of the algorithm is demonstrated using a single object scenario.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123430274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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