In the nanometer regime carbon nanotube has been a potential candidate in replacing the traditional copper based interconnects. The work in this paper analyzes the delay of multi-wall carbon nanotube (MWCNT) based interconnect systems at the system level by implementing a four-bit array multiplier using MWCNT based interconnects. The layout of the multiplier is drawn using MWCNT based interconnects and delay has been analyzed and compared with that of the traditional copper based interconnects. It has been observed that MWCNT based design has 3.4% less delay in the critical path as compared to the copper based design. The paper also describes a methodology of modeling and analyzing a system designed with MWCNT interconnects, using the conventional chip design flow and tools.
{"title":"Design of 4-Bit Array Multiplier Using Multi-wall Carbon Nanotube Interconnects","authors":"Debaprasad Das, Sourav Das, H. Rahaman","doi":"10.1109/ISED.2012.19","DOIUrl":"https://doi.org/10.1109/ISED.2012.19","url":null,"abstract":"In the nanometer regime carbon nanotube has been a potential candidate in replacing the traditional copper based interconnects. The work in this paper analyzes the delay of multi-wall carbon nanotube (MWCNT) based interconnect systems at the system level by implementing a four-bit array multiplier using MWCNT based interconnects. The layout of the multiplier is drawn using MWCNT based interconnects and delay has been analyzed and compared with that of the traditional copper based interconnects. It has been observed that MWCNT based design has 3.4% less delay in the critical path as compared to the copper based design. The paper also describes a methodology of modeling and analyzing a system designed with MWCNT interconnects, using the conventional chip design flow and tools.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117032022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present the design of "e-SURAKSHAK," a novel cyber-physical health care management system of Wireless Embedded Internet Devices (WEIDs) that sense vital health parameters. The system is capable of sensing body temperature, heart rate, oxygen saturation level and also allows noninvasive blood pressure (NIBP) measurement. End to end internet connectivity is provided by using 6LoWPAN based wireless network that uses the 802.15.4 radio. A service oriented architecture (SOA) [1] is implemented to extract meaningful information and present it in an easy-to-understand form to the end-user instead of raw data made available by sensors. A central electronic database and health care management software are developed. Vital health parameters are measured and stored periodically in the database. Further, support for real-time measurement of health parameters is provided through a web based GUI. The system has been implemented completely and demonstrated with multiple users and multiple WEIDs.
{"title":"e-SURAKSHAK: A Cyber-Physical Healthcare System with Service Oriented Architecture","authors":"I. H. Rao, N. A. Amir, Haresh Dagale, J. Kuri","doi":"10.1109/ISED.2012.66","DOIUrl":"https://doi.org/10.1109/ISED.2012.66","url":null,"abstract":"In this paper we present the design of \"e-SURAKSHAK,\" a novel cyber-physical health care management system of Wireless Embedded Internet Devices (WEIDs) that sense vital health parameters. The system is capable of sensing body temperature, heart rate, oxygen saturation level and also allows noninvasive blood pressure (NIBP) measurement. End to end internet connectivity is provided by using 6LoWPAN based wireless network that uses the 802.15.4 radio. A service oriented architecture (SOA) [1] is implemented to extract meaningful information and present it in an easy-to-understand form to the end-user instead of raw data made available by sensors. A central electronic database and health care management software are developed. Vital health parameters are measured and stored periodically in the database. Further, support for real-time measurement of health parameters is provided through a web based GUI. The system has been implemented completely and demonstrated with multiple users and multiple WEIDs.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131277527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sagar Mukherjee, Dipankar Saha, P. Mostafa, S. Chatterjee, C. Sarkar
In this paper the implementation of a low power high speed 4-bit Binary Search ADC (BS-ADC) is reported using 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is introduced as a modification of the latch-based conventional comparators. The reported structure of the ADC occupies an active area of 0.0157 mm2 and consumes 127 μW of average power while operating with an input frequency (fin) of 5 MHZ, and a supply voltage of 1.8Volt. For this proposed architecture, the maximum sampling rate is obtained as 0.2 GSPS. At 0.2 GSPS sampling rate, the Signal to Noise plus Distortion Ratio (SNDR) is found to be 20.84 dB, yielding the Effective Number of Bits (ENOB) as 3.2 bit.
{"title":"A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications","authors":"Sagar Mukherjee, Dipankar Saha, P. Mostafa, S. Chatterjee, C. Sarkar","doi":"10.1109/ISED.2012.18","DOIUrl":"https://doi.org/10.1109/ISED.2012.18","url":null,"abstract":"In this paper the implementation of a low power high speed 4-bit Binary Search ADC (BS-ADC) is reported using 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is introduced as a modification of the latch-based conventional comparators. The reported structure of the ADC occupies an active area of 0.0157 mm2 and consumes 127 μW of average power while operating with an input frequency (fin) of 5 MHZ, and a supply voltage of 1.8Volt. For this proposed architecture, the maximum sampling rate is obtained as 0.2 GSPS. At 0.2 GSPS sampling rate, the Signal to Noise plus Distortion Ratio (SNDR) is found to be 20.84 dB, yielding the Effective Number of Bits (ENOB) as 3.2 bit.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128411194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently cognitive radios have been proposed to mitigate the problem of spectrum scarcity and spectrum under-utilization. One of the key aspect of the cognitive radio is the optimal channel selection. The cognitive radio system selects a licensed band which has acceptable availability and also satisfies the system needs in terms of bandwidth and power constraints. To this end we propose an energy aware spectrum decision framework for cognitive radio network (ESDF-CR), which guarantees a certain level of QoS to the system running on low power, by selecting those channels which require lesser power for transmission. Channel selection and packet admission control techniques have been proposed to realize the spectrum decision framework. A comparison is done with random channel selection scheme to show the effectiveness of the proposed framework.
{"title":"Energy Aware Spectrum Decision Framework for Cognitive Radio Networks","authors":"V. Mishra, C. Lau, Syin Chan, Ashish Kumar","doi":"10.1109/ISED.2012.65","DOIUrl":"https://doi.org/10.1109/ISED.2012.65","url":null,"abstract":"Recently cognitive radios have been proposed to mitigate the problem of spectrum scarcity and spectrum under-utilization. One of the key aspect of the cognitive radio is the optimal channel selection. The cognitive radio system selects a licensed band which has acceptable availability and also satisfies the system needs in terms of bandwidth and power constraints. To this end we propose an energy aware spectrum decision framework for cognitive radio network (ESDF-CR), which guarantees a certain level of QoS to the system running on low power, by selecting those channels which require lesser power for transmission. Channel selection and packet admission control techniques have been proposed to realize the spectrum decision framework. A comparison is done with random channel selection scheme to show the effectiveness of the proposed framework.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121316429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sukanta Bhattacharjee, A. Banerjee, B. Bhattacharya
Digital microfluidic (DMF) biochips offer a versatile platform for implementing several laboratory based biochemical protocols. These tiny chips can electrically control the dynamics of nanoliter volume of discrete fluid droplets on an electrode array with desired actuation patterns. One important step in biochemical sample preparation is dilution, where the objective is to prepare a fluid with a desired concentration factor. Bioassays implemented on DMF biochips may require several different concentration values of the same sample. In this paper, we propose a scheme in which a set of different target droplets (target concentration values ranged between 0% and 100%) can be produced using 0% concentration (buffer solution) and 100% concentration (sample/reagent), with an error bounded above by 1/2^(n+1) where concentration values are rounded-off by an n-bit binary fraction. Simulation results show that significant amount of savings in the number of mix-split steps and waste droplets can be achieved in comparison with the repeated use of existing single target based methods for generating multiple concentration factors.
{"title":"Multiple Dilution Sample Preparation Using Digital Microfluidic Biochips","authors":"Sukanta Bhattacharjee, A. Banerjee, B. Bhattacharya","doi":"10.1109/ISED.2012.73","DOIUrl":"https://doi.org/10.1109/ISED.2012.73","url":null,"abstract":"Digital microfluidic (DMF) biochips offer a versatile platform for implementing several laboratory based biochemical protocols. These tiny chips can electrically control the dynamics of nanoliter volume of discrete fluid droplets on an electrode array with desired actuation patterns. One important step in biochemical sample preparation is dilution, where the objective is to prepare a fluid with a desired concentration factor. Bioassays implemented on DMF biochips may require several different concentration values of the same sample. In this paper, we propose a scheme in which a set of different target droplets (target concentration values ranged between 0% and 100%) can be produced using 0% concentration (buffer solution) and 100% concentration (sample/reagent), with an error bounded above by 1/2^(n+1) where concentration values are rounded-off by an n-bit binary fraction. Simulation results show that significant amount of savings in the number of mix-split steps and waste droplets can be achieved in comparison with the repeated use of existing single target based methods for generating multiple concentration factors.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116776135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rajdeep Mukherjee, Priyankar Ghosh, N. Kumar, P. Dasgupta, A. Pal
There has been a renewed interest in the operator scheduling problem due to the down-scaling trend of CMOS technology and the increasing adoption of the fine-grained power management at the level of individual functional unit. Traditionally branch-and-bound has been a popular choice for determining the pareto-optimal frontier with respect to area and power under certain user constraints. In this paper we explore the scope of parallelism within the branch-and-bound(B/B) algorithm for control and data-flow intensive circuits in order to address the scalability issue. The scheduling also aims at maximum conditional and unconditional resource sharing and is able to attain sufficient area and power gains for complex benchmarks under strict and relaxed timing constraints. Experimental results reveals that the distributed framework is able to parallelize the search space uniformly and is able to achieve promising speedup compared to the serial B/B counterpart.
{"title":"Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework","authors":"Rajdeep Mukherjee, Priyankar Ghosh, N. Kumar, P. Dasgupta, A. Pal","doi":"10.1109/ISED.2012.51","DOIUrl":"https://doi.org/10.1109/ISED.2012.51","url":null,"abstract":"There has been a renewed interest in the operator scheduling problem due to the down-scaling trend of CMOS technology and the increasing adoption of the fine-grained power management at the level of individual functional unit. Traditionally branch-and-bound has been a popular choice for determining the pareto-optimal frontier with respect to area and power under certain user constraints. In this paper we explore the scope of parallelism within the branch-and-bound(B/B) algorithm for control and data-flow intensive circuits in order to address the scalability issue. The scheduling also aims at maximum conditional and unconditional resource sharing and is able to attain sufficient area and power gains for complex benchmarks under strict and relaxed timing constraints. Experimental results reveals that the distributed framework is able to parallelize the search space uniformly and is able to achieve promising speedup compared to the serial B/B counterpart.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114178541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Connecting different Intellectual Property (IP) cores with Network on Chip (NoC) router using Network Interface (NI) is a challenging task due to its asynchronous nature and data width. In this paper, a generic high-speed Network Interface for Network on Chip using Ping Pong Buffers is proposed in order to ensure the seamless high throughput between the router and processing core. The proposed scheme uses simple control logic to handle the read and write operations simultaneously in the memory modules. This proposed method is analyzed with the existing Asynchronous First in First Out (FIFO) based NIs with different encoding schemes like One-Hot encoding and Johnson encoding. The optimal depth of the asynchronous FIFOs is calculated based on router frequency, processing element frequency, packet size and flit size at router and processing element using Practical Extraction and Report Language (PERL) and the required Register Transfer Level (RTL) Verilog Hardware Description Language (HDL) and timing constrain is created by Perl scripting itself. The NI is implemented using the asynchronous FIFOs and ping pong - double buffering scheme using Altera Stratix III FPGA. The synthesis results show that the proposed architecture enhances the speed of NI by 30 % when memory depth is 8 and enhances speed by 11% when memory depth is 256.
由于网络接口(NI)的异步特性和数据宽度，使用网络接口(NI)将不同的知识产权(IP)内核与片上网络(NoC)路由器连接是一项具有挑战性的任务。为了保证路由器与处理核心之间的无缝高吞吐量，本文提出了一种基于乒乓缓冲的通用高速片上网络接口。该方案使用简单的控制逻辑来同时处理内存模块中的读和写操作。该方法与现有的基于异步先进先出(FIFO)的NIs进行了分析，并采用了One-Hot编码和Johnson编码等不同的编码方案。异步fifo的最佳深度是基于路由器频率、处理单元频率、数据包大小和路由器上的flit大小计算的，处理单元使用实用提取和报告语言(PERL)和所需的寄存器传输级别(RTL) Verilog硬件描述语言(HDL)，时间约束由PERL脚本本身创建。采用Altera Stratix III FPGA实现异步fifo和乒乓双缓冲方案。综合结果表明，当存储深度为8时，该架构可将NI速度提高30%，当存储深度为256时，该架构可将NI速度提高11%。
{"title":"High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers","authors":"K. Swaminathan, G. Lakshminarayanan, S. Ko","doi":"10.1109/ISED.2012.11","DOIUrl":"https://doi.org/10.1109/ISED.2012.11","url":null,"abstract":"Connecting different Intellectual Property (IP) cores with Network on Chip (NoC) router using Network Interface (NI) is a challenging task due to its asynchronous nature and data width. In this paper, a generic high-speed Network Interface for Network on Chip using Ping Pong Buffers is proposed in order to ensure the seamless high throughput between the router and processing core. The proposed scheme uses simple control logic to handle the read and write operations simultaneously in the memory modules. This proposed method is analyzed with the existing Asynchronous First in First Out (FIFO) based NIs with different encoding schemes like One-Hot encoding and Johnson encoding. The optimal depth of the asynchronous FIFOs is calculated based on router frequency, processing element frequency, packet size and flit size at router and processing element using Practical Extraction and Report Language (PERL) and the required Register Transfer Level (RTL) Verilog Hardware Description Language (HDL) and timing constrain is created by Perl scripting itself. The NI is implemented using the asynchronous FIFOs and ping pong - double buffering scheme using Altera Stratix III FPGA. The synthesis results show that the proposed architecture enhances the speed of NI by 30 % when memory depth is 8 and enhances speed by 11% when memory depth is 256.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114488126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design of a 6bit 125MS/s Successive Approximation (SAR) Analog to Digital Converter (ADC) that uses modified switching technique has been presented in this paper. This modified switching technique requires only half the number capacitors and achieves a switching energy reduction of about 91.5% when compared with conventional SAR ADC approach. This scheme also reduces by half the DAC capacitor array output settling time during bit cycling sequence. This SAR ADC with modified switching technique has been designed and simulated in UMC 0.13u MM/RF CMOS process. This design works with the clock frequency of 1GHz achieving a maximum sampling rate of 125MS/s and consumes 5.16mW power with 1.2V supply voltage and 800mVpp differential input range. The simulated dynamic performance indicates an SNDR and SFDR of 37.97dB and 54.35dB respectively.
{"title":"A Design of 6-bit 125-MS/s SAR ADC in 0.13-µm MM/RF CMOS Process","authors":"R. Rajendran, P. Ramakrishna","doi":"10.1109/ISED.2012.63","DOIUrl":"https://doi.org/10.1109/ISED.2012.63","url":null,"abstract":"The design of a 6bit 125MS/s Successive Approximation (SAR) Analog to Digital Converter (ADC) that uses modified switching technique has been presented in this paper. This modified switching technique requires only half the number capacitors and achieves a switching energy reduction of about 91.5% when compared with conventional SAR ADC approach. This scheme also reduces by half the DAC capacitor array output settling time during bit cycling sequence. This SAR ADC with modified switching technique has been designed and simulated in UMC 0.13u MM/RF CMOS process. This design works with the clock frequency of 1GHz achieving a maximum sampling rate of 125MS/s and consumes 5.16mW power with 1.2V supply voltage and 800mVpp differential input range. The simulated dynamic performance indicates an SNDR and SFDR of 37.97dB and 54.35dB respectively.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"451 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116075170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design of through-Silicon-Via (TSV) based 3D IC is became feasible recently. Testing of TSVs is an important issue in this respect. It is a challenge to test the TSVs before the bonding of different layers so that the manufacturing defects of TSV can be identified properly. In this paper, we are trying to test the TSVs before bonding. Here we have proposed a heuristic algorithm to locate the faulty TSVs uniquely and at the same time it reduces the test time significantly for locating those faulty TSVs. Simulation results how that our algorithm achieved up to on an average 33% reduction in test time for a 20 TSV network than serial testing approach. Our algorithm also performs better in terms of est time reduction than the previous work present in the literature.
{"title":"Identifying Faulty TSVs in 3D Stacked IC during Pre-bond Testing","authors":"S. Roy, S. Chatterjee, C. Giri","doi":"10.1109/ISED.2012.49","DOIUrl":"https://doi.org/10.1109/ISED.2012.49","url":null,"abstract":"Design of through-Silicon-Via (TSV) based 3D IC is became feasible recently. Testing of TSVs is an important issue in this respect. It is a challenge to test the TSVs before the bonding of different layers so that the manufacturing defects of TSV can be identified properly. In this paper, we are trying to test the TSVs before bonding. Here we have proposed a heuristic algorithm to locate the faulty TSVs uniquely and at the same time it reduces the test time significantly for locating those faulty TSVs. Simulation results how that our algorithm achieved up to on an average 33% reduction in test time for a 20 TSV network than serial testing approach. Our algorithm also performs better in terms of est time reduction than the previous work present in the literature.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114792132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper a high performance signal stepping based multimode multi-threshold CMOS technique is introduced which reduces standby leakage current and provides a better way to control the ground bounce noise during sleep to active mode transition using one additional mode i.e. wait mode. Analysis of signal stepping based multimode multi-threshold CMOS technique using low power 16-bit full adder has been done for reduction of standby leakage current and ground bounce noise. Further, to see the effectiveness of signal stepping based multimode multi-threshold CMOS technique, simulation has been done for low power 16 bit full adder in BPTM 90nm technology with supply voltage of 1V at room temperature. Results show that this technique reduces ground bounce noise by 95.80 % and standby leakage current by 19.24% as compared to the standard trimode MTCMOS technique.
{"title":"Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders","authors":"Shashikant Sharma, M. Pattanaik, B. Raj","doi":"10.1109/ISED.2012.14","DOIUrl":"https://doi.org/10.1109/ISED.2012.14","url":null,"abstract":"In this paper a high performance signal stepping based multimode multi-threshold CMOS technique is introduced which reduces standby leakage current and provides a better way to control the ground bounce noise during sleep to active mode transition using one additional mode i.e. wait mode. Analysis of signal stepping based multimode multi-threshold CMOS technique using low power 16-bit full adder has been done for reduction of standby leakage current and ground bounce noise. Further, to see the effectiveness of signal stepping based multimode multi-threshold CMOS technique, simulation has been done for low power 16 bit full adder in BPTM 90nm technology with supply voltage of 1V at room temperature. Results show that this technique reduces ground bounce noise by 95.80 % and standby leakage current by 19.24% as compared to the standard trimode MTCMOS technique.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"11 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126318938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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