High speed adders are very important in computer arithmetic such that a small improvement in the performance of adders has a great impact on other operations. A way to speed up the adders is to eliminate carry propagation by using carry-free adders. In this paper we improve the fastest previous carry-free adder by changing the transfer digit-set to [-2,1]. It is shown that this small change leads to a simpler signed-digit adder which consumes lower area/power than the fastest previous work while not increasing the latency.
{"title":"Improved Design of High-Radix Signed-Digit Adders","authors":"F. Naderpour, S. Ko","doi":"10.1109/ISED.2012.10","DOIUrl":"https://doi.org/10.1109/ISED.2012.10","url":null,"abstract":"High speed adders are very important in computer arithmetic such that a small improvement in the performance of adders has a great impact on other operations. A way to speed up the adders is to eliminate carry propagation by using carry-free adders. In this paper we improve the fastest previous carry-free adder by changing the transfer digit-set to [-2,1]. It is shown that this small change leads to a simpler signed-digit adder which consumes lower area/power than the fastest previous work while not increasing the latency.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"90 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134162600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel value propagation based equivalence checking method of finite state machines with datapath (FSMDs) is presented here for validation of code motion transformations commonly applied during scheduling phase of high-level synthesis. Unlike many other reported techniques, our method is able to handle code motions across loop bodies. This is accomplished by repeated propagation of the mismatched values to subsequent paths until the values match or the final path segments are traversed without finding a match. Checking loop invariance of the values being propagated beyond the loops has been underlined to play an important role. The proposed method is capable of handling control structure modification as well. The method has been implemented and satisfactorily tested for some benchmark examples.
{"title":"A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques","authors":"K. Banerjee, C. Karfa, D. Sarkar, C. Mandal","doi":"10.1109/ISED.2012.28","DOIUrl":"https://doi.org/10.1109/ISED.2012.28","url":null,"abstract":"A novel value propagation based equivalence checking method of finite state machines with datapath (FSMDs) is presented here for validation of code motion transformations commonly applied during scheduling phase of high-level synthesis. Unlike many other reported techniques, our method is able to handle code motions across loop bodies. This is accomplished by repeated propagation of the mismatched values to subsequent paths until the values match or the final path segments are traversed without finding a match. Checking loop invariance of the values being propagated beyond the loops has been underlined to play an important role. The proposed method is capable of handling control structure modification as well. The method has been implemented and satisfactorily tested for some benchmark examples.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134420404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Sivanantham, K. Sarathkumar, J. Manuel, P. Mallick, J. Perinbam
In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1's or 0's using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS'89 benchmark circuits show that, the CSP - filling technique provides a significant reduction in both shift and capture transitions in test mode.
{"title":"CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications","authors":"S. Sivanantham, K. Sarathkumar, J. Manuel, P. Mallick, J. Perinbam","doi":"10.1109/ISED.2012.62","DOIUrl":"https://doi.org/10.1109/ISED.2012.62","url":null,"abstract":"In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1's or 0's using the proposed don't care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS'89 benchmark circuits show that, the CSP - filling technique provides a significant reduction in both shift and capture transitions in test mode.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132995279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advent of digital technologies, the pseudo LFM digital radar using polyphase code is gaining popularity as compared to once popular Analog LFM Radar. Benefits include improved target detection and avoidance of channel impairments by exploiting the higher processing gain of Polyphase codes. In this paper attempt has been made towards realizing such high performance spread spectrum radar. Latest equipments including AWG, VSG, and VSA are used for the realization. By eliminating channel impairments, the detectability of the target is extended towards target imaging which would lead to target classification.
{"title":"Improvement in Target Detectability Using Spread Spectrum Radar in Dispersive Channel Condition","authors":"S. Bera, A. Singh, S. Sur, D. Bhaskar, R. Bera","doi":"10.1109/ISED.2012.30","DOIUrl":"https://doi.org/10.1109/ISED.2012.30","url":null,"abstract":"With the advent of digital technologies, the pseudo LFM digital radar using polyphase code is gaining popularity as compared to once popular Analog LFM Radar. Benefits include improved target detection and avoidance of channel impairments by exploiting the higher processing gain of Polyphase codes. In this paper attempt has been made towards realizing such high performance spread spectrum radar. Latest equipments including AWG, VSG, and VSA are used for the realization. By eliminating channel impairments, the detectability of the target is extended towards target imaging which would lead to target classification.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"710 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114361035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The data coherence in the cache systems of CMPs (Chip Multi-Processors) is to be more accurate and reliable. In this work, we propose an effective solution to the issue through introduction of highly efficient test logic (fault detection unit). The test design is based on the modular structure of Cellular Automata (CA). The SACA (single length single cycle attractor cellular automata) has been introduced to identify the inconsistencies in cache line states of processors' private caches realizing the MOESI protocol. The simple hardware implementation of the CA based design realizes quick decision on the cache coherency in CMPs with 100% accuracy.
{"title":"A Test Design for Quick Determination of Incoherency in Chip Multiprocessors' Cache Realizing MOESI Protocol","authors":"M. Dalui, B. Sikdar","doi":"10.1109/ISED.2012.67","DOIUrl":"https://doi.org/10.1109/ISED.2012.67","url":null,"abstract":"The data coherence in the cache systems of CMPs (Chip Multi-Processors) is to be more accurate and reliable. In this work, we propose an effective solution to the issue through introduction of highly efficient test logic (fault detection unit). The test design is based on the modular structure of Cellular Automata (CA). The SACA (single length single cycle attractor cellular automata) has been introduced to identify the inconsistencies in cache line states of processors' private caches realizing the MOESI protocol. The simple hardware implementation of the CA based design realizes quick decision on the cache coherency in CMPs with 100% accuracy.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116192140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The variations of March tests are extensively used for functional test of SRAMs and DRAMs. This work proposes hardware realization of March C- to enable efficient fault detection in memories. The properties of single length cycle attractor cellular automata are exploited to memorize the status (faulty/non-faulty) of memory words during read (r0/r1) operation of the March C- algorithm. It effectively reduces the overhead of comparison that is required in a conventional test structure, to take decision on the faults in memory.
{"title":"High Speed Hardware for March C¯","authors":"M. Saha, Souvik Das, B. Sikdar","doi":"10.1109/ISED.2012.56","DOIUrl":"https://doi.org/10.1109/ISED.2012.56","url":null,"abstract":"The variations of March tests are extensively used for functional test of SRAMs and DRAMs. This work proposes hardware realization of March C- to enable efficient fault detection in memories. The properties of single length cycle attractor cellular automata are exploited to memorize the status (faulty/non-faulty) of memory words during read (r0/r1) operation of the March C- algorithm. It effectively reduces the overhead of comparison that is required in a conventional test structure, to take decision on the faults in memory.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121989541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Improvements of the Elliptic Curve Cryptosystem (ECC) point multiplication processor is presented in this paper. The main contributions of this paper are the improved finite field multiplier, which uses a 2-stage Karatsuba-Ofman multiplier architecture. Furthermore, a revised algorithm is proposed for the projective to affine coordinate conversion, which computes 2 inversion operations simultaneously with the numerator portion, in order to make better use of parallel cores implemented in the ECC processor. The design is implemented on a Virtex 4 XC4VLX80 FPGA and the implementation results show that the ECC processor can compute a point multiplication in 6.72 us. This time is the fastest to the authors' best knowledge. Thus, the ECC processor proposed in this paper is suitable for applications where high-throughput is required, such as network servers.
{"title":"Improvements for High Performance Elliptic Curve Cryptosystem Processor over GF(2^163)","authors":"K. C. C. Loi, S. Ko","doi":"10.1109/ISED.2012.15","DOIUrl":"https://doi.org/10.1109/ISED.2012.15","url":null,"abstract":"Improvements of the Elliptic Curve Cryptosystem (ECC) point multiplication processor is presented in this paper. The main contributions of this paper are the improved finite field multiplier, which uses a 2-stage Karatsuba-Ofman multiplier architecture. Furthermore, a revised algorithm is proposed for the projective to affine coordinate conversion, which computes 2 inversion operations simultaneously with the numerator portion, in order to make better use of parallel cores implemented in the ECC processor. The design is implemented on a Virtex 4 XC4VLX80 FPGA and the implementation results show that the ECC processor can compute a point multiplication in 6.72 us. This time is the fastest to the authors' best knowledge. Thus, the ECC processor proposed in this paper is suitable for applications where high-throughput is required, such as network servers.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127786726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes the design of Hysteresis Current Controller (HCC) for a single-phase Hybrid Active Power Filter (HAPF) using Simulink and Xilinx System Generator as a design platform. At the present age, elimination of harmonics produced by the nonlinear loads to improve the power quality is a great issue. To overcome the problem due to harmonics, Active Power Filters (APFs) are used with various control schemes. But Hybrid Active power filter is a power electronic device which has both the characteristics of passive power filters and active power filters, helps in cancelation of the harmonics by producing compensating signal. The digital controller design and its simulation are presented, showing acceptable THD results for the word length used in the fixed-point computations involved in the switching sequence generation.
本文介绍了采用Simulink和Xilinx System Generator作为设计平台，设计单相混合有源电力滤波器(HAPF)的磁滞电流控制器(HCC)。消除非线性负载产生的谐波以改善电能质量是当前的一个重大问题。为了克服谐波问题，有源电力滤波器(apf)被用于各种控制方案。而混合有源电力滤波器是一种兼具无源电力滤波器和有源电力滤波器特性的电力电子器件，它通过产生补偿信号来抵消谐波。提出了数字控制器的设计及其仿真，显示了在切换序列生成中涉及的定点计算中使用的字长可接受的THD结果。
{"title":"Analysis and Operation of FPGA-based Hybrid Active Power Filter for Harmonic Elimination in a Distribution System","authors":"G. Panda, Santanu Kumar Dash, N. Sahoo","doi":"10.1109/ISED.2012.32","DOIUrl":"https://doi.org/10.1109/ISED.2012.32","url":null,"abstract":"This paper describes the design of Hysteresis Current Controller (HCC) for a single-phase Hybrid Active Power Filter (HAPF) using Simulink and Xilinx System Generator as a design platform. At the present age, elimination of harmonics produced by the nonlinear loads to improve the power quality is a great issue. To overcome the problem due to harmonics, Active Power Filters (APFs) are used with various control schemes. But Hybrid Active power filter is a power electronic device which has both the characteristics of passive power filters and active power filters, helps in cancelation of the harmonics by producing compensating signal. The digital controller design and its simulation are presented, showing acceptable THD results for the word length used in the fixed-point computations involved in the switching sequence generation.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126414497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Papia Manna, D. Kole, H. Rahaman, D. K. Das, B. Bhattacharya
We propose two population-based search techniques for synthesizing reversible circuits. Given a reversible specification of a circuit, the algorithms produce a network of Toffoli gates for its realization, which is competitive in terms of the number of gates and quantum cost compared to earlier designs. Synthesis of several reversible circuits was studied to evaluate the proposed methods. Experimental results are indicative of encouraging performance with respect to cost and time of synthesis.
{"title":"Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization","authors":"Papia Manna, D. Kole, H. Rahaman, D. K. Das, B. Bhattacharya","doi":"10.1109/ISED.2012.71","DOIUrl":"https://doi.org/10.1109/ISED.2012.71","url":null,"abstract":"We propose two population-based search techniques for synthesizing reversible circuits. Given a reversible specification of a circuit, the algorithms produce a network of Toffoli gates for its realization, which is competitive in terms of the number of gates and quantum cost compared to earlier designs. Synthesis of several reversible circuits was studied to evaluate the proposed methods. Experimental results are indicative of encouraging performance with respect to cost and time of synthesis.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126607388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fast context independent HV partitioning scheme for fractal image compression technique of grey scale images is proposed. The proposed partitioning scheme partitions middle of range either horizontally or vertically to create to sub-ranges if the range is not covered well by any domain. The decision to select one of the two possibilities i.e. horizontal or vertical partitioning is done only by a simple checking which side of the range is larger than the other. It does not depend on the context of the range to compute the partitioning point that speed up the partitioning. One variant of the same is also proposed where the decision to select one of the two sides of range is done by computing the pixel value differences of the middle vertical lines and the middle horizontal lines and determining which is greater than other. The fractal image compression for grey scale image with the proposed partitioning schemes offer better compression rates than the quadtree partitioning scheme maintaining almost same compression times with improved PSNRs. Though the compression rates are not as well as offered by HV partitioning scheme, the proposed schemes are much faster than the same.
{"title":"Fractal Image Compression Using Fast Context Independent HV Partitioning Scheme","authors":"U. Nandi, Jyotsna Kumar Mandal","doi":"10.1109/ISED.2012.13","DOIUrl":"https://doi.org/10.1109/ISED.2012.13","url":null,"abstract":"A fast context independent HV partitioning scheme for fractal image compression technique of grey scale images is proposed. The proposed partitioning scheme partitions middle of range either horizontally or vertically to create to sub-ranges if the range is not covered well by any domain. The decision to select one of the two possibilities i.e. horizontal or vertical partitioning is done only by a simple checking which side of the range is larger than the other. It does not depend on the context of the range to compute the partitioning point that speed up the partitioning. One variant of the same is also proposed where the decision to select one of the two sides of range is done by computing the pixel value differences of the middle vertical lines and the middle horizontal lines and determining which is greater than other. The fractal image compression for grey scale image with the proposed partitioning schemes offer better compression rates than the quadtree partitioning scheme maintaining almost same compression times with improved PSNRs. Though the compression rates are not as well as offered by HV partitioning scheme, the proposed schemes are much faster than the same.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124038544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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