Pub Date : 2008-01-21DOI: 10.1109/ASPDAC.2008.4483982
T. Nakagawa, M. Miyazaki, G. Ono, R. Fujiwara, T. Norimatsu, T. Terada, A. Maeki, Y. Ogata, Shinsuke Kobayashi, N. Koshizuka, K. Sakamura
An ultra-small, high-data-rate, low-power 1-cc computer (OCCC) with an UWB-IR (ultra-wideband impulse-radio) transceiver was developed for a wireless sensor network. Thanks to bear-chip implementation and a flexible printed circuit board, the size of the computer is only 1 cm3. To achieve 10-Mbps data rate, a middle-class 32-bit microcontroller, which has both a bus interface and a USB 2.0 controller, was selected. Low-power techniques, such as transition of microcontroller status to standby mode by using an external real-time clock during wait times, power shutdown of halted circuits, and detailed control of UWB-IR transceiver status, are applied. The effect of these low-power techniques is verified by measuring the time history of current consumption of the OCCC. It was confirmed that the OCCC can provide wireless communication at a transmission rate of 258 kbps over a distance of 30 m.
{"title":"1-cc computer using UWB-IR for wireless sensor network","authors":"T. Nakagawa, M. Miyazaki, G. Ono, R. Fujiwara, T. Norimatsu, T. Terada, A. Maeki, Y. Ogata, Shinsuke Kobayashi, N. Koshizuka, K. Sakamura","doi":"10.1109/ASPDAC.2008.4483982","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483982","url":null,"abstract":"An ultra-small, high-data-rate, low-power 1-cc computer (OCCC) with an UWB-IR (ultra-wideband impulse-radio) transceiver was developed for a wireless sensor network. Thanks to bear-chip implementation and a flexible printed circuit board, the size of the computer is only 1 cm3. To achieve 10-Mbps data rate, a middle-class 32-bit microcontroller, which has both a bus interface and a USB 2.0 controller, was selected. Low-power techniques, such as transition of microcontroller status to standby mode by using an external real-time clock during wait times, power shutdown of halted circuits, and detailed control of UWB-IR transceiver status, are applied. The effect of these low-power techniques is verified by measuring the time history of current consumption of the OCCC. It was confirmed that the OCCC can provide wireless communication at a transmission rate of 258 kbps over a distance of 30 m.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131714464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-21DOI: 10.1109/ASPDAC.2008.4483944
S. Nassif
The semiconductor industry is unique in that it produces products with little or no prototyping! While a car company will build (and crash) many prototypes before converging on a final design, integrated circuits are built almost entirely on a basis of computer predictions. These predictions are based on models of performance based on simulation performed at multiple hierarchical levels, but always rooted in the end in classical circuit simulation using tools like the venerable Spice [1]. But as we continue to scale technology further, we observe a diminishing rate of performance return which is in turn causing a spiral of increasing manufacturing process complexity in an attempt to maintain performance per historical trends. This increase in technology complexity is introducing a number of systematic (i.e. design dependent) sources of design variability which demand modeling and characterization resources. At the same time, we are entering a regime where the averaging effect of the law of large numbers is becoming weaker, resulting in an increase in influence of fundamental atomistic variations. Phenomena like channel dopant fluctuations [2] and line-edge roughness [3] are creating a random variability noise floor which is difficult to get around without significant process impact. The result of the increase in these, and other sources of variability is a corresponding increase in important circuit phenomena like SRAM stability and leakage power variations. The net result is a gradual breakdown of the traditional ";device model + design rule"; contact between design and manufacturing, and a corresponding lack of predictability in fabrication outcome that is endangering the profitability of Silicon semiconductor manufacturing as we enter what may be the last handful of generations of CMOS. This lack of predictability is happening because of two important factors. ldr The overall CMOS technology slowdown has led to rapidly increasing complexity in the process and in its interaction with design. This has in turn caused an increase in the number and magnitude of systematic sources of mismatch between simulation models (both at the circuit simulation and timing levels) and hardware measurements. ldr Manufacturing variability, both systematic and random, -long a source of concern only for analog design- is becoming important for digital designs as well and thus its prediction is now a first order priority. However, it is competing for the attention of researchers and CAD developers with a host of other so-called nm effects, thus slowing down the delivery of needed solutions. The result is (a) our ability to arbitrarily compose a design out of disparate components is compromised because of a high degree of interaction between these components , and (b) our ability to predict the nominal performance of a design as well as its tolerances and sensitivities is in danger. In this talk, we will review these issues and show how they are all related to the cor
{"title":"Technology modeling and characterization beyond the 45nm node","authors":"S. Nassif","doi":"10.1109/ASPDAC.2008.4483944","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483944","url":null,"abstract":"The semiconductor industry is unique in that it produces products with little or no prototyping! While a car company will build (and crash) many prototypes before converging on a final design, integrated circuits are built almost entirely on a basis of computer predictions. These predictions are based on models of performance based on simulation performed at multiple hierarchical levels, but always rooted in the end in classical circuit simulation using tools like the venerable Spice [1]. But as we continue to scale technology further, we observe a diminishing rate of performance return which is in turn causing a spiral of increasing manufacturing process complexity in an attempt to maintain performance per historical trends. This increase in technology complexity is introducing a number of systematic (i.e. design dependent) sources of design variability which demand modeling and characterization resources. At the same time, we are entering a regime where the averaging effect of the law of large numbers is becoming weaker, resulting in an increase in influence of fundamental atomistic variations. Phenomena like channel dopant fluctuations [2] and line-edge roughness [3] are creating a random variability noise floor which is difficult to get around without significant process impact. The result of the increase in these, and other sources of variability is a corresponding increase in important circuit phenomena like SRAM stability and leakage power variations. The net result is a gradual breakdown of the traditional \";device model + design rule\"; contact between design and manufacturing, and a corresponding lack of predictability in fabrication outcome that is endangering the profitability of Silicon semiconductor manufacturing as we enter what may be the last handful of generations of CMOS. This lack of predictability is happening because of two important factors. ldr The overall CMOS technology slowdown has led to rapidly increasing complexity in the process and in its interaction with design. This has in turn caused an increase in the number and magnitude of systematic sources of mismatch between simulation models (both at the circuit simulation and timing levels) and hardware measurements. ldr Manufacturing variability, both systematic and random, -long a source of concern only for analog design- is becoming important for digital designs as well and thus its prediction is now a first order priority. However, it is competing for the attention of researchers and CAD developers with a host of other so-called nm effects, thus slowing down the delivery of needed solutions. The result is (a) our ability to arbitrarily compose a design out of disparate components is compromised because of a high degree of interaction between these components , and (b) our ability to predict the nominal performance of a design as well as its tolerances and sensitivities is in danger. In this talk, we will review these issues and show how they are all related to the cor","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129572803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-21DOI: 10.1109/ASPDAC.2008.4483959
Takayuki Fukuoka, A. Tsuchiya, H. Onodera
In this paper, we propose a calculation method of gate delay for SSTA (Statistical Static Timing Analysis) considering MIS (Multiple Input Switching). Most SSTA approaches assume a single input switching model and ignore the effect of MIS on gate delay. MIS occurs when multiple inputs of a gate switch nearly simultaneously. Thus, ignoring MIS causes error in MAX operation in SSTA. We propose a statistical gate delay model considering MIS. We verify the proposed method by SPICE based Monte Carlo simulations and experimental results show that the proposed method improves the error due to ignoring MIS.
{"title":"Statistical gate delay model for Multiple Input Switching","authors":"Takayuki Fukuoka, A. Tsuchiya, H. Onodera","doi":"10.1109/ASPDAC.2008.4483959","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483959","url":null,"abstract":"In this paper, we propose a calculation method of gate delay for SSTA (Statistical Static Timing Analysis) considering MIS (Multiple Input Switching). Most SSTA approaches assume a single input switching model and ignore the effect of MIS on gate delay. MIS occurs when multiple inputs of a gate switch nearly simultaneously. Thus, ignoring MIS causes error in MAX operation in SSTA. We propose a statistical gate delay model considering MIS. We verify the proposed method by SPICE based Monte Carlo simulations and experimental results show that the proposed method improves the error due to ignoring MIS.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132143205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-21DOI: 10.1109/ASPDAC.2008.4484059
S. Pasricha, N. Dutt
As application complexity continues to increase, multiprocessor systems-on-chip (MPSoC) with tens to hundreds of processing cores are becoming the norm. While computational cores have become faster with each successive technology generation, communication between them has become a bottleneck that limits overall chip performance. On-chip optical interconnects can overcome this bottleneck by replacing electrical wires with optical waveguides. In this paper we propose an optical ring bus (ORB) based on-chip communication architecture for next generation MPSoCs. ORB uses an optical ring waveguide to replace global pipelined electrical interconnects while preserving the interface with today's bus protocol standards such as AMBA AXI. We present experiments to show how ORB has the potential to provide superior performance (more than 2times) and significantly lower power consumption (a reduction of more than 10times) compared to traditionally used pipelined, all-electrical bus-based communication architectures, for 65-22 nm technology nodes.
{"title":"ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip","authors":"S. Pasricha, N. Dutt","doi":"10.1109/ASPDAC.2008.4484059","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484059","url":null,"abstract":"As application complexity continues to increase, multiprocessor systems-on-chip (MPSoC) with tens to hundreds of processing cores are becoming the norm. While computational cores have become faster with each successive technology generation, communication between them has become a bottleneck that limits overall chip performance. On-chip optical interconnects can overcome this bottleneck by replacing electrical wires with optical waveguides. In this paper we propose an optical ring bus (ORB) based on-chip communication architecture for next generation MPSoCs. ORB uses an optical ring waveguide to replace global pipelined electrical interconnects while preserving the interface with today's bus protocol standards such as AMBA AXI. We present experiments to show how ORB has the potential to provide superior performance (more than 2times) and significantly lower power consumption (a reduction of more than 10times) compared to traditionally used pipelined, all-electrical bus-based communication architectures, for 65-22 nm technology nodes.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129394749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-21DOI: 10.1109/ASPDAC.2008.4484016
Yu Hu, Xiang Fu, Xiaoxin Fan, H. Fujiwara
Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead.
{"title":"Localized random access scan: Towards low area and routing overhead","authors":"Yu Hu, Xiang Fu, Xiaoxin Fan, H. Fujiwara","doi":"10.1109/ASPDAC.2008.4484016","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484016","url":null,"abstract":"Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134276666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-21DOI: 10.1109/ASPDAC.2008.4483995
Pei-Yu Huang, Chih-Kang Lin, Yu-Min Lee
The capability of predicting the temperature profile is critically important for circuit timing estimation, leakage reduction, power estimation, hotspot avoidance, and reliability concerns during modern IC designs. This paper presents an accurate and fast analytical full-chip thermal simulator for the early-stage temperature-aware chip design. By using the technique of generalized integral transforms (GIT), our proposed method can accurately estimate the temperature distribution of full-chip with very small truncation points of bases in the spatial domain. We also develop a fast Fourier transform (FFT) like evaluating algorithm to efficiently evaluate the temperature distribution. Experimental results confirm that our GIT based analyzer can achieve an order of magnitude speedup compared with a highly efficient Green's function based method.
{"title":"Full-chip thermal analysis for the early design stage via generalized integral transforms","authors":"Pei-Yu Huang, Chih-Kang Lin, Yu-Min Lee","doi":"10.1109/ASPDAC.2008.4483995","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483995","url":null,"abstract":"The capability of predicting the temperature profile is critically important for circuit timing estimation, leakage reduction, power estimation, hotspot avoidance, and reliability concerns during modern IC designs. This paper presents an accurate and fast analytical full-chip thermal simulator for the early-stage temperature-aware chip design. By using the technique of generalized integral transforms (GIT), our proposed method can accurately estimate the temperature distribution of full-chip with very small truncation points of bases in the spatial domain. We also develop a fast Fourier transform (FFT) like evaluating algorithm to efficiently evaluate the temperature distribution. Experimental results confirm that our GIT based analyzer can achieve an order of magnitude speedup compared with a highly efficient Green's function based method.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133219577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-21DOI: 10.1109/ASPDAC.2008.4483960
Pushkar Tripathi, Rohan Jain, S. Kurra, P. Panda
We propose REWIRED (register write inhibition by resource dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of function unit (FU) output data into registers. Registers are generally inferred in HLS when data produced in one clock cycle is used in a later cycle. However, when it can be established that the input registers to an FU are not changing values during a certain period, the outputs during this period can be directly read off the FU output pins without needing to store them in registers. When the life-times of such data are short, it may be possible to completely eliminate the register storage operation, thereby reducing power. We present a genetic algorithm formulation and a heuristic for maximizing the number of register stores that can be inhibited in a scheduled data flow graph (DFG) during behavioral synthesis.
{"title":"REWIRED - Register Write Inhibition by Resource Dedication","authors":"Pushkar Tripathi, Rohan Jain, S. Kurra, P. Panda","doi":"10.1109/ASPDAC.2008.4483960","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483960","url":null,"abstract":"We propose REWIRED (register write inhibition by resource dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of function unit (FU) output data into registers. Registers are generally inferred in HLS when data produced in one clock cycle is used in a later cycle. However, when it can be established that the input registers to an FU are not changing values during a certain period, the outputs during this period can be directly read off the FU output pins without needing to store them in registers. When the life-times of such data are short, it may be possible to completely eliminate the register storage operation, thereby reducing power. We present a genetic algorithm formulation and a heuristic for maximizing the number of register stores that can be inhibited in a scheduled data flow graph (DFG) during behavioral synthesis.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125851024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-21DOI: 10.1109/ASPDAC.2008.4483950
Lijuan Luo, Martin D. F. Wong
Routing for high-speed boards is largely a time-consuming manual task today. In this work we consider the ordered escape routing problem which is a key problem in board-level routing. All existing approaches to this problem cannot guarantee to find a routing solution even if one exists. We present an algorithm to exactly solve this problem based on Boolean satisfiability. Experimental results on escape routing problems from industry show that our algorithm performs well.
{"title":"Ordered escape routing based on Boolean satisfiability","authors":"Lijuan Luo, Martin D. F. Wong","doi":"10.1109/ASPDAC.2008.4483950","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483950","url":null,"abstract":"Routing for high-speed boards is largely a time-consuming manual task today. In this work we consider the ordered escape routing problem which is a key problem in board-level routing. All existing approaches to this problem cannot guarantee to find a routing solution even if one exists. We present an algorithm to exactly solve this problem based on Boolean satisfiability. Experimental results on escape routing problems from industry show that our algorithm performs well.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130243295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-21DOI: 10.1109/ASPDAC.2008.4484045
Yexin Zheng, Chao Huang
Resonant tunneling diodes (RTDs) have demonstrated promising circuit characteristics of high speed switching property and versatile functionality with negative differential resistance (NDR). In this paper, we propose novel programmable logic elements (PLEs) that can be configured to realize all three- or four-input logic functions. These simple RTD-based circuit elements are implemented with threshold gates (TGs) and multi-threshold threshold gates (MTTGs) by employing programmable monostable-bistable logic element (MOBILE) principles. We also developed a dynamically reconfigurable scheme based on our PLE structures which facilitate nanopipelining without incurring delay overheads.
{"title":"Reconfigurable RTD-based circuit elements of complete logic functionality","authors":"Yexin Zheng, Chao Huang","doi":"10.1109/ASPDAC.2008.4484045","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484045","url":null,"abstract":"Resonant tunneling diodes (RTDs) have demonstrated promising circuit characteristics of high speed switching property and versatile functionality with negative differential resistance (NDR). In this paper, we propose novel programmable logic elements (PLEs) that can be configured to realize all three- or four-input logic functions. These simple RTD-based circuit elements are implemented with threshold gates (TGs) and multi-threshold threshold gates (MTTGs) by employing programmable monostable-bistable logic element (MOBILE) principles. We also developed a dynamically reconfigurable scheme based on our PLE structures which facilitate nanopipelining without incurring delay overheads.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129971273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-21DOI: 10.1109/ASPDAC.2008.4483942
Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, J. Cong
Thermal issue is a critical challenge in 3D IC circuit design. Incorporating thermal vias into 3D IC is a promising way to mitigate thermal issues by lowering down the thermal resistances between device layers. However, it is usually difficult to get enough space at target regions to insert thermal vias. In this paper, we propose a novel analytical algorithm to re-allocate white space for 3D ICs to facilitate via insertion. Experimental results show that after reallocating whitespaces, thermal vias and total wirelength could be reduced by 14% and by 2%, respectively. It also shows that whitespace distribution with via planning alone will degrade performance by 9% while performance-aware via planning method can reduce thermal via number by 60% and the performance is kept nearly unchanged.
{"title":"LP based white space redistribution for thermal via planning and performance optimization in 3D ICs","authors":"Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, J. Cong","doi":"10.1109/ASPDAC.2008.4483942","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483942","url":null,"abstract":"Thermal issue is a critical challenge in 3D IC circuit design. Incorporating thermal vias into 3D IC is a promising way to mitigate thermal issues by lowering down the thermal resistances between device layers. However, it is usually difficult to get enough space at target regions to insert thermal vias. In this paper, we propose a novel analytical algorithm to re-allocate white space for 3D ICs to facilitate via insertion. Experimental results show that after reallocating whitespaces, thermal vias and total wirelength could be reduced by 14% and by 2%, respectively. It also shows that whitespace distribution with via planning alone will degrade performance by 9% while performance-aware via planning method can reduce thermal via number by 60% and the performance is kept nearly unchanged.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116986601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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