Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844157
Yao-Sheng Hu, Kai-Yue Lin, Hsin-Shu Chen
This paper presents an energy-efficient 12-bit 200kS/s subranging SAR ADC for multi-touch sensing applications. In order to reduce DAC power consumption, an energy-curve reshape technique is proposed to fit the switching energy curve to the characteristics of Rx signals. An auxiliary polarity quantizer joined with the well-known bottom-plate sampling not only can eliminate the gain mismatch of the subranging architecture but also can be as effective as the top-plate sampling. The ADC low-voltage operation could support the smart wake-up mode in the touch sensing system without using dual reference voltages. A pulse-type self-trigger latch technique is utilized to decrease digital loop power dissipation in the low-voltage environment. This ADC consumes 0.95 μW at 200kS/s under a 0.7V supply in 40nm CMOS technology. It achieves an SNDR of 69.24dB at Nyquist rate and results in an FoM of 2fJ/c.-s.
{"title":"A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique","authors":"Yao-Sheng Hu, Kai-Yue Lin, Hsin-Shu Chen","doi":"10.1109/ASSCC.2016.7844157","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844157","url":null,"abstract":"This paper presents an energy-efficient 12-bit 200kS/s subranging SAR ADC for multi-touch sensing applications. In order to reduce DAC power consumption, an energy-curve reshape technique is proposed to fit the switching energy curve to the characteristics of Rx signals. An auxiliary polarity quantizer joined with the well-known bottom-plate sampling not only can eliminate the gain mismatch of the subranging architecture but also can be as effective as the top-plate sampling. The ADC low-voltage operation could support the smart wake-up mode in the touch sensing system without using dual reference voltages. A pulse-type self-trigger latch technique is utilized to decrease digital loop power dissipation in the low-voltage environment. This ADC consumes 0.95 μW at 200kS/s under a 0.7V supply in 40nm CMOS technology. It achieves an SNDR of 69.24dB at Nyquist rate and results in an FoM of 2fJ/c.-s.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126964161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844181
Young-Ho Choi, Kihwan Seong, Byungsub Kim, J. Sim, Hong-June Park
A high-speed transmitter for serial link interface was synthesized by using only Verilog codes and digital standard cells. The transmitter employs a differential voltage-mode architecture with a 2-tap feed-forward equalizer (FFE). A delay line which is locked to a data period is used for the FFE operation because a high speed flip-flop is not available in standard cells. The proposed transmitter chip in a 65nm CMOS process works at data rates up to 6Gbps with a 1.4m FR4 microstrip line of 20.6dB loss, occupies 0.0363mm2 and consumes 33.6mW at 1.2 V.
{"title":"All-synthesizable 6Gbps voltage-mode transmitter for serial link","authors":"Young-Ho Choi, Kihwan Seong, Byungsub Kim, J. Sim, Hong-June Park","doi":"10.1109/ASSCC.2016.7844181","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844181","url":null,"abstract":"A high-speed transmitter for serial link interface was synthesized by using only Verilog codes and digital standard cells. The transmitter employs a differential voltage-mode architecture with a 2-tap feed-forward equalizer (FFE). A delay line which is locked to a data period is used for the FFE operation because a high speed flip-flop is not available in standard cells. The proposed transmitter chip in a 65nm CMOS process works at data rates up to 6Gbps with a 1.4m FR4 microstrip line of 20.6dB loss, occupies 0.0363mm2 and consumes 33.6mW at 1.2 V.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125984380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844205
Masato Tamura, M. Ikeda
We have designed and fabricated a 256-bit elliptic curve digital signature algorithm (ECDSA) on a GF(p) signature generation processor in SOTB 65-nm CMOS. We have optimized the pipeline architecture of the Montgomery multiplier by exploiting parallelism, and have achieved 1/50 energy consumption for signature generation, as compared with the previously reported state-of-the-art. Our processor showed correct operation under a wide range of power supply voltages (Vdd) from 1.1 V to 0.25 V, realized a signature generation time (Tsg) of 325 μs at Vdd of 1.1 V and a body bias of VBP = 0.55 V and VBN = 0.55 V, Tsg of 2.3 ms and an energy consumption of 1.68 μJ at Vdd of 0.3 V and a body bias of VBP = 0.3 V and VBN = 0 V, and Tsg of 11 ms and a power consumption of 0.15 mW at Vdd of 0.25 V and a body bias of VBP = 0.37 V and VBN = −0.12 V. Our design demonstrated the lowest power/energy value ever reported and the fastest signature generation ever reported in real silicon.
{"title":"1.68μJ/signature-generation 256-bit ECDSA over GF(p) signature generator for IoT devices","authors":"Masato Tamura, M. Ikeda","doi":"10.1109/ASSCC.2016.7844205","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844205","url":null,"abstract":"We have designed and fabricated a 256-bit elliptic curve digital signature algorithm (ECDSA) on a GF(p) signature generation processor in SOTB 65-nm CMOS. We have optimized the pipeline architecture of the Montgomery multiplier by exploiting parallelism, and have achieved 1/50 energy consumption for signature generation, as compared with the previously reported state-of-the-art. Our processor showed correct operation under a wide range of power supply voltages (Vdd) from 1.1 V to 0.25 V, realized a signature generation time (Tsg) of 325 μs at Vdd of 1.1 V and a body bias of VBP = 0.55 V and VBN = 0.55 V, Tsg of 2.3 ms and an energy consumption of 1.68 μJ at Vdd of 0.3 V and a body bias of VBP = 0.3 V and VBN = 0 V, and Tsg of 11 ms and a power consumption of 0.15 mW at Vdd of 0.25 V and a body bias of VBP = 0.37 V and VBN = −0.12 V. Our design demonstrated the lowest power/energy value ever reported and the fastest signature generation ever reported in real silicon.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128145941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844132
T. Someya, K. Matsunaga, H. Morimura, T. Sakurai, M. Takamiya
A programmable voltage detector (PVD) for the battery management is developed for the first time. In battery management applications, PVD's with fine voltage resolution (<±1% of battery voltage) are required to precisely control the charging and discharging of the battery and to provide a universal voltage detector. The proposed fine voltage-step subtraction (FVS) method in PVD enables the wide detection voltage (Vdetect) range from 1.88 V to 4.67 V, fine Vdetect resolution of 50mV, and the 56-level linear programmability. Compared with previous publications, the 50-mV resolution is the smallest and the 56-level programmability is the largest. The programmability of Vdetect enables a Vdetect hopping capability achieving time-varying Vdetect to reduce the number of voltage detectors in the battery management system. PVD fabricated in 5V, 250-nm CMOS process shows the measured power consumption of 13nW at 3.5V and the temperature coefficient of 0.17mV/°C in −20°C to 80°C.
{"title":"56-Level programmable voltage detector in steps of 50mV for battery management","authors":"T. Someya, K. Matsunaga, H. Morimura, T. Sakurai, M. Takamiya","doi":"10.1109/ASSCC.2016.7844132","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844132","url":null,"abstract":"A programmable voltage detector (PVD) for the battery management is developed for the first time. In battery management applications, PVD's with fine voltage resolution (<±1% of battery voltage) are required to precisely control the charging and discharging of the battery and to provide a universal voltage detector. The proposed fine voltage-step subtraction (FVS) method in PVD enables the wide detection voltage (Vdetect) range from 1.88 V to 4.67 V, fine Vdetect resolution of 50mV, and the 56-level linear programmability. Compared with previous publications, the 50-mV resolution is the smallest and the 56-level programmability is the largest. The programmability of Vdetect enables a Vdetect hopping capability achieving time-varying Vdetect to reduce the number of voltage detectors in the battery management system. PVD fabricated in 5V, 250-nm CMOS process shows the measured power consumption of 13nW at 3.5V and the temperature coefficient of 0.17mV/°C in −20°C to 80°C.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131371810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844174
Quoc-Hoang Duong, J. Kong, H. Shin, Huy-Hieu Nguyen, Pan-Jong Kim, Yu-Seok Ko, Hwayeal Yu, Hojin Park
In portable mobile devices, the power management IC unit (PMIC) requires many low-dropout voltage regulators (LDO) with different output voltages and load current capacities to support many applications; such as Application Processor (AP), Camera, Memory, RFIC Transceivers, USB, etc. For example, the PMIC in mobile phone Galaxy S6/S7 needs more than 50 LDOs to support the above applications, which require an extremely big quiescent current that degrade battery life time. Reducing quiescent current of LDO while maintaining system's operation is critical; however, there is a big trade-off between quiescent current and other LDO's characteristics such as undershoot/overshoot, PSRR, noise, etc. This paper proposed a new multiple-loop design technique for LDO that offer very low quiescent current (more than 50% reduction); however, excellent performance improvement compared to prior reported works. The design has been successfully implemented in many products of Samsung for mobile phone, Table PCs, etc.
{"title":"Multiple-loop design technique for high-performance low dropout regulator","authors":"Quoc-Hoang Duong, J. Kong, H. Shin, Huy-Hieu Nguyen, Pan-Jong Kim, Yu-Seok Ko, Hwayeal Yu, Hojin Park","doi":"10.1109/ASSCC.2016.7844174","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844174","url":null,"abstract":"In portable mobile devices, the power management IC unit (PMIC) requires many low-dropout voltage regulators (LDO) with different output voltages and load current capacities to support many applications; such as Application Processor (AP), Camera, Memory, RFIC Transceivers, USB, etc. For example, the PMIC in mobile phone Galaxy S6/S7 needs more than 50 LDOs to support the above applications, which require an extremely big quiescent current that degrade battery life time. Reducing quiescent current of LDO while maintaining system's operation is critical; however, there is a big trade-off between quiescent current and other LDO's characteristics such as undershoot/overshoot, PSRR, noise, etc. This paper proposed a new multiple-loop design technique for LDO that offer very low quiescent current (more than 50% reduction); however, excellent performance improvement compared to prior reported works. The design has been successfully implemented in many products of Samsung for mobile phone, Table PCs, etc.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130047132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844200
W. El-Halwagy, P. Mousavi, Masum Hossain
This paper introduces a first-order noise-shaped time-domain ADC utilizing SAR-TDC as quantizer. The high resolution correlated double sampling SAR-TDC improves the quantization noise level of the ADC. The VCO non-linearity is resolved by employing a 1-bit folded VCO architecture. The ADC linearity is further improved using foreground digital calibration. Implemented in 65nm CMOS, the 675MS/s time-domain ADC achieves measured peak SNDR/SFDR of 79.5/86.4dB in 10MHz BW while consuming 11.65mW. The SAR-TDC achieves 1.15ps resolution with peak measured DNL/INL of 0.64/0.65LSB. The 1-bit folded VCO improves the VCO linearity from 12% to 0.17%.
{"title":"A 79dB SNDR, 10MHz BW, 675MS/s open-loop time-based ADC employing a 1.15ps SAR-TDC","authors":"W. El-Halwagy, P. Mousavi, Masum Hossain","doi":"10.1109/ASSCC.2016.7844200","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844200","url":null,"abstract":"This paper introduces a first-order noise-shaped time-domain ADC utilizing SAR-TDC as quantizer. The high resolution correlated double sampling SAR-TDC improves the quantization noise level of the ADC. The VCO non-linearity is resolved by employing a 1-bit folded VCO architecture. The ADC linearity is further improved using foreground digital calibration. Implemented in 65nm CMOS, the 675MS/s time-domain ADC achieves measured peak SNDR/SFDR of 79.5/86.4dB in 10MHz BW while consuming 11.65mW. The SAR-TDC achieves 1.15ps resolution with peak measured DNL/INL of 0.64/0.65LSB. The 1-bit folded VCO improves the VCO linearity from 12% to 0.17%.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133474893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844162
Hyunui Lee, S. Kang, Hye-Seung Yu, Won-Joo Yun, Jae-Hun Jung, Sungoh Ahn, Wang-Soo Kim, Beomyong Kil, Y. Sung, Sang-Hoon Shin, Yong-Sik Park, Yong-Hwan Kim, Kyung-Woo Nam, Indal Song, Kyomin Sohn, Yong-Cheol Bae, J. Choi, Seong-Jin Jang, G. Jin
This paper presents a HBM device which verifies DC and AC characteristics of I/O circuits without direct contact on the u-bump. To verify DC and AC characteristics internally, design for excellence (DFx) circuits are implemented. Also, to perform accurate impedance calibration without ZQ pin, reference resistor calibration logic is embedded. In comparison of DFx AC result and automatic test equipment measurement result, it is confirmed that the DFx AC operation is well correlated with normal operation up to 2Gb/s.
{"title":"Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)","authors":"Hyunui Lee, S. Kang, Hye-Seung Yu, Won-Joo Yun, Jae-Hun Jung, Sungoh Ahn, Wang-Soo Kim, Beomyong Kil, Y. Sung, Sang-Hoon Shin, Yong-Sik Park, Yong-Hwan Kim, Kyung-Woo Nam, Indal Song, Kyomin Sohn, Yong-Cheol Bae, J. Choi, Seong-Jin Jang, G. Jin","doi":"10.1109/ASSCC.2016.7844162","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844162","url":null,"abstract":"This paper presents a HBM device which verifies DC and AC characteristics of I/O circuits without direct contact on the u-bump. To verify DC and AC characteristics internally, design for excellence (DFx) circuits are implemented. Also, to perform accurate impedance calibration without ZQ pin, reference resistor calibration logic is embedded. In comparison of DFx AC result and automatic test equipment measurement result, it is confirmed that the DFx AC operation is well correlated with normal operation up to 2Gb/s.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126026204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844194
Abhik Das, Yuan Gao, T. T. Kim
This paper presents a highly efficient 3-stage boost converter with an isolated Power-on-Reset (PoR) based starter for thermal energy harvesting. The automatic pulse generation property of the proposed PoR is coupled with a charge-pump (CP) based clock enhancer (CE) to enhance the gate-driving capability for fast and efficient boost conversion during startup. Unlike conventional PoR-based startup circuits, where the reset signals cannot be directly utilized to execute a boost conversion during startup, the proposed starter converts a chain of pulses from the PoR into level-shifted clock signals to aid direct boost conversion from sub-threshold voltages. The proposed boost converter has a minimum self-startup TEG voltage of 150 mV at the series resistance (ESR) of 450 Ω without using external devices or native MOSFET. The maximum ESR for startup is 600 Ω at the TEG voltage of 320 mV. The peak power conversion efficiency of the proposed boost converter is 78 %.
{"title":"An isolated PoR based pulse generator for TEG energy harvesting with minimum startup of 150 mV and maximum series resistance of 600 Ω","authors":"Abhik Das, Yuan Gao, T. T. Kim","doi":"10.1109/ASSCC.2016.7844194","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844194","url":null,"abstract":"This paper presents a highly efficient 3-stage boost converter with an isolated Power-on-Reset (PoR) based starter for thermal energy harvesting. The automatic pulse generation property of the proposed PoR is coupled with a charge-pump (CP) based clock enhancer (CE) to enhance the gate-driving capability for fast and efficient boost conversion during startup. Unlike conventional PoR-based startup circuits, where the reset signals cannot be directly utilized to execute a boost conversion during startup, the proposed starter converts a chain of pulses from the PoR into level-shifted clock signals to aid direct boost conversion from sub-threshold voltages. The proposed boost converter has a minimum self-startup TEG voltage of 150 mV at the series resistance (ESR) of 450 Ω without using external devices or native MOSFET. The maximum ESR for startup is 600 Ω at the TEG voltage of 320 mV. The peak power conversion efficiency of the proposed boost converter is 78 %.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131250058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844154
Jongeun Koo, Eunwoo Song, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, S. Yoo, Jae-Joon Kim
We propose a new timing error correction scheme for area-efficient design of flip-flop based pipeline. Key features in the proposed scheme are 1) one-cycle error correction using a new local stalling scheme and 2) selective replacement of the error detection and correction flip-flops in critical paths only. A 32-bit MIPS testchip in a 65 nm CMOS technology has been implemented as a testbed. By employing the proposed scheme in the flop-flop based pipeline, the area overhead due to the retiming process (∼21%) in the previous two-phase transparent latch based scheme can be eliminated. In addition, substantial area saving (16%) can be achieved compared to the state-of-the-art flip-flop based scheme thanks to the selective replacement of the error detection and correction flip-flops.
{"title":"Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines","authors":"Jongeun Koo, Eunwoo Song, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, S. Yoo, Jae-Joon Kim","doi":"10.1109/ASSCC.2016.7844154","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844154","url":null,"abstract":"We propose a new timing error correction scheme for area-efficient design of flip-flop based pipeline. Key features in the proposed scheme are 1) one-cycle error correction using a new local stalling scheme and 2) selective replacement of the error detection and correction flip-flops in critical paths only. A 32-bit MIPS testchip in a 65 nm CMOS technology has been implemented as a testbed. By employing the proposed scheme in the flop-flop based pipeline, the area overhead due to the retiming process (∼21%) in the previous two-phase transparent latch based scheme can be eliminated. In addition, substantial area saving (16%) can be achieved compared to the state-of-the-art flip-flop based scheme thanks to the selective replacement of the error detection and correction flip-flops.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124969093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844141
Xuqiang Zheng, Chun Zhang, S. Yuan, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
An improved clock data recovery (CDR) operating at 40 Gb/s is implemented in 65 nm CMOS technology. Passive low-pass filters (LPFs) with adaptively adjusted bandwidth are introduced into the data-sampling path to automatically balance jitter tracking and jitter suppression for data decisions. Additionally, a time-averaging based compensating phase interpolator (PI) is proposed to not only improve the phase-step uniformity but also reduce phase-spacing drifting between edge and data sampling clocks. Measurement results show that different bandwidths for jitter transfer (4 MHz) and jitter tolerance (20 MHz) can be obtained. The total jitter of recovered clocks for edge-sampling and data-sampling are 11.48 ps and 7.66 ps, respectively. Meanwhile, the introduced jitter-suppression filters improve the maximum tolerable amplitude of sinusoidal jitter from 0.31 UI to 0.41 UI at 100 MHz.
{"title":"An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators","authors":"Xuqiang Zheng, Chun Zhang, S. Yuan, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang","doi":"10.1109/ASSCC.2016.7844141","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844141","url":null,"abstract":"An improved clock data recovery (CDR) operating at 40 Gb/s is implemented in 65 nm CMOS technology. Passive low-pass filters (LPFs) with adaptively adjusted bandwidth are introduced into the data-sampling path to automatically balance jitter tracking and jitter suppression for data decisions. Additionally, a time-averaging based compensating phase interpolator (PI) is proposed to not only improve the phase-step uniformity but also reduce phase-spacing drifting between edge and data sampling clocks. Measurement results show that different bandwidths for jitter transfer (4 MHz) and jitter tolerance (20 MHz) can be obtained. The total jitter of recovered clocks for edge-sampling and data-sampling are 11.48 ps and 7.66 ps, respectively. Meanwhile, the introduced jitter-suppression filters improve the maximum tolerable amplitude of sinusoidal jitter from 0.31 UI to 0.41 UI at 100 MHz.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"323 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132459138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：