Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844131
Chih-Chan Tu, Yu-Kai Wang, Tsung-Hsien Lin
A sensor readout circuit employing chopped VCO-based CTDSM is presented in this paper. This VCO-based ADC features direct connection to the sensors to eliminate pre-amplifier. The VCO is designed as a Gm-CCO, which is a Gm stage cascaded with the folded-cascode current-controlled oscillator. The proposed circuit ensures a high input impedance. Furthermore, the main noise and offset contributor, the Gm stage, is mitigated by chopping operation. The VCO-based CTDSM is implemented in 40-nm CMOS. The whole circuit draws 14 μA from 1.2-V supply. With a 2.4-mVpp input, it achieves 49.43 dB SNDR over 5-kHz BW and has SFDR of 59.5 dB. The input-referred noise is 40nV/√Hz. The chip area is only 0.0145 mm2.
{"title":"A 40-nV/VHz 0.0145-mm2 sensor readout circuit with chopped VCO-based CTDSM in 40-nm CMOS","authors":"Chih-Chan Tu, Yu-Kai Wang, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2016.7844131","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844131","url":null,"abstract":"A sensor readout circuit employing chopped VCO-based CTDSM is presented in this paper. This VCO-based ADC features direct connection to the sensors to eliminate pre-amplifier. The VCO is designed as a Gm-CCO, which is a Gm stage cascaded with the folded-cascode current-controlled oscillator. The proposed circuit ensures a high input impedance. Furthermore, the main noise and offset contributor, the Gm stage, is mitigated by chopping operation. The VCO-based CTDSM is implemented in 40-nm CMOS. The whole circuit draws 14 μA from 1.2-V supply. With a 2.4-mVpp input, it achieves 49.43 dB SNDR over 5-kHz BW and has SFDR of 59.5 dB. The input-referred noise is 40nV/√Hz. The chip area is only 0.0145 mm2.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131161160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844184
Sungpill Choi, Seongwook Park, H. Yoo
A low-power depth-estimation processor is proposed for mobile UI applications. We adopt hardware-friendly shift-only computations for exponentiation and multiplication in stereo algorithm to reduce power consumption down to 4.7mW with negligible accuracy loss. Also, the 7-stage shifter-register-based pipeline architecture with applying pipeline reordering optimization is deployed for reducing power and area. Utilization of the proposed pipeline architecture is 94% at 166MHz. The proposed algorithm and hardware co-optimization reduces required number of operations and external memory accesses by 85.5%, resulting in 75.6% lower energy consumption. The 1.47mm2 chip is fabricated with 65nm CMOS process and the resulting depth map is successfully used for hand segmentation.
{"title":"A 34pJ/level pixel depth-estimation processor with shifter-based pipelined architecture for mobile user interface","authors":"Sungpill Choi, Seongwook Park, H. Yoo","doi":"10.1109/ASSCC.2016.7844184","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844184","url":null,"abstract":"A low-power depth-estimation processor is proposed for mobile UI applications. We adopt hardware-friendly shift-only computations for exponentiation and multiplication in stereo algorithm to reduce power consumption down to 4.7mW with negligible accuracy loss. Also, the 7-stage shifter-register-based pipeline architecture with applying pipeline reordering optimization is deployed for reducing power and area. Utilization of the proposed pipeline architecture is 94% at 166MHz. The proposed algorithm and hardware co-optimization reduces required number of operations and external memory accesses by 85.5%, resulting in 75.6% lower energy consumption. The 1.47mm2 chip is fabricated with 65nm CMOS process and the resulting depth map is successfully used for hand segmentation.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"8 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120967708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844134
Yuan Ren, Sai-Weng Sin, C. Lam, M. Wong, U. Seng-Pan, R. Martins
This paper presents a 4-channel power electronics (PE) controller front-end interface with input signal conditioning and analog-to-digital (A/D) conversion functions for different power electronics system applications. The proposed front-end is composed of a 4-channel continuous-time (CT) and discrete-time (DT) hybrid sigma-delta modulator (H-EAM) embedding an input programmable-gain (PGA) in the first CT stage in order to enhance the input dynamic range (DR). The second shared DT stage is designed to utilize multiple-sampling technique with a shared single Op-Amp for low power consumption. This PE controller front-end chip is fabricated with 65 nm CMOS technology. Measurement results show a high dynamic range of 98.3 dB and 84.2 dB SNDR, while achieving a power consumption of 68 μW per channel and a FoMs of 172–179 dB due to the dynamic range boost.
{"title":"A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller","authors":"Yuan Ren, Sai-Weng Sin, C. Lam, M. Wong, U. Seng-Pan, R. Martins","doi":"10.1109/ASSCC.2016.7844134","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844134","url":null,"abstract":"This paper presents a 4-channel power electronics (PE) controller front-end interface with input signal conditioning and analog-to-digital (A/D) conversion functions for different power electronics system applications. The proposed front-end is composed of a 4-channel continuous-time (CT) and discrete-time (DT) hybrid sigma-delta modulator (H-EAM) embedding an input programmable-gain (PGA) in the first CT stage in order to enhance the input dynamic range (DR). The second shared DT stage is designed to utilize multiple-sampling technique with a shared single Op-Amp for low power consumption. This PE controller front-end chip is fabricated with 65 nm CMOS technology. Measurement results show a high dynamic range of 98.3 dB and 84.2 dB SNDR, while achieving a power consumption of 68 μW per channel and a FoMs of 172–179 dB due to the dynamic range boost.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125428097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844171
Lei Yao, I. M. Darmayuda, Yuan Gao
In this paper, we present a dynamic voltage scaling supply (DVSS) for electrical stimulation applications. The core architecture of the proposed DVSS is based on a 7x series-parallel charge pump structure. It converts 1.65V DC input into N × 1.65V DC output in which the number of N can be dynamically scaled from 1 to 7. The DVSS circuit consumes a static power of 20μW and achieves a peak efficiency of 83.3% under a constant current load of 500μΛ at output voltage of 3 × 1.65V. The DVSS circuit has a fast response time of 146ns when switching from standby to the maximum 11.4V output. It has an intrinsic energy recycling mechanism to effectively reduce the energy wastage when switching DVSS from active to standby state. The DVSS circuit is designed and implemented in a standard 0.18μm CMOS process without high-voltage (HV) transistor option, which saves mask cost and provides possibility for HV stimulation system to be designed and integrated in more advanced technology node.
{"title":"A 83% peak efficiency 1.65 V to 11.4V dynamic voltage scaling supply for electrical stimulation applications in standard 0.18μm CMOS process","authors":"Lei Yao, I. M. Darmayuda, Yuan Gao","doi":"10.1109/ASSCC.2016.7844171","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844171","url":null,"abstract":"In this paper, we present a dynamic voltage scaling supply (DVSS) for electrical stimulation applications. The core architecture of the proposed DVSS is based on a 7x series-parallel charge pump structure. It converts 1.65V DC input into N × 1.65V DC output in which the number of N can be dynamically scaled from 1 to 7. The DVSS circuit consumes a static power of 20μW and achieves a peak efficiency of 83.3% under a constant current load of 500μΛ at output voltage of 3 × 1.65V. The DVSS circuit has a fast response time of 146ns when switching from standby to the maximum 11.4V output. It has an intrinsic energy recycling mechanism to effectively reduce the energy wastage when switching DVSS from active to standby state. The DVSS circuit is designed and implemented in a standard 0.18μm CMOS process without high-voltage (HV) transistor option, which saves mask cost and provides possibility for HV stimulation system to be designed and integrated in more advanced technology node.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125269176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Conventional hybrid supply modulator for envelope tracking (ET) technique requires the linear amplifier to track a RF envelop signal with the help of switching converter to provide average power for high efficiency. Any distortion caused by resistive and inaccurate current sensing will result in increase of power loss and Error Vector Magnitude (EVM). Thus, a lossless inductor current control (LICC) with a closed-loop self-allocation technique is proposed to increase efficiency and decrease the EVM. Inductor current ripple information is directly extracted from the gate drive signal of a class-AB linear amplifier and a weighted self-allocation control is applied to optimize for efficiency and EVM. Extra power improvement of 2.5% can be derived. Owing to the removal of a power-consuming sensing resistor in conventional design, the efficiency can be effectively improved. The proposed supply modulator is capable of delivering an instantaneous peak power of 3.36W and a bandwidth of 20MHz with an averaged efficiency up to 85%.
{"title":"Lossless inductor current control in envelope tracking supply modulator with self-allocation of energy for optimzation of efficiency and EVM","authors":"Shang-Hsien Yang, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai","doi":"10.1109/ASSCC.2016.7844190","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844190","url":null,"abstract":"Conventional hybrid supply modulator for envelope tracking (ET) technique requires the linear amplifier to track a RF envelop signal with the help of switching converter to provide average power for high efficiency. Any distortion caused by resistive and inaccurate current sensing will result in increase of power loss and Error Vector Magnitude (EVM). Thus, a lossless inductor current control (LICC) with a closed-loop self-allocation technique is proposed to increase efficiency and decrease the EVM. Inductor current ripple information is directly extracted from the gate drive signal of a class-AB linear amplifier and a weighted self-allocation control is applied to optimize for efficiency and EVM. Extra power improvement of 2.5% can be derived. Owing to the removal of a power-consuming sensing resistor in conventional design, the efficiency can be effectively improved. The proposed supply modulator is capable of delivering an instantaneous peak power of 3.36W and a bandwidth of 20MHz with an averaged efficiency up to 85%.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123779173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ASSCC.2016.7844133
S. Chiu, Chun-Chieh Kuo, K. Chuang, Wen-Hau Yang, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Jian-Ru Lin, Lsung-Yen Lsai, Jui-Lung Chen
The proposed pseudo-linear LED driver can effectively solve the serious flicker in conventional linear LED driver (LLD). Besides, it has good electromagnetic interference (EMI) performance similar to that in conventional LLD at high AC input voltage. In the meanwhile, it has high power factor (PF) similar to boost switching regulator (SWR) LED driver at low AC input voltage. Furthermore, owing to the combination of line filter and the active full bridge rectifier, the pseudo-linear LED driver has a compact solution and high efficiency. The test chip was fabricated in 0.5μm 500V LDMOS process. Experimental results show 93% high efficiency, 6% total harmonic distortion (THD), and 0.99 PF at the power of 7W.
{"title":"93% Efficiency and 0.99 power factor in pseudo-linear LED driver","authors":"S. Chiu, Chun-Chieh Kuo, K. Chuang, Wen-Hau Yang, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Jian-Ru Lin, Lsung-Yen Lsai, Jui-Lung Chen","doi":"10.1109/ASSCC.2016.7844133","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844133","url":null,"abstract":"The proposed pseudo-linear LED driver can effectively solve the serious flicker in conventional linear LED driver (LLD). Besides, it has good electromagnetic interference (EMI) performance similar to that in conventional LLD at high AC input voltage. In the meanwhile, it has high power factor (PF) similar to boost switching regulator (SWR) LED driver at low AC input voltage. Furthermore, owing to the combination of line filter and the active full bridge rectifier, the pseudo-linear LED driver has a compact solution and high efficiency. The test chip was fabricated in 0.5μm 500V LDMOS process. Experimental results show 93% high efficiency, 6% total harmonic distortion (THD), and 0.99 PF at the power of 7W.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124661501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ASSCC.2016.7844193
Hui-Hsuan Lee, Po-Hung Chen
In this paper, a single-inductor dual-input dual-output (SIDIDO) power converter with sequential pulse-skip modulation (SPSM) is proposed for IoT applications. It manages power from a 1.4-V zinc-air battery and a 0.55-V to 0.7-V photovoltaic (PV) module to prolong the battery life. The proposed converter employs buck-boost mode and buck mode for PV module and the battery, respectively, to produce two different output voltages. The input sources are automatically selected by mode detection circuit which monitors both PV voltage and the output voltage to minimize the battery usage. The proposed SPSM along with a constant voltage maximum power point tracking (MPPT) method controls output voltages with low cross regulation while extracting the maximum power from a PV module. The measurement results demonstrate a peak efficiency of 89 % with an available input voltage of 0.55 V to 1.4 V.
{"title":"A single-inductor dual-input dual-output (SIDIDO) power management with sequential pulse-skip modulation for battery/PV hybrid systems","authors":"Hui-Hsuan Lee, Po-Hung Chen","doi":"10.1109/ASSCC.2016.7844193","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844193","url":null,"abstract":"In this paper, a single-inductor dual-input dual-output (SIDIDO) power converter with sequential pulse-skip modulation (SPSM) is proposed for IoT applications. It manages power from a 1.4-V zinc-air battery and a 0.55-V to 0.7-V photovoltaic (PV) module to prolong the battery life. The proposed converter employs buck-boost mode and buck mode for PV module and the battery, respectively, to produce two different output voltages. The input sources are automatically selected by mode detection circuit which monitors both PV voltage and the output voltage to minimize the battery usage. The proposed SPSM along with a constant voltage maximum power point tracking (MPPT) method controls output voltages with low cross regulation while extracting the maximum power from a PV module. The measurement results demonstrate a peak efficiency of 89 % with an available input voltage of 0.55 V to 1.4 V.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133269984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ASSCC.2016.7844204
Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm2, drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.
{"title":"A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications","authors":"Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ASSCC.2016.7844204","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844204","url":null,"abstract":"LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm2, drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132591257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ASSCC.2016.7844191
J. Prinzie, M. Steyaert, P. Leroux, J. Christiansen, P. Moreira
This paper presents a Single Event Upset (SEU) robust low phase-noise PLL for clock generation in harsh environments like nuclear and space applications. The PLL has been implemented in a 65 nm CMOS technology. A low noise LC-tank oscillator is included with a tuning range from 2.2 GHz to 3.2 GHz. The PLL includes a new phase detector and divider with Triple Modular Redundancy (TMR) to suppress Single Event Effects in ionizing radiation environments. A highly reconfigurable bandwidth from 0.7 MHz to 2 MHz provides optimal reference phase noise filtering. The PLL has been designed and measured to operate in a temperature range from −25 C to 125 C and features a jitter of 345 fs rms with a power consumption of 11.7 mW and is tolerant to 10 % supply variations. Single Event Upset laser tests are performed to verify the triplicated circuit performance.
{"title":"A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS","authors":"J. Prinzie, M. Steyaert, P. Leroux, J. Christiansen, P. Moreira","doi":"10.1109/ASSCC.2016.7844191","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844191","url":null,"abstract":"This paper presents a Single Event Upset (SEU) robust low phase-noise PLL for clock generation in harsh environments like nuclear and space applications. The PLL has been implemented in a 65 nm CMOS technology. A low noise LC-tank oscillator is included with a tuning range from 2.2 GHz to 3.2 GHz. The PLL includes a new phase detector and divider with Triple Modular Redundancy (TMR) to suppress Single Event Effects in ionizing radiation environments. A highly reconfigurable bandwidth from 0.7 MHz to 2 MHz provides optimal reference phase noise filtering. The PLL has been designed and measured to operate in a temperature range from −25 C to 125 C and features a jitter of 345 fs rms with a power consumption of 11.7 mW and is tolerant to 10 % supply variations. Single Event Upset laser tests are performed to verify the triplicated circuit performance.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129287631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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