Kaifang Weng, Changsheng Shen, Zhaofu Chen, Ningfeng Bai
Recent advances in nanofabrication have made it possible to combine planar solid-state devices with vacuum electronics to create planar nano vacuum channel transistors that offer the advantages of cold-field emission and ballistic transmission. However, the current research is mainly limited to the study of a single field emission transistor, which has problems such as low current and poor gate control capability. To solve the above problems, a multitip field emission array is used in this work, and gate modulation is performed by a back-gate structure to fabricate and process a back-gate nano vacuum transistor array. First, we conducted simulation modeling of the back-gate nano vacuum transistor, investigated the impact of its structural parameters on its performance, and obtained the optimal simulation results. Then, structural parameters of the back-gate nano vacuum channel transistor array (BG-NVCTA) are selected based on the simulation results and fabricated by electron beam lithography on the silicon wafer. The experimental results, agreed well with the simulation results, show that the BG-NVCTA device has excellent gate control characteristics and a high current density. Its anode current is greater than 5 μA, and the transconductance is 1.05 μS when the anode voltage is 5 V.
纳米制造技术的最新进展使平面固态器件与真空电子器件的结合成为可能，从而制造出具有冷场发射和弹道传输优势的平面纳米真空沟道晶体管。然而，目前的研究主要局限于单场发射晶体管的研究，存在电流小、栅极控制能力差等问题。为解决上述问题，本研究采用了多芯片场发射阵列，并通过后栅结构进行栅极调制，制作和加工出了后栅纳米真空晶体管阵列。首先，我们对背栅纳米真空晶体管进行了仿真建模，研究了其结构参数对其性能的影响，并得到了最优的仿真结果。然后，根据仿真结果选择了背栅纳米真空沟道晶体管阵列（BG-NVCTA）的结构参数，并通过电子束光刻技术在硅片上制作了该阵列。实验结果与仿真结果一致，表明 BG-NVCTA 器件具有优异的栅极控制特性和较高的电流密度。其阳极电流大于 5 μA，阳极电压为 5 V 时的跨导为 1.05 μS。
{"title":"Investigation of silicon-on-insulator back-gate nano vacuum channel transistor array","authors":"Kaifang Weng, Changsheng Shen, Zhaofu Chen, Ningfeng Bai","doi":"10.1116/6.0003346","DOIUrl":"https://doi.org/10.1116/6.0003346","url":null,"abstract":"Recent advances in nanofabrication have made it possible to combine planar solid-state devices with vacuum electronics to create planar nano vacuum channel transistors that offer the advantages of cold-field emission and ballistic transmission. However, the current research is mainly limited to the study of a single field emission transistor, which has problems such as low current and poor gate control capability. To solve the above problems, a multitip field emission array is used in this work, and gate modulation is performed by a back-gate structure to fabricate and process a back-gate nano vacuum transistor array. First, we conducted simulation modeling of the back-gate nano vacuum transistor, investigated the impact of its structural parameters on its performance, and obtained the optimal simulation results. Then, structural parameters of the back-gate nano vacuum channel transistor array (BG-NVCTA) are selected based on the simulation results and fabricated by electron beam lithography on the silicon wafer. The experimental results, agreed well with the simulation results, show that the BG-NVCTA device has excellent gate control characteristics and a high current density. Its anode current is greater than 5 μA, and the transconductance is 1.05 μS when the anode voltage is 5 V.","PeriodicalId":282302,"journal":{"name":"Journal of Vacuum Science & Technology B","volume":"66 3","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139810326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kaifang Weng, Changsheng Shen, Zhaofu Chen, Ningfeng Bai
Recent advances in nanofabrication have made it possible to combine planar solid-state devices with vacuum electronics to create planar nano vacuum channel transistors that offer the advantages of cold-field emission and ballistic transmission. However, the current research is mainly limited to the study of a single field emission transistor, which has problems such as low current and poor gate control capability. To solve the above problems, a multitip field emission array is used in this work, and gate modulation is performed by a back-gate structure to fabricate and process a back-gate nano vacuum transistor array. First, we conducted simulation modeling of the back-gate nano vacuum transistor, investigated the impact of its structural parameters on its performance, and obtained the optimal simulation results. Then, structural parameters of the back-gate nano vacuum channel transistor array (BG-NVCTA) are selected based on the simulation results and fabricated by electron beam lithography on the silicon wafer. The experimental results, agreed well with the simulation results, show that the BG-NVCTA device has excellent gate control characteristics and a high current density. Its anode current is greater than 5 μA, and the transconductance is 1.05 μS when the anode voltage is 5 V.
纳米制造技术的最新进展使平面固态器件与真空电子器件的结合成为可能，从而制造出具有冷场发射和弹道传输优势的平面纳米真空沟道晶体管。然而，目前的研究主要局限于单场发射晶体管的研究，存在电流小、栅极控制能力差等问题。为解决上述问题，本研究采用了多芯片场发射阵列，并通过后栅结构进行栅极调制，制作和加工出了后栅纳米真空晶体管阵列。首先，我们对背栅纳米真空晶体管进行了仿真建模，研究了其结构参数对其性能的影响，并得到了最优的仿真结果。然后，根据仿真结果选择了背栅纳米真空沟道晶体管阵列（BG-NVCTA）的结构参数，并通过电子束光刻技术在硅片上制作了该阵列。实验结果与仿真结果一致，表明 BG-NVCTA 器件具有优异的栅极控制特性和较高的电流密度。其阳极电流大于 5 μA，阳极电压为 5 V 时的跨导为 1.05 μS。
{"title":"Investigation of silicon-on-insulator back-gate nano vacuum channel transistor array","authors":"Kaifang Weng, Changsheng Shen, Zhaofu Chen, Ningfeng Bai","doi":"10.1116/6.0003346","DOIUrl":"https://doi.org/10.1116/6.0003346","url":null,"abstract":"Recent advances in nanofabrication have made it possible to combine planar solid-state devices with vacuum electronics to create planar nano vacuum channel transistors that offer the advantages of cold-field emission and ballistic transmission. However, the current research is mainly limited to the study of a single field emission transistor, which has problems such as low current and poor gate control capability. To solve the above problems, a multitip field emission array is used in this work, and gate modulation is performed by a back-gate structure to fabricate and process a back-gate nano vacuum transistor array. First, we conducted simulation modeling of the back-gate nano vacuum transistor, investigated the impact of its structural parameters on its performance, and obtained the optimal simulation results. Then, structural parameters of the back-gate nano vacuum channel transistor array (BG-NVCTA) are selected based on the simulation results and fabricated by electron beam lithography on the silicon wafer. The experimental results, agreed well with the simulation results, show that the BG-NVCTA device has excellent gate control characteristics and a high current density. Its anode current is greater than 5 μA, and the transconductance is 1.05 μS when the anode voltage is 5 V.","PeriodicalId":282302,"journal":{"name":"Journal of Vacuum Science & Technology B","volume":"28 2","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139870134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Optical properties of two-dimensional bilayer silicon have been explored at midinfrared wavelengths using density functional theory. In this work, progressive atomic structural deformation and the resultant variations in the optical properties of the bilayer silicon films were investigated under external in-plane strain. A phase transformation of the atomic structure has been observed at an applied in-plane tensile strain of 5.17%, at which the atomic lattice is changed from a low buckled to a buckle-free honeycomb structure. Evaluations of the optical properties were carried out by taking into account the inter- and intraband transitions. An abrupt change in the optical refraction index was observed at the phase transition. In addition, the buckle-free honeycomb structure presents a strain-resistive absorption edge pinned at 1.14 μm wavelength. Exceeding a strain threshold of 12.26% results in the development of both direct- and indirect-energy bandgap openings. The direct bandgap induced interband optical transitions, resulting in absorption peaks at midinfrared wavelengths and a drastic increase in the refraction index. Moreover, by adjusting the strain, the optical absorptions can be tuned in a wide range of wavelength at midinfrared from 1.5 to 11.5 μm.
{"title":"Strain-tuned optical properties of bilayer silicon at midinfrared wavelengths","authors":"K. Vishal, Z. Ji, Y. Zhuang","doi":"10.1116/6.0003202","DOIUrl":"https://doi.org/10.1116/6.0003202","url":null,"abstract":"Optical properties of two-dimensional bilayer silicon have been explored at midinfrared wavelengths using density functional theory. In this work, progressive atomic structural deformation and the resultant variations in the optical properties of the bilayer silicon films were investigated under external in-plane strain. A phase transformation of the atomic structure has been observed at an applied in-plane tensile strain of 5.17%, at which the atomic lattice is changed from a low buckled to a buckle-free honeycomb structure. Evaluations of the optical properties were carried out by taking into account the inter- and intraband transitions. An abrupt change in the optical refraction index was observed at the phase transition. In addition, the buckle-free honeycomb structure presents a strain-resistive absorption edge pinned at 1.14 μm wavelength. Exceeding a strain threshold of 12.26% results in the development of both direct- and indirect-energy bandgap openings. The direct bandgap induced interband optical transitions, resulting in absorption peaks at midinfrared wavelengths and a drastic increase in the refraction index. Moreover, by adjusting the strain, the optical absorptions can be tuned in a wide range of wavelength at midinfrared from 1.5 to 11.5 μm.","PeriodicalId":282302,"journal":{"name":"Journal of Vacuum Science & Technology B","volume":"54 14","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139869436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chang-Won Jeong, Choong-Mo Ryu, Hee-Lak Lee, Jong Jin Hwang, Seung Jae Moon
The inductively coupled plasma-ion implanter is a closed vacuum, and the temperature increase in the source head owing to plasma generation in the chamber was predicted by numerical simulation and verified via measurements. The heat generation of the source head inside the vacuum chamber was photographed using an infrared thermal-imaging camera and set as the main temperature boundary condition for analysis. The showerhead temperature was confirmed through thermocouple measurements to verify the simulation and ensure reliability. An error of less than 1% was obtained for the aperture and aperture cover. The simulation-analysis results and measured showerhead results obtained from the thermocouple equipment exhibited an error of less than 2%.
{"title":"Thermal analysis of implanter source head in radio-frequency inductively coupled plasma","authors":"Chang-Won Jeong, Choong-Mo Ryu, Hee-Lak Lee, Jong Jin Hwang, Seung Jae Moon","doi":"10.1116/6.0003060","DOIUrl":"https://doi.org/10.1116/6.0003060","url":null,"abstract":"The inductively coupled plasma-ion implanter is a closed vacuum, and the temperature increase in the source head owing to plasma generation in the chamber was predicted by numerical simulation and verified via measurements. The heat generation of the source head inside the vacuum chamber was photographed using an infrared thermal-imaging camera and set as the main temperature boundary condition for analysis. The showerhead temperature was confirmed through thermocouple measurements to verify the simulation and ensure reliability. An error of less than 1% was obtained for the aperture and aperture cover. The simulation-analysis results and measured showerhead results obtained from the thermocouple equipment exhibited an error of less than 2%.","PeriodicalId":282302,"journal":{"name":"Journal of Vacuum Science & Technology B","volume":"115 2","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140482173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mingyu Yu, Jiayang Wang, Sahani A. Iddawela, Molly McDonough, Jessica L. Thompson, S. Sinnott, D. Reifsnyder Hickey, Stephanie Law
GaAs(111)B are commercially available substrates widely used for the growth of van der Waals chalcogenide films. Wafer-scale, high-quality crystalline films can be deposited on GaAs(111)B substrates using molecular beam epitaxy. However, two obstacles persist in the use of GaAs(111)B: first, the surface dangling bonds make it challenging for the growth of van der Waals materials; second, the As-terminated surface is prone to aging in air. This study investigated a thermal treatment method for deoxidizing GaAs(111)B substrates while simultaneously passivating the surface dangling bonds with Se. By optimizing the treatment parameters, we obtained a flat and completely deoxidized platform for subsequent film growth, with highly reproducible operations. Furthermore, through first-principle calculations, we find that the most energetically favorable surface of GaAs(111)B after Se passivation consists of 25% As atoms and 75% Se atoms. Finally, we discovered that the common storage method using food-grade vacuum packaging cannot completely prevent substrate aging, and even after thermal treatment, aging still affects subsequent growth. Therefore, we recommend using N2-purged containers for better preservation.
GaAs(111)B是市场上可买到的基底，广泛用于生长范德华共卤化物薄膜。利用分子束外延技术可以在 GaAs(111)B 基底上沉积出晶圆级的高质量晶体薄膜。然而，在使用 GaAs(111)B 时仍然存在两个障碍：首先，表面悬空键使范德华材料的生长面临挑战；其次，As 端面在空气中容易老化。本研究探讨了一种热处理方法，在对 GaAs(111)B 衬底进行脱氧的同时，用 Se 对表面悬空键进行钝化。通过优化处理参数，我们获得了一个平整且完全脱氧的平台，可用于后续薄膜生长，并且操作具有高度的可重复性。此外，通过第一原理计算，我们发现硒钝化后的 GaAs(111)B 最有利的能量表面由 25% 的 As 原子和 75% 的 Se 原子组成。最后，我们发现使用食品级真空包装的常见存储方法无法完全防止基底老化，即使经过热处理，老化仍然会影响后续生长。因此，我们建议使用氮气吹扫的容器来进行更好的保存。
{"title":"Treatment and aging studies of GaAs(111)B substrates for van der Waals chalcogenide film growth","authors":"Mingyu Yu, Jiayang Wang, Sahani A. Iddawela, Molly McDonough, Jessica L. Thompson, S. Sinnott, D. Reifsnyder Hickey, Stephanie Law","doi":"10.1116/6.0003470","DOIUrl":"https://doi.org/10.1116/6.0003470","url":null,"abstract":"GaAs(111)B are commercially available substrates widely used for the growth of van der Waals chalcogenide films. Wafer-scale, high-quality crystalline films can be deposited on GaAs(111)B substrates using molecular beam epitaxy. However, two obstacles persist in the use of GaAs(111)B: first, the surface dangling bonds make it challenging for the growth of van der Waals materials; second, the As-terminated surface is prone to aging in air. This study investigated a thermal treatment method for deoxidizing GaAs(111)B substrates while simultaneously passivating the surface dangling bonds with Se. By optimizing the treatment parameters, we obtained a flat and completely deoxidized platform for subsequent film growth, with highly reproducible operations. Furthermore, through first-principle calculations, we find that the most energetically favorable surface of GaAs(111)B after Se passivation consists of 25% As atoms and 75% Se atoms. Finally, we discovered that the common storage method using food-grade vacuum packaging cannot completely prevent substrate aging, and even after thermal treatment, aging still affects subsequent growth. Therefore, we recommend using N2-purged containers for better preservation.","PeriodicalId":282302,"journal":{"name":"Journal of Vacuum Science & Technology B","volume":"94 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140503797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reza Farsad Asadi, T. Zheng, Pao-Chuan Shih, Tomás Palacios, A. Akinwande, B. Gnade
Field emitter arrays (FEAs) have the potential to operate at high frequencies and in harsh environments. However, they have been shown to degrade under oxidizing environments. Studying the effect of O2 on FEAs can help to understand the degradation mechanisms, identify the requirements for vacuum packaging, and estimate the lifetime of the device. In this work, the effect of O2 exposure on 100 × 100 gallium-nitride-field emitter arrays (GaN-FEAs) was studied. The GaN-FEAs were operated at 6 × 10−10 Torr with a 1000 V DC anode voltage and a 50 V DC gate voltage, where the anode current was 1 μA and the gate current was ≤4 nA. The devices were exposed to 10−7, 10−6, and 10−5 Torr of O2 for 100 000 L. The anode current dropped by 50% after 300 L and 98% after 100 000 L. It was observed that the degradation depends on the exposure dose, rather than pressure. The devices mostly degrade when they are ON, confirmed by exposing the device to O2 when the gate voltage was off, and also by the relation between the degradation and duty cycle when pulsing the gate. The results of O2 exposure were compared to Ar exposure to determine whether sputtering and changes in the surface geometry were the primary cause of degradation. The results suggest that changes in the work function and surface chemistry are the cause of emission degradation of GaN-FEA induced by O2.
场发射器阵列（FEA）具有在高频和恶劣环境中工作的潜力。然而，事实证明它们在氧化环境下会发生降解。研究氧气对 FEA 的影响有助于了解降解机制、确定真空包装的要求以及估计器件的使用寿命。在这项工作中，研究了氧气暴露对 100 × 100 氮化镓场发射器阵列（GaN-FEAs）的影响。GaN-FEA 在 6 × 10-10 托、1000 V 直流阳极电压和 50 V 直流栅极电压下工作，其中阳极电流为 1 μA，栅极电流为 ≤4 nA。这些器件分别暴露在 10-7、10-6 和 10-5 托的氧气中 100 000 L。300 L 后阳极电流下降了 50%，100 000 L 后下降了 98%。据观察，降解取决于暴露剂量，而不是压力。通过在栅极电压关闭时将器件暴露在氧气中，以及通过脉冲栅极时降解与占空比之间的关系，证实了器件主要在导通时降解。将暴露在氧气中的结果与暴露在氩气中的结果进行比较，以确定溅射和表面几何形状的变化是否是降解的主要原因。结果表明，功函数和表面化学的变化是二氧化氮诱导 GaN-FEA 发射降解的原因。
{"title":"Degradation of GaN field emitter arrays induced by O2 exposure","authors":"Reza Farsad Asadi, T. Zheng, Pao-Chuan Shih, Tomás Palacios, A. Akinwande, B. Gnade","doi":"10.1116/6.0003314","DOIUrl":"https://doi.org/10.1116/6.0003314","url":null,"abstract":"Field emitter arrays (FEAs) have the potential to operate at high frequencies and in harsh environments. However, they have been shown to degrade under oxidizing environments. Studying the effect of O2 on FEAs can help to understand the degradation mechanisms, identify the requirements for vacuum packaging, and estimate the lifetime of the device. In this work, the effect of O2 exposure on 100 × 100 gallium-nitride-field emitter arrays (GaN-FEAs) was studied. The GaN-FEAs were operated at 6 × 10−10 Torr with a 1000 V DC anode voltage and a 50 V DC gate voltage, where the anode current was 1 μA and the gate current was ≤4 nA. The devices were exposed to 10−7, 10−6, and 10−5 Torr of O2 for 100 000 L. The anode current dropped by 50% after 300 L and 98% after 100 000 L. It was observed that the degradation depends on the exposure dose, rather than pressure. The devices mostly degrade when they are ON, confirmed by exposing the device to O2 when the gate voltage was off, and also by the relation between the degradation and duty cycle when pulsing the gate. The results of O2 exposure were compared to Ar exposure to determine whether sputtering and changes in the surface geometry were the primary cause of degradation. The results suggest that changes in the work function and surface chemistry are the cause of emission degradation of GaN-FEA induced by O2.","PeriodicalId":282302,"journal":{"name":"Journal of Vacuum Science & Technology B","volume":"10 4","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139633517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Staaks, Y. Hsu, Kim Y. Lee, Philip L. Steiner, Zhaoning Yu, Jason J. Wu, S. Xiao, XiaoMin Yang, Thomas Y. Chang
Nanoimprint lithography presents unique opportunities for advanced magnetic storage media with ordered bit arrangements such as bit patterned media or heated dot magnetic recording. Providing sub-10 nm resolution and full disk imprinting capability, UV-nanoimprint lithography based on rigid quartz templates bears the entitlement for patterned recording media manufacturing with high throughput at low cost. However, a key challenge is the fabrication of the high-resolution template that can transfer the desired pattern onto the disk with high fidelity and low line edge roughness. In this article, we present fabrication routes and overcome challenges to the fabrication of quartz templates suitable for self-alignment and guiding purposes to be used for template replication toward full disk imprints. Guiding patterns down to 40 nm pitch are prepared using a rotary electron beam lithography tool. We compare three different process approaches to fabricate an etching mask for patterning the quartz. Two methods target chromium patterning, one with traditional lift-off and another by dry etching, both using an e-beam resist mask. The third approach is based on the development of a carbon-based Tri-layer hard mask. The template pattern profile is optimized for imprint-suitable sidewall angles using dry etching in a CF4/O2 chemistry. The templates were characterized using scanning electron microscopy and atomic force microscopy to evaluate the quality of the transferred pattern as well as line edge roughness. Our results show that the Tri-layer process using carbon resulted in the lowest line edge roughness of ≈0.65 nm at the imprinted disk level. In addition, we show that Tri-layer masking allowed for the use of conventional ZEP e-beam resist and fast writing speeds, while gaining high selectivity during quartz patterning.
{"title":"Nanoimprint lithography guiding templates for advanced magnetic media fabrication","authors":"D. Staaks, Y. Hsu, Kim Y. Lee, Philip L. Steiner, Zhaoning Yu, Jason J. Wu, S. Xiao, XiaoMin Yang, Thomas Y. Chang","doi":"10.1116/6.0003210","DOIUrl":"https://doi.org/10.1116/6.0003210","url":null,"abstract":"Nanoimprint lithography presents unique opportunities for advanced magnetic storage media with ordered bit arrangements such as bit patterned media or heated dot magnetic recording. Providing sub-10 nm resolution and full disk imprinting capability, UV-nanoimprint lithography based on rigid quartz templates bears the entitlement for patterned recording media manufacturing with high throughput at low cost. However, a key challenge is the fabrication of the high-resolution template that can transfer the desired pattern onto the disk with high fidelity and low line edge roughness. In this article, we present fabrication routes and overcome challenges to the fabrication of quartz templates suitable for self-alignment and guiding purposes to be used for template replication toward full disk imprints. Guiding patterns down to 40 nm pitch are prepared using a rotary electron beam lithography tool. We compare three different process approaches to fabricate an etching mask for patterning the quartz. Two methods target chromium patterning, one with traditional lift-off and another by dry etching, both using an e-beam resist mask. The third approach is based on the development of a carbon-based Tri-layer hard mask. The template pattern profile is optimized for imprint-suitable sidewall angles using dry etching in a CF4/O2 chemistry. The templates were characterized using scanning electron microscopy and atomic force microscopy to evaluate the quality of the transferred pattern as well as line edge roughness. Our results show that the Tri-layer process using carbon resulted in the lowest line edge roughness of ≈0.65 nm at the imprinted disk level. In addition, we show that Tri-layer masking allowed for the use of conventional ZEP e-beam resist and fast writing speeds, while gaining high selectivity during quartz patterning.","PeriodicalId":282302,"journal":{"name":"Journal of Vacuum Science & Technology B","volume":"30 2","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139633050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Hausladen, P. Buchner, M. Bartl, M. Bachmann, R. Schreiner
In this work, high-current field emission electron source chips were fabricated using laser-micromachining and MEMS technology. The resulting chips were combined with commercially available printed circuit boards (PCBs) to obtain a multichip electron source. By controlling the separate electron sources using an external current control circuit, we were able to divide the desired total current evenly across the individual chips deployed in the PCB-carrier. In consequence, we were able to show a decreased degradation due to the reduced current load per chip. First, a single electron source chip was measured without current regulation. A steady-state emission current of 1 mA with a high stability of ±1.3% at an extraction voltage of 250 V was observed. At this current level, a mean degradation slope of −0.7 μA/min with a nearly perfect transmission ratio of 99% ± 0.4% was determined. The measurements of a fully assembled multichip PCB-carrier electron source, using a current control circuit for regulation, showed that an even distribution of the desired total current led to a decreased degradation. This was determined by the increase in the required extraction voltage over time. For this purpose, two current levels were applied to the electron source chips of the PCB-carrier using an external current control circuit. First, 300 μA total current was evenly distributed among the individual electron source chips followed by the emission of 300 μA per electron source chip. This allows the observation of the influence of a distributed and nondistributed total current, carried by the electron source chips. Thereby, we obtained an increase in the mean degradation slope from +0.011 V/min (300 μA distributed) to +0.239 V/min (300 μA per chip), which is approximately 21 times higher. Moreover, our current control circuit improved the current stability to under 0.1% for both current levels, 300 μA distributed and 300 μA per chip.
{"title":"Integrated multichip field emission electron source fabricated by laser-micromachining and MEMS technology","authors":"M. Hausladen, P. Buchner, M. Bartl, M. Bachmann, R. Schreiner","doi":"10.1116/6.0003233","DOIUrl":"https://doi.org/10.1116/6.0003233","url":null,"abstract":"In this work, high-current field emission electron source chips were fabricated using laser-micromachining and MEMS technology. The resulting chips were combined with commercially available printed circuit boards (PCBs) to obtain a multichip electron source. By controlling the separate electron sources using an external current control circuit, we were able to divide the desired total current evenly across the individual chips deployed in the PCB-carrier. In consequence, we were able to show a decreased degradation due to the reduced current load per chip. First, a single electron source chip was measured without current regulation. A steady-state emission current of 1 mA with a high stability of ±1.3% at an extraction voltage of 250 V was observed. At this current level, a mean degradation slope of −0.7 μA/min with a nearly perfect transmission ratio of 99% ± 0.4% was determined. The measurements of a fully assembled multichip PCB-carrier electron source, using a current control circuit for regulation, showed that an even distribution of the desired total current led to a decreased degradation. This was determined by the increase in the required extraction voltage over time. For this purpose, two current levels were applied to the electron source chips of the PCB-carrier using an external current control circuit. First, 300 μA total current was evenly distributed among the individual electron source chips followed by the emission of 300 μA per electron source chip. This allows the observation of the influence of a distributed and nondistributed total current, carried by the electron source chips. Thereby, we obtained an increase in the mean degradation slope from +0.011 V/min (300 μA distributed) to +0.239 V/min (300 μA per chip), which is approximately 21 times higher. Moreover, our current control circuit improved the current stability to under 0.1% for both current levels, 300 μA distributed and 300 μA per chip.","PeriodicalId":282302,"journal":{"name":"Journal of Vacuum Science & Technology B","volume":"322 8","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139395175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Room-temperature (RT) photoconductor using mid-wave infrared (MWIR) nanostructured lead selenide (PbSe)/cadmium selenide (CdSe) is presented on a commercially available silicon dioxide on silicon (100) (SiO2/Si) wafer. This device is fabricated through vapor phase deposition (VPD) and subsequently annealed in oxygen to create interconnected nanostructures, which establish efficient pathways for photogenerated carriers and passivate defects within the material. RT specific detectivity (D*) of 8.57 × 108 Jones and a peak D* of 2.49 × 109 Jones are achieved with interband cut-off wavelength of 4 μm. Additionally, the utilization of nanostructured thin film deposition on cost-effective SiO2/Si(100) substrates via the affordable VPD method significantly reduces production costs and facilitates the potential of monolithic integration with Si-based readout integrated circuitry enabling low-cost large-scale production.
{"title":"Room-temperature nanostructured PbSe/CdSe mid-infrared photodetector: Annealing effects","authors":"Milad Rastkar Mirzaei, Zhisheng Shi","doi":"10.1116/6.0003193","DOIUrl":"https://doi.org/10.1116/6.0003193","url":null,"abstract":"Room-temperature (RT) photoconductor using mid-wave infrared (MWIR) nanostructured lead selenide (PbSe)/cadmium selenide (CdSe) is presented on a commercially available silicon dioxide on silicon (100) (SiO2/Si) wafer. This device is fabricated through vapor phase deposition (VPD) and subsequently annealed in oxygen to create interconnected nanostructures, which establish efficient pathways for photogenerated carriers and passivate defects within the material. RT specific detectivity (D*) of 8.57 × 108 Jones and a peak D* of 2.49 × 109 Jones are achieved with interband cut-off wavelength of 4 μm. Additionally, the utilization of nanostructured thin film deposition on cost-effective SiO2/Si(100) substrates via the affordable VPD method significantly reduces production costs and facilitates the potential of monolithic integration with Si-based readout integrated circuitry enabling low-cost large-scale production.","PeriodicalId":282302,"journal":{"name":"Journal of Vacuum Science & Technology B","volume":"26 44","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139631336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hao Yuan, T. Tiedje, Jingye Chen, Hui Wang, Brad Aitchison, Pawan Kumar, Yuxin Song
Polished Cd0.9Zn0.1Te (CZT) single crystals have been exposed to dilute H2S in nitrogen at temperatures from 200 to 280 °C in order to produce a sulfide layer on the surface. The composition of the CZT surfaces before and after H2S exposure has been investigated by photoemission, x-ray absorption, cross-sectional SEM, and spectroscopic ellipsometry. At the highest temperature, H2S exposure removes surface oxides and depletes Te, leaving a CdS surface layer. CdS layers 60 nm thick have been grown with a 2 h exposure to H2S at 280 °C. Surfaces that are initially oxidized through ozone exposure are much more reactive with H2S than unintentionally oxidized surfaces.
{"title":"Growth of CdS heterojunctions on Cd0.9Zn0.1Te single crystals with H2S","authors":"Hao Yuan, T. Tiedje, Jingye Chen, Hui Wang, Brad Aitchison, Pawan Kumar, Yuxin Song","doi":"10.1116/6.0003265","DOIUrl":"https://doi.org/10.1116/6.0003265","url":null,"abstract":"Polished Cd0.9Zn0.1Te (CZT) single crystals have been exposed to dilute H2S in nitrogen at temperatures from 200 to 280 °C in order to produce a sulfide layer on the surface. The composition of the CZT surfaces before and after H2S exposure has been investigated by photoemission, x-ray absorption, cross-sectional SEM, and spectroscopic ellipsometry. At the highest temperature, H2S exposure removes surface oxides and depletes Te, leaving a CdS surface layer. CdS layers 60 nm thick have been grown with a 2 h exposure to H2S at 280 °C. Surfaces that are initially oxidized through ozone exposure are much more reactive with H2S than unintentionally oxidized surfaces.","PeriodicalId":282302,"journal":{"name":"Journal of Vacuum Science & Technology B","volume":"59 23","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139634182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：