Pub Date : 2004-09-27DOI: 10.1109/AGEC.2004.1290868
C. Bailey, H. Lu, C. Yin, S. Stoyanov
The adoption of lead-free interconnection materials and other environmentally friendly materials is causing a number of concerns for electronic package manufacturers. In this paper the methodology and results of using computer modelling to study the reliability of flip chips with lead-free solder, anisotropic conductive adhesive films and isotropic adhesives interconnects are discussed. It is shown that with currently available material data and computer modelling techniques many useful trends in reliability can be predicted and the results can be used to improve the initial product design and speed up the material section process.
{"title":"Modelling the reliability of green electronic interconnects","authors":"C. Bailey, H. Lu, C. Yin, S. Stoyanov","doi":"10.1109/AGEC.2004.1290868","DOIUrl":"https://doi.org/10.1109/AGEC.2004.1290868","url":null,"abstract":"The adoption of lead-free interconnection materials and other environmentally friendly materials is causing a number of concerns for electronic package manufacturers. In this paper the methodology and results of using computer modelling to study the reliability of flip chips with lead-free solder, anisotropic conductive adhesive films and isotropic adhesives interconnects are discussed. It is shown that with currently available material data and computer modelling techniques many useful trends in reliability can be predicted and the results can be used to improve the initial product design and speed up the material section process.","PeriodicalId":291057,"journal":{"name":"2004 International IEEE Conference on the Asian Green Electronics (AGEC). Proceedings of","volume":"24 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124531533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-27DOI: 10.1109/AGEC.2004.1290859
S. Yue
{"title":"Philips our experience in the introduction of leadfree soldering","authors":"S. Yue","doi":"10.1109/AGEC.2004.1290859","DOIUrl":"https://doi.org/10.1109/AGEC.2004.1290859","url":null,"abstract":"","PeriodicalId":291057,"journal":{"name":"2004 International IEEE Conference on the Asian Green Electronics (AGEC). Proceedings of","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115783053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-27DOI: 10.1109/AGEC.2004.1290892
R. Leung
Taiwan has been experiencing good economic growth in the last few decades and electronic industry contributes significantly to the export in recent years. The European and Japanese requirements on electronic products, electrical products and automobile production will put a lot of restrictions on the export items in these areas in the next few years to come. Taiwan government has recognized the need and understood that green products will be able to meet future requirements and compete for global market. Since three years ago, seminar, workshop and international conference have been held to promote green design in Taiwan, especially in the key industries. At the same time, technical publications were produced and relevant design tools were developed to help industries to go for green design or design for environment, design for recycling and so on. The Green Design Network, sponsored by the government, is developed as an information platform to provide information on tools, local and international activities, relevant regulations, design case studies, reference and web sites, promoting organizations and definitions, etc to facilitate the industries to perform green design. The launching of the network is a pilot in Asia and may be expanded in future to regional and international level.
{"title":"Facilitating DfE in enterprises: the Taiwan Green Design Network","authors":"R. Leung","doi":"10.1109/AGEC.2004.1290892","DOIUrl":"https://doi.org/10.1109/AGEC.2004.1290892","url":null,"abstract":"Taiwan has been experiencing good economic growth in the last few decades and electronic industry contributes significantly to the export in recent years. The European and Japanese requirements on electronic products, electrical products and automobile production will put a lot of restrictions on the export items in these areas in the next few years to come. Taiwan government has recognized the need and understood that green products will be able to meet future requirements and compete for global market. Since three years ago, seminar, workshop and international conference have been held to promote green design in Taiwan, especially in the key industries. At the same time, technical publications were produced and relevant design tools were developed to help industries to go for green design or design for environment, design for recycling and so on. The Green Design Network, sponsored by the government, is developed as an information platform to provide information on tools, local and international activities, relevant regulations, design case studies, reference and web sites, promoting organizations and definitions, etc to facilitate the industries to perform green design. The launching of the network is a pilot in Asia and may be expanded in future to regional and international level.","PeriodicalId":291057,"journal":{"name":"2004 International IEEE Conference on the Asian Green Electronics (AGEC). Proceedings of","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123646620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-27DOI: 10.1109/AGEC.2004.1290873
Z. Jinsong, Wu Feng-shun, Wang Lei, Wu Yiping
Pb-free solders will replace traditional Sn-Pb solders to correspond with the green-packaging strategy. In this paper, a 2D model was presented to study the electromigration (EM) in Pb-free solder joints (Sn-Ag-Cu). Some geometry patterns of Cu thin films were designed and interconnected with Pb-free solder joints. The current density distribution in the special geometry pattern interconnect was analyzed with ANASYS. And then the testing data were obtained to compare with the simulation results. Numerical simulation showed that current density crowding occurred because of the interconnect geometry changes, which resulted in inhomogeneous drift of metal atoms. For a given geometry Pb-free interconnect, it was found that voids nucleated at the IMC interface where current density was crowding excessively and propagated along the current-density gradient direction. In the meantime, some hillocks were observed at the IMC interface of the anode. In addition, IMCs dissolved at the cathode or formed at the anode, of those whose boundary migrated in the EM process. Those phenomena were fully accorded with the prediction from simulation results. Finally, EM driving forces were applied to explain these phenomena.
{"title":"Effect of current density and geometry structure on Pb-free solder joints electromigration","authors":"Z. Jinsong, Wu Feng-shun, Wang Lei, Wu Yiping","doi":"10.1109/AGEC.2004.1290873","DOIUrl":"https://doi.org/10.1109/AGEC.2004.1290873","url":null,"abstract":"Pb-free solders will replace traditional Sn-Pb solders to correspond with the green-packaging strategy. In this paper, a 2D model was presented to study the electromigration (EM) in Pb-free solder joints (Sn-Ag-Cu). Some geometry patterns of Cu thin films were designed and interconnected with Pb-free solder joints. The current density distribution in the special geometry pattern interconnect was analyzed with ANASYS. And then the testing data were obtained to compare with the simulation results. Numerical simulation showed that current density crowding occurred because of the interconnect geometry changes, which resulted in inhomogeneous drift of metal atoms. For a given geometry Pb-free interconnect, it was found that voids nucleated at the IMC interface where current density was crowding excessively and propagated along the current-density gradient direction. In the meantime, some hillocks were observed at the IMC interface of the anode. In addition, IMCs dissolved at the cathode or formed at the anode, of those whose boundary migrated in the EM process. Those phenomena were fully accorded with the prediction from simulation results. Finally, EM driving forces were applied to explain these phenomena.","PeriodicalId":291057,"journal":{"name":"2004 International IEEE Conference on the Asian Green Electronics (AGEC). Proceedings of","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132219755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-27DOI: 10.1109/AGEC.2004.1290877
M. Sham, Jang‐Kyo Kim, R.S.W. Lee, Jingshen Wu, M. Yuen
Of fundamental importance to enhance the reliability of flip chip on board (FCOB) packages is to avoid the initiation and propagation of various interfacial failures, and therefore, robust interfacial bonds between the underfill and other components are highly desired. In the present study, the interfacial bond strengths of both conventional and no-flow underfill resins with die passivation, eutectic solder and epoxy solder mask are measured using the button shear test. It is found that the interfacial bond strength of the underfill with the eutectic solder is far weaker than of other interfaces. The degradation of underfill bond strength with silicon nitride passivation, eutectic solder and polymeric solder mask surfaces is enhanced in the presence of solder flux, and cleaning the fluxed surface with a saponifier is an efficient means to restore the original interfacial adhesion. The necessity of post-solder reflow cleaning is shown by performing thermal cycle tests on FCOB packages with different extents of flux residue. Distinctive solder failure behaviors are observed for the packages with and without post-solder reflow cleaning from the cross-sectional analysis.
{"title":"Effects of underfill adhesion on flip chip package reliability","authors":"M. Sham, Jang‐Kyo Kim, R.S.W. Lee, Jingshen Wu, M. Yuen","doi":"10.1109/AGEC.2004.1290877","DOIUrl":"https://doi.org/10.1109/AGEC.2004.1290877","url":null,"abstract":"Of fundamental importance to enhance the reliability of flip chip on board (FCOB) packages is to avoid the initiation and propagation of various interfacial failures, and therefore, robust interfacial bonds between the underfill and other components are highly desired. In the present study, the interfacial bond strengths of both conventional and no-flow underfill resins with die passivation, eutectic solder and epoxy solder mask are measured using the button shear test. It is found that the interfacial bond strength of the underfill with the eutectic solder is far weaker than of other interfaces. The degradation of underfill bond strength with silicon nitride passivation, eutectic solder and polymeric solder mask surfaces is enhanced in the presence of solder flux, and cleaning the fluxed surface with a saponifier is an efficient means to restore the original interfacial adhesion. The necessity of post-solder reflow cleaning is shown by performing thermal cycle tests on FCOB packages with different extents of flux residue. Distinctive solder failure behaviors are observed for the packages with and without post-solder reflow cleaning from the cross-sectional analysis.","PeriodicalId":291057,"journal":{"name":"2004 International IEEE Conference on the Asian Green Electronics (AGEC). Proceedings of","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133824770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-27DOI: 10.1109/AGEC.2004.1290889
U.C. Pandey, V.C. Sethi, K. Schischke, H. Griese, H. Reichl
During the 1990s electronics has assumed the role of providing a forceful leverage to the socio-economic and technological growth of developing society. The initial thinking that the IT & electronics manufacturing activities, involving high technologies would be clean and free from pollution problems, is no more valid today. As the electronics industry rapidly expanded it became evident that the diversity of the industry and its products could cause considerable environmental damage if not properly managed. The major impacts include pollution from manufacturing, waste disposal and use of toxic materials and chemicals that can cause damage to water, soil and air eventually polluting our Oceans and our Planet. In order to ameliorate the environmental impact from the hazardous processes and products, the IT & electronics sector has to adopt increased environmental safety standards. A systematic and integrated approach to environmental management is thus inescapable in the long run. Department of Information Technology in collaboration with United Nationals Development Programme (UNDP) has drawn up a National Programme on "Environmental Management in Semiconductor and Printed Circuit Board Industry in India" to foster environmental management and pollution prevention in Indian Electronics and IT industry. The implementation of this programme has been supported by National and International partners, such as Fraunhofer IZM, Germany, by training and consultancy, US EPA and industry in USA & Europe in providing the information about cleaner production technologies being practiced. The topic will be presented with two papers: Part I describes the Indian initiative on cleaner production technologies in communication, information and electronics sector, objectives and scope of the DIT project. The results of phase I activities of the DIT project cover the survey findings according to the general framework of electronics manufacturing in India and the role of domestic electronics industry in global supply chains. The technological status of electronics manufacturing and the main environmental aspects to be addressed are specified. Best available technologies and practices in Indian context are analyzed in detail. Best practice case studies presented in the paper cover examples from PCB and semiconductor industry. The case studies comprise material flow analysis for these specific technologies and environmental assessment. The part I paper concludes with an outlook on phase II activities of the DIT project.
{"title":"Environmental management in semiconductor and printed circuit board industry in India. Part I: Survey results and case studies","authors":"U.C. Pandey, V.C. Sethi, K. Schischke, H. Griese, H. Reichl","doi":"10.1109/AGEC.2004.1290889","DOIUrl":"https://doi.org/10.1109/AGEC.2004.1290889","url":null,"abstract":"During the 1990s electronics has assumed the role of providing a forceful leverage to the socio-economic and technological growth of developing society. The initial thinking that the IT & electronics manufacturing activities, involving high technologies would be clean and free from pollution problems, is no more valid today. As the electronics industry rapidly expanded it became evident that the diversity of the industry and its products could cause considerable environmental damage if not properly managed. The major impacts include pollution from manufacturing, waste disposal and use of toxic materials and chemicals that can cause damage to water, soil and air eventually polluting our Oceans and our Planet. In order to ameliorate the environmental impact from the hazardous processes and products, the IT & electronics sector has to adopt increased environmental safety standards. A systematic and integrated approach to environmental management is thus inescapable in the long run. Department of Information Technology in collaboration with United Nationals Development Programme (UNDP) has drawn up a National Programme on \"Environmental Management in Semiconductor and Printed Circuit Board Industry in India\" to foster environmental management and pollution prevention in Indian Electronics and IT industry. The implementation of this programme has been supported by National and International partners, such as Fraunhofer IZM, Germany, by training and consultancy, US EPA and industry in USA & Europe in providing the information about cleaner production technologies being practiced. The topic will be presented with two papers: Part I describes the Indian initiative on cleaner production technologies in communication, information and electronics sector, objectives and scope of the DIT project. The results of phase I activities of the DIT project cover the survey findings according to the general framework of electronics manufacturing in India and the role of domestic electronics industry in global supply chains. The technological status of electronics manufacturing and the main environmental aspects to be addressed are specified. Best available technologies and practices in Indian context are analyzed in detail. Best practice case studies presented in the paper cover examples from PCB and semiconductor industry. The case studies comprise material flow analysis for these specific technologies and environmental assessment. The part I paper concludes with an outlook on phase II activities of the DIT project.","PeriodicalId":291057,"journal":{"name":"2004 International IEEE Conference on the Asian Green Electronics (AGEC). Proceedings of","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115191403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-27DOI: 10.1109/AGEC.2004.1290874
Wu Feng-shun, Chen Li, Wu Boyi, Wu Yiping
In this paper, the effects of heating factor on the geometry size of unrestricted lead-free joints were investigated. The morphologies of IMC formed in the joint were studied in detail by using SEM and EDX. When the Sn3.5Ag0.5Cu solder joint was formed in unrestricted condition, the width of the joint and the mean thickness of interfacial IMC increased with the increase of heating factor. The volume of the joint was larger than the volume of the Sn3.5Ag0.5Cu solder, but the effects of heating factor on the change of volume were undulate. The morphologies of the interfacial IMC were needle-like when heating factor was small, and then, grew, coarsened when heating factor increased. The tensile fractography of the joint indicated that the morphologies of IMC at fracture surface were various. Some of IMCs shaped like pyramid, and some of IMCs shaped like needle. And part of the fracture surface located in the solder, and part of the fracture surface located at the interface between the interfacial IMC and solder.
{"title":"Effects of heating factors on the geometry size of unrestricted lead-free joints","authors":"Wu Feng-shun, Chen Li, Wu Boyi, Wu Yiping","doi":"10.1109/AGEC.2004.1290874","DOIUrl":"https://doi.org/10.1109/AGEC.2004.1290874","url":null,"abstract":"In this paper, the effects of heating factor on the geometry size of unrestricted lead-free joints were investigated. The morphologies of IMC formed in the joint were studied in detail by using SEM and EDX. When the Sn3.5Ag0.5Cu solder joint was formed in unrestricted condition, the width of the joint and the mean thickness of interfacial IMC increased with the increase of heating factor. The volume of the joint was larger than the volume of the Sn3.5Ag0.5Cu solder, but the effects of heating factor on the change of volume were undulate. The morphologies of the interfacial IMC were needle-like when heating factor was small, and then, grew, coarsened when heating factor increased. The tensile fractography of the joint indicated that the morphologies of IMC at fracture surface were various. Some of IMCs shaped like pyramid, and some of IMCs shaped like needle. And part of the fracture surface located in the solder, and part of the fracture surface located at the interface between the interfacial IMC and solder.","PeriodicalId":291057,"journal":{"name":"2004 International IEEE Conference on the Asian Green Electronics (AGEC). Proceedings of","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123868752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-27DOI: 10.1109/AGEC.2004.1290910
I. Watanabe, T. Fujinawa, M. Arifuku, K. Kobayashi, Y. Gotoh
Anisotropic conductive films(ACFs) consists of conducting particles and adhesive resins and have been widely used for packaging technologies in FPDs(Flat panel displays) such as LCDs(Liquid crystal displays) for last decades. So far various packaging technologies such as TCP(Tape carrier package) on LCD panel or PWB(Printed wiring board), COF(Chip on flex) on LCD panel or PWB and COG(Chip on Glass) using ACFs have been realized to meet the requirement of fine pitch capability and make the flat panel displays smaller, lighter and thinner. In order to meet the requirement of finer pitch interconnection of outer lead of TCP in LCD packaging technologies, the influence of conducting particles on contact resistance of ACF joints was investigated. It was found that the 50 micron pitch of outer lead interconnection of TCP is realized by optimizing the hardness of conducting particles. In addition, to meet fine pitch capability smaller than 50 micron pitch, the improvement of the adhesion characteristics against COF has been demonstrated in outer lead interconnection. It was confirmed that making conducting particles smaller is advantageous for the driver IC with small bump size and space in COG. Low temperature curable ACF using new curing system which cross-links at 140 degrees C in 10 sec bonding has been demonstrated in TCP/PWB interconnection.
{"title":"Recent advances of interconnection technologies using anisotropic conductive films","authors":"I. Watanabe, T. Fujinawa, M. Arifuku, K. Kobayashi, Y. Gotoh","doi":"10.1109/AGEC.2004.1290910","DOIUrl":"https://doi.org/10.1109/AGEC.2004.1290910","url":null,"abstract":"Anisotropic conductive films(ACFs) consists of conducting particles and adhesive resins and have been widely used for packaging technologies in FPDs(Flat panel displays) such as LCDs(Liquid crystal displays) for last decades. So far various packaging technologies such as TCP(Tape carrier package) on LCD panel or PWB(Printed wiring board), COF(Chip on flex) on LCD panel or PWB and COG(Chip on Glass) using ACFs have been realized to meet the requirement of fine pitch capability and make the flat panel displays smaller, lighter and thinner. In order to meet the requirement of finer pitch interconnection of outer lead of TCP in LCD packaging technologies, the influence of conducting particles on contact resistance of ACF joints was investigated. It was found that the 50 micron pitch of outer lead interconnection of TCP is realized by optimizing the hardness of conducting particles. In addition, to meet fine pitch capability smaller than 50 micron pitch, the improvement of the adhesion characteristics against COF has been demonstrated in outer lead interconnection. It was confirmed that making conducting particles smaller is advantageous for the driver IC with small bump size and space in COG. Low temperature curable ACF using new curing system which cross-links at 140 degrees C in 10 sec bonding has been demonstrated in TCP/PWB interconnection.","PeriodicalId":291057,"journal":{"name":"2004 International IEEE Conference on the Asian Green Electronics (AGEC). Proceedings of","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125102304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-27DOI: 10.1109/AGEC.2004.1290890
K. Schischke, U.C. Pandey, V.C. Sethi, H. Griese, H. Reichl
Part II of the paper on "environmental management in semiconductor and printed circuit board industry in India" sets the focus on benchmarking of the survey results and international best practice sharing. Environmental issues have got different priorities in different regions of the world. Also the general framework for the economy, open-mindedness for an appropriate environmental management and the approaches necessary to tackle environmental problems are specific for different regions. The part II paper compares the different background of Europe and India for implementing environmental management. The intermediary results of the DIT project are set in a global context through a benchmark analysis based on research and development activities of Fraunhofer IZM with European electronics industry. The importance of international know-how exchange to learn from each others' technological and environmental expertise is shown.
{"title":"Environmental management in semiconductor and printed circuit board industry in India - part II: benchmarking and international best practice sharing","authors":"K. Schischke, U.C. Pandey, V.C. Sethi, H. Griese, H. Reichl","doi":"10.1109/AGEC.2004.1290890","DOIUrl":"https://doi.org/10.1109/AGEC.2004.1290890","url":null,"abstract":"Part II of the paper on \"environmental management in semiconductor and printed circuit board industry in India\" sets the focus on benchmarking of the survey results and international best practice sharing. Environmental issues have got different priorities in different regions of the world. Also the general framework for the economy, open-mindedness for an appropriate environmental management and the approaches necessary to tackle environmental problems are specific for different regions. The part II paper compares the different background of Europe and India for implementing environmental management. The intermediary results of the DIT project are set in a global context through a benchmark analysis based on research and development activities of Fraunhofer IZM with European electronics industry. The importance of international know-how exchange to learn from each others' technological and environmental expertise is shown.","PeriodicalId":291057,"journal":{"name":"2004 International IEEE Conference on the Asian Green Electronics (AGEC). Proceedings of","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128628954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-27DOI: 10.1109/AGEC.2004.1290897
Y. Sohn, Jin Yu, S.K. Kang, D. Shih, Taek-Yeong Lee
Intermetallic compound (IMC) spalling from electroless Ni-P film was investigated with lead-free solders (Sn-3.5 wt.% Ag and pure Sn) in terms of solder deposition method (electroplating, solder paste and solder preform) and P content in Ni-P layer (4.6, 9, and 13 wt.% P). The reaction of Ni-P with Sn3.5Ag paste easily led to IMC spalling after 2min reflow at 250 /spl deg/C while IMCs adhered to the Ni-P layer after 10min reflow with electroplated Sri or Sn3.5Ag. The IMC spalling in Sn3.5Ag preform was moderate. The spalling increased with P content in the Ni-P layer. Ni/sub 3/Sn/sub 4/ intermetallics formed as a needle-shaped morphology in an early stage and changed into a chunky shape. Needle-shaped compounds exhibited a higher propensity for spalling from the Ni-P layer than the chunky shaped because a molten solder can easily penetrate into the interface between the needle-shaped IMCs and the P-rich layer. A reaction between the penetrated Sn and the P-rich layer formed a NiSnP layer. The poor adhesion between the Ni/sub 3/Sn/sub 4/ compound and the NiSnP layer is attributed to the IMC spalling. Dewetting of solder from the NiSnP layer, however, didn't occur even after spalling of most IMCs.
{"title":"Spalling behaviors of intermetallic compounds during the wetting reaction of Sn(3.5Ag) on electroless Ni-P metallization","authors":"Y. Sohn, Jin Yu, S.K. Kang, D. Shih, Taek-Yeong Lee","doi":"10.1109/AGEC.2004.1290897","DOIUrl":"https://doi.org/10.1109/AGEC.2004.1290897","url":null,"abstract":"Intermetallic compound (IMC) spalling from electroless Ni-P film was investigated with lead-free solders (Sn-3.5 wt.% Ag and pure Sn) in terms of solder deposition method (electroplating, solder paste and solder preform) and P content in Ni-P layer (4.6, 9, and 13 wt.% P). The reaction of Ni-P with Sn3.5Ag paste easily led to IMC spalling after 2min reflow at 250 /spl deg/C while IMCs adhered to the Ni-P layer after 10min reflow with electroplated Sri or Sn3.5Ag. The IMC spalling in Sn3.5Ag preform was moderate. The spalling increased with P content in the Ni-P layer. Ni/sub 3/Sn/sub 4/ intermetallics formed as a needle-shaped morphology in an early stage and changed into a chunky shape. Needle-shaped compounds exhibited a higher propensity for spalling from the Ni-P layer than the chunky shaped because a molten solder can easily penetrate into the interface between the needle-shaped IMCs and the P-rich layer. A reaction between the penetrated Sn and the P-rich layer formed a NiSnP layer. The poor adhesion between the Ni/sub 3/Sn/sub 4/ compound and the NiSnP layer is attributed to the IMC spalling. Dewetting of solder from the NiSnP layer, however, didn't occur even after spalling of most IMCs.","PeriodicalId":291057,"journal":{"name":"2004 International IEEE Conference on the Asian Green Electronics (AGEC). Proceedings of","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126182351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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