Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669451
N. Choudhary, M. Gaur, V. Laxmi, Virendra Singh
Network-on-Chip (NoC) has emerged as a solution for communication framework for high-performance nanoscale architecture. One important aspect, in addition to deadlock-free routing, is low power consumption. In view of varied communication requirements, application specific SoC design is increasingly important. Customized NoC architectures are more suitable for a particular application, and do not necessarily conform to regular topologies. In this work, a methodology using the priori knowledge of the application's communication characteristic for the design of customized and energy optimized irregular NoC is proposed.
{"title":"Energy aware design methodologies for application specific NoC","authors":"N. Choudhary, M. Gaur, V. Laxmi, Virendra Singh","doi":"10.1109/NORCHIP.2010.5669451","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669451","url":null,"abstract":"Network-on-Chip (NoC) has emerged as a solution for communication framework for high-performance nanoscale architecture. One important aspect, in addition to deadlock-free routing, is low power consumption. In view of varied communication requirements, application specific SoC design is increasingly important. Customized NoC architectures are more suitable for a particular application, and do not necessarily conform to regular topologies. In this work, a methodology using the priori knowledge of the application's communication characteristic for the design of customized and energy optimized irregular NoC is proposed.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124220102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669477
M. Straka, Jan Kastil, Z. Kotásek
In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented.
{"title":"Generic partial dynamic reconfiguration controller for fault tolerant designs based on FPGA","authors":"M. Straka, Jan Kastil, Z. Kotásek","doi":"10.1109/NORCHIP.2010.5669477","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669477","url":null,"abstract":"In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132889378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669483
B. Jonsson
The influence of CMOS scaling on A/D-converter performance is investigated by observing the entire body of experimental CMOS ADCs reported in IEEE journals and conferences central to the field from 1976 to 2010. Based on the near-exhaustive set of scientific data, empirically observed scaling trends are derived for performance in terms of noisefloor, speed and resolution, as well as for power efficiency expressed by two commonly used figures-of-merit. The trends are used to estimate limits on the achievable ADC performance in nanometer CMOS technologies, with implications for LTE and WCDMA infrastructure applications particularly highlighted.
{"title":"On CMOS scaling and A/D-converter performance","authors":"B. Jonsson","doi":"10.1109/NORCHIP.2010.5669483","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669483","url":null,"abstract":"The influence of CMOS scaling on A/D-converter performance is investigated by observing the entire body of experimental CMOS ADCs reported in IEEE journals and conferences central to the field from 1976 to 2010. Based on the near-exhaustive set of scientific data, empirically observed scaling trends are derived for performance in terms of noisefloor, speed and resolution, as well as for power efficiency expressed by two commonly used figures-of-merit. The trends are used to estimate limits on the achievable ADC performance in nanometer CMOS technologies, with implications for LTE and WCDMA infrastructure applications particularly highlighted.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129260929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669446
V. Laxmi, Roopesh Chuggani, M. Gaur, P. Khandelwal, Prateek Bansal
NoC (Network on Chip) is an emerging paradigm for design of VLSI/ULSI circuits to overcome communication bottleneck of traditional bus based systems. NoC communication framework consists of regularly placed routers, which are connected to processing cores. NoC performance is determined by latency and throughput for communication requirements. NoC communication traffic modelling plays an important role in design of NoC simulators and/or prototypes. This paper presents a framework for modelling source traffic for multipoint communication from one source to different destinations as is required for multicasting. Such a traffic model captures real-world scenarios such as multicasting, execution of concurrent multiple tasks on a single core (each task requiring communication with different destinations). The model proposes how concurrent traffic streams from a single core to different destinations can be mathematically characterized as a single stream at source end. The model is derived from statistical behaviour of probabilistically demultiplexing of a single traffic stream. In its nascent stage, the method is proposed for a scenario of one source concurrently communicating with two destinations as shall be required for mapping two concurrent tasks to same core or simultaneous broadcast to two destinations.
片上网络(Network on Chip, NoC)是克服传统总线通信瓶颈的VLSI/ULSI电路设计新范式。NoC通信框架由固定放置的路由器组成，这些路由器连接到处理核心。NoC性能由通信需求的延迟和吞吐量决定。NoC通信流量建模在NoC仿真器和/或原型设计中起着重要的作用。本文提出了一种用于多播所需的从一个源到不同目的地的多点通信的源流量建模框架。这样的流量模型捕获了诸如多播、在单个核心上执行并发的多个任务(每个任务需要与不同的目的地通信)等现实场景。该模型提出了从单个核心到不同目的地的并发流量如何在数学上表征为源端的单个流。该模型是根据单流量概率解复用的统计行为推导出来的。在初始阶段，针对将两个并发任务映射到同一个核心或同时广播到两个目标所需要的一个源与两个目标同时通信的场景，提出了该方法。
{"title":"Traffic characterization for multicasting in NoC","authors":"V. Laxmi, Roopesh Chuggani, M. Gaur, P. Khandelwal, Prateek Bansal","doi":"10.1109/NORCHIP.2010.5669446","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669446","url":null,"abstract":"NoC (Network on Chip) is an emerging paradigm for design of VLSI/ULSI circuits to overcome communication bottleneck of traditional bus based systems. NoC communication framework consists of regularly placed routers, which are connected to processing cores. NoC performance is determined by latency and throughput for communication requirements. NoC communication traffic modelling plays an important role in design of NoC simulators and/or prototypes. This paper presents a framework for modelling source traffic for multipoint communication from one source to different destinations as is required for multicasting. Such a traffic model captures real-world scenarios such as multicasting, execution of concurrent multiple tasks on a single core (each task requiring communication with different destinations). The model proposes how concurrent traffic streams from a single core to different destinations can be mathematically characterized as a single stream at source end. The model is derived from statistical behaviour of probabilistically demultiplexing of a single traffic stream. In its nascent stage, the method is proposed for a scenario of one source concurrently communicating with two destinations as shall be required for mapping two concurrent tasks to same core or simultaneous broadcast to two destinations.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125913763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669459
A. Jalili, S. Sayedi, J. Wikner, N. Andersson, M. Vesterbacka
In this paper we present a calibration technique for sigma-delta analog-to-digital converters (ΣΔADC) in which high-speed, low-resolution flash subADCs are used. The calibration technique as such is mainly targeting calibration of the flash subADC, but we also study how the correction depends on where in the ΣΔ modulator the calibration signals are applied.
{"title":"Calibration of ΣΔ analog-to-digital converters based on histogram test methods","authors":"A. Jalili, S. Sayedi, J. Wikner, N. Andersson, M. Vesterbacka","doi":"10.1109/NORCHIP.2010.5669459","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669459","url":null,"abstract":"In this paper we present a calibration technique for sigma-delta analog-to-digital converters (ΣΔADC) in which high-speed, low-resolution flash subADCs are used. The calibration technique as such is mainly targeting calibration of the flash subADC, but we also study how the correction depends on where in the ΣΔ modulator the calibration signals are applied.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114291200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669436
M. A. Shami, A. Hemani
An improved Dynamic, Partial and self reconfigurable interconnection network (Hybrid-2 Network) is presented for Dynamically Reprogrammable Resource Array (DRRA), which is a Coarse Grain Reconfiguration Architecture (CGRA). To justify the design decision, Hybrid-2 network implementation is compared against the possible implementations using Multiplexer, NoC, Crossbar and already published Hybrid-1 interconnection network. Results shows that newly presented Hybrid-2 Interconnection network take (1.08x, 0.104x, 0.212x and 0.681x) the area, (1x, 0.037x, 0.026x and 0.107x) the configuration bits of Multiplexer, NoC, Crossbar and Hybrid-1 Implementation respectively. Hybrid-2 network is also 2.87x and 5.86x faster than Multiplexer and Hybrid-1 networks.
{"title":"An improved self-reconfigurable interconnection scheme for a Coarse Grain Reconfigurable Architecture","authors":"M. A. Shami, A. Hemani","doi":"10.1109/NORCHIP.2010.5669436","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669436","url":null,"abstract":"An improved Dynamic, Partial and self reconfigurable interconnection network (Hybrid-2 Network) is presented for Dynamically Reprogrammable Resource Array (DRRA), which is a Coarse Grain Reconfiguration Architecture (CGRA). To justify the design decision, Hybrid-2 network implementation is compared against the possible implementations using Multiplexer, NoC, Crossbar and already published Hybrid-1 interconnection network. Results shows that newly presented Hybrid-2 Interconnection network take (1.08x, 0.104x, 0.212x and 0.681x) the area, (1x, 0.037x, 0.026x and 0.107x) the configuration bits of Multiplexer, NoC, Crossbar and Hybrid-1 Implementation respectively. Hybrid-2 network is also 2.87x and 5.86x faster than Multiplexer and Hybrid-1 networks.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133653376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669465
T. Taniguchi, Kazuya Kojima, A. Matsuzawa, K. Matsunaga, Y. Hirachi
Since 2008, we have been developing the integrated SoC, which incorporates from the ultra high speed multi-level QAM modem to the gigabit Ethernet interface, in a bid to adapt to the millimeter wave broadband wireless system. In 2009, we developed the SoC that functions on its maximum modulation clock 200 MHz, single-carrier 16QAM, and TDD, and managed to conduct field evaluation tests as a state of actual operation of 38 GHz band P-P FWA system. This time, we have increased the resolution of ADC/DAC incorporated in the SoC, and made design improvements to suppress the internal clock jitter, and finally managed to develop a prototype SoC for the wireless system, which enables 64QAM operations (on architecture of the modem, maximum multi-level is 256QAM) and also actualized an effective throughput of 1 Gbps.
{"title":"Developments of the SoC for high-multi-level QAM 1 Gbps class wireless system and its evaluation with RF hardware of 38 GHz band FWA","authors":"T. Taniguchi, Kazuya Kojima, A. Matsuzawa, K. Matsunaga, Y. Hirachi","doi":"10.1109/NORCHIP.2010.5669465","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669465","url":null,"abstract":"Since 2008, we have been developing the integrated SoC, which incorporates from the ultra high speed multi-level QAM modem to the gigabit Ethernet interface, in a bid to adapt to the millimeter wave broadband wireless system. In 2009, we developed the SoC that functions on its maximum modulation clock 200 MHz, single-carrier 16QAM, and TDD, and managed to conduct field evaluation tests as a state of actual operation of 38 GHz band P-P FWA system. This time, we have increased the resolution of ADC/DAC incorporated in the SoC, and made design improvements to suppress the internal clock jitter, and finally managed to develop a prototype SoC for the wireless system, which enables 64QAM operations (on architecture of the modem, maximum multi-level is 256QAM) and also actualized an effective throughput of 1 Gbps.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125173667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669454
Bo Yang, L. Guang, T. Xu, A. Yin, T. Santti, J. Plosila
Massive parallel computing performed on many-core Network-on-Chips (NoCs) is the future of the computing. One feasible approach to implement parallel computing is to deploy multiple applications on the NoC simultaneously. In this paper, we propose a multi-application mapping method starting with the application mapping which finds a region on the NoC for each application and then task mapping which maps all tasks of the application into each region. In the application mapping step, several strategies based on the maximal empty rectangle (MER) technique are introduced for finding an optimal region for each application. In the task mapping step, a tree-model based algorithm is used with the purpose of reducing the communication latency and energy consumption. The experiment results show that the proposed method can achieve considerable reduction of network latency and energy consumption (up to 18%) for a given set of applications.
{"title":"Multi-application multi-step mapping method for many-core Network-on-Chips","authors":"Bo Yang, L. Guang, T. Xu, A. Yin, T. Santti, J. Plosila","doi":"10.1109/NORCHIP.2010.5669454","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669454","url":null,"abstract":"Massive parallel computing performed on many-core Network-on-Chips (NoCs) is the future of the computing. One feasible approach to implement parallel computing is to deploy multiple applications on the NoC simultaneously. In this paper, we propose a multi-application mapping method starting with the application mapping which finds a region on the NoC for each application and then task mapping which maps all tasks of the application into each region. In the application mapping step, several strategies based on the maximal empty rectangle (MER) technique are introduced for finding an optimal region for each application. In the task mapping step, a tree-model based algorithm is used with the purpose of reducing the communication latency and energy consumption. The experiment results show that the proposed method can achieve considerable reduction of network latency and energy consumption (up to 18%) for a given set of applications.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133806189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669468
P. Santos, J. Canas Ferreira
This paper describes an FPGA-based system capable of computing the distance of objects in a scene to two stereo cameras, and use that information to isolate objects in the foreground. For this purpose, four disparity maps are generated in real time, according to different similarity metrics and sweep directions, and then merged into a single foreground-versus-background bitmap. Our main contribution is a custom-built hardware architecture for the disparity map calculation, and an optional post-processing stage that coarsens the output to improve resilience against spurious results. The system was described in Verilog, and a prototype implemented on a Xilinx Virtex-II Pro FPGA proved capable of processing 640×480 black-and-white images at a maximum frame rate of 40 fps, using 3×3 matching windows and detecting disparities of up to 135 pixels.
本文描述了一个基于fpga的系统，该系统能够计算场景中物体到两个立体摄像机的距离，并利用该信息隔离前景中的物体。为此，根据不同的相似度度量和扫描方向，实时生成四个视差图，然后合并为单个前景-背景位图。我们的主要贡献是一个用于视差图计算的定制硬件架构，以及一个可选的后处理阶段，该阶段可以粗化输出以提高对虚假结果的弹性。该系统是用Verilog描述的，在Xilinx Virtex-II Pro FPGA上实现的原型证明能够以最大帧率40 fps处理640×480黑白图像，使用3×3匹配窗口并检测高达135像素的差异。
{"title":"FPGA-based real-time disparity computation and object location","authors":"P. Santos, J. Canas Ferreira","doi":"10.1109/NORCHIP.2010.5669468","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669468","url":null,"abstract":"This paper describes an FPGA-based system capable of computing the distance of objects in a scene to two stereo cameras, and use that information to isolate objects in the foreground. For this purpose, four disparity maps are generated in real time, according to different similarity metrics and sweep directions, and then merged into a single foreground-versus-background bitmap. Our main contribution is a custom-built hardware architecture for the disparity map calculation, and an optional post-processing stage that coarsens the output to improve resilience against spurious results. The system was described in Verilog, and a prototype implemented on a Xilinx Virtex-II Pro FPGA proved capable of processing 640×480 black-and-white images at a maximum frame rate of 40 fps, using 3×3 matching windows and detecting disparities of up to 135 pixels.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134070839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669482
C. Bryant, H. Sjoland
This paper presents an inductorless ultra-low power frontend for applications such as sensor networks and medical implants. By using a completely inductorless topology the chip area is just 0.017mm2, excluding pads. A real input impedance of 300Ω is achieved with current feedback. Manufactured in 65nm CMOS, it measures more than 17dB gain from 100MHz to 2000MHz while consuming only 175µW from a 0.9V supply (The LNA consumes 115µW). The measured noise figure and IIP3 is 11dB and −16.8dBm respectively.
本文提出了一种用于传感器网络和医疗植入物等应用的无电感超低功耗前端。通过使用完全无电感拓扑，芯片面积仅为0.017mm2，不包括焊盘。通过电流反馈实现了真实输入阻抗300Ω。它采用65nm CMOS制造，在100MHz至2000MHz范围内的增益超过17dB，而0.9V电源的功耗仅为175 μ W (LNA功耗为115 μ W)。实测噪声系数和IIP3分别为11dB和- 16.8dBm。
{"title":"A 175µW 100MHz-2GHz inductorless receiver front-end in 65nm CMOS","authors":"C. Bryant, H. Sjoland","doi":"10.1109/NORCHIP.2010.5669482","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669482","url":null,"abstract":"This paper presents an inductorless ultra-low power frontend for applications such as sensor networks and medical implants. By using a completely inductorless topology the chip area is just 0.017mm2, excluding pads. A real input impedance of 300Ω is achieved with current feedback. Manufactured in 65nm CMOS, it measures more than 17dB gain from 100MHz to 2000MHz while consuming only 175µW from a 0.9V supply (The LNA consumes 115µW). The measured noise figure and IIP3 is 11dB and −16.8dBm respectively.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134317611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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