Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669460
M. Sadeghifar, J. Wikner
This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation in order to allocate more energy to higher Nyquist ranges as is commonly done in RF DACs. The interpolation is done in the time domain, such that it approximates the oscillating signal from the RF DAC concept to modulate the signal up to a higher Nyquist range. Then, instead of taking the output from within the Nyquist range, as in conventional case, the output of the DAC is taken from higher images. The proposed architecture looks promising for future implementations in high-speed DACs as it can be used in RF DAC or modified versions of digital-to-RF converters (DRFCs). Simulation results and theoretical descriptions are presented to support the idea.
{"title":"A higher Nyquist-range DAC employing sinusoidal interpolation","authors":"M. Sadeghifar, J. Wikner","doi":"10.1109/NORCHIP.2010.5669460","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669460","url":null,"abstract":"This work discusses a link between two previously reported ideas in high-speed digital-to-analog converter (DAC) design: linear approximation with analog interpolation techniques and an RF DAC concept where oscillatory pulses are used to combine a DAC with an up-conversion mixer. An architecture is proposed where we utilize analog interpolation techniques, but using sinusoidal rather than linear interpolation in order to allocate more energy to higher Nyquist ranges as is commonly done in RF DACs. The interpolation is done in the time domain, such that it approximates the oscillating signal from the RF DAC concept to modulate the signal up to a higher Nyquist range. Then, instead of taking the output from within the Nyquist range, as in conventional case, the output of the DAC is taken from higher images. The proposed architecture looks promising for future implementations in high-speed DACs as it can be used in RF DAC or modified versions of digital-to-RF converters (DRFCs). Simulation results and theoretical descriptions are presented to support the idea.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"31 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128563945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669484
F. Gruian, Martin Schoeberl
In this paper we examine the idea of implementing communicating sequential processes (CSP) constructs on a Java embedded chip multiprocessor (CMP). The approach is intended to reduce the memory bandwidth pressure on the shared memory, by employing a dedicated network-on-chip (NoC). The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. A CMP architecture of three processors is implemented and tested on an FPGA, showing a 15% increase in device area without performance penalties. Compared to shared memory-based communication, our NoC-based solution is between 2.3 and 11.5 times faster, depending on the communication and memory configuration.
{"title":"NoC-based CSP support for a Java chip multiprocessor","authors":"F. Gruian, Martin Schoeberl","doi":"10.1109/NORCHIP.2010.5669484","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669484","url":null,"abstract":"In this paper we examine the idea of implementing communicating sequential processes (CSP) constructs on a Java embedded chip multiprocessor (CMP). The approach is intended to reduce the memory bandwidth pressure on the shared memory, by employing a dedicated network-on-chip (NoC). The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. A CMP architecture of three processors is implemented and tested on an FPGA, showing a 15% increase in device area without performance penalties. Compared to shared memory-based communication, our NoC-based solution is between 2.3 and 11.5 times faster, depending on the communication and memory configuration.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"29 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120932517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669428
L. Guang, Bo Yang, J. Plosila, Khalid Latif, H. Tenhunen
A case study is presented for hierarchical agent monitoring design approach, which provides a high level abstraction for designing monitoring functions on massively parallel and distributed systems. The case study features hierarchical power monitoring on NoC platforms, where each level of agents perform specific monitoring operations based on their granularity. The monitoring hierarchy and operations are specified by a formal language for consistent and non-ambiguous system design. Various benchmarks are mapped onto NoCs, running with hierarchical power monitoring agents. Quantitative evaluations are performed in terms of energy efficiency, communication latency, and silicon overhead.
{"title":"Hierarchical power monitoring on NoC - a case study for hierarchical agent monitoring design approach","authors":"L. Guang, Bo Yang, J. Plosila, Khalid Latif, H. Tenhunen","doi":"10.1109/NORCHIP.2010.5669428","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669428","url":null,"abstract":"A case study is presented for hierarchical agent monitoring design approach, which provides a high level abstraction for designing monitoring functions on massively parallel and distributed systems. The case study features hierarchical power monitoring on NoC platforms, where each level of agents perform specific monitoring operations based on their granularity. The monitoring hierarchy and operations are specified by a formal language for consistent and non-ambiguous system design. Various benchmarks are mapped onto NoCs, running with hierarchical power monitoring agents. Quantitative evaluations are performed in terms of energy efficiency, communication latency, and silicon overhead.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116266525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669470
Trupti B. Salankar, Vilas A. Nitnaware
We describe the methodology; the design and the implementation of scheduler block of interconnect. The scheduler block is implemented in Verilog using SYNOPSYS tool's DVE and Design_vision. The interconnect is capable of handling 72 bit packets and a total of 32 packets at a time. There are total 8 devices and we have to establish the communication between them. Each device consists of an input block and the output block. The input block first receives the 72 bit packet and the total of 32 packets one by one. The input block internally consists of four arrays-destination head, destination tail, packet array and linked list array and also a shift register. It stores the packets in an array called packet array. When scheduler sends transmit request these packets are given to the scheduler. Scheduler internally consists of grant and accept arbiters. Scheduler perform its operation in three steps i.e. request, grant and accept. It works on the principle of i-slip algorithm. Finally the scheduler decides that which packet should be send from the input block to the output block of the device. Output block of the device simply receives the packet. These packets are sent and received in two phases. In the first phase 36 bits are sent and in the second phase 36bits are sent. Thus the connection is established between the devices using interconnect. We are also modifying the scheduler design to reduce the area required for on chip implementation. For this reason we are combining the two sets of arbiters into only one, so the total arbiters required for modified scheduler now reduces to only 8 compared to 16 for original scheduler.
{"title":"SOC chip scheduler embodying I-slip algorithm","authors":"Trupti B. Salankar, Vilas A. Nitnaware","doi":"10.1109/NORCHIP.2010.5669470","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669470","url":null,"abstract":"We describe the methodology; the design and the implementation of scheduler block of interconnect. The scheduler block is implemented in Verilog using SYNOPSYS tool's DVE and Design_vision. The interconnect is capable of handling 72 bit packets and a total of 32 packets at a time. There are total 8 devices and we have to establish the communication between them. Each device consists of an input block and the output block. The input block first receives the 72 bit packet and the total of 32 packets one by one. The input block internally consists of four arrays-destination head, destination tail, packet array and linked list array and also a shift register. It stores the packets in an array called packet array. When scheduler sends transmit request these packets are given to the scheduler. Scheduler internally consists of grant and accept arbiters. Scheduler perform its operation in three steps i.e. request, grant and accept. It works on the principle of i-slip algorithm. Finally the scheduler decides that which packet should be send from the input block to the output block of the device. Output block of the device simply receives the packet. These packets are sent and received in two phases. In the first phase 36 bits are sent and in the second phase 36bits are sent. Thus the connection is established between the devices using interconnect. We are also modifying the scheduler design to reduce the area required for on chip implementation. For this reason we are combining the two sets of arbiters into only one, so the total arbiters required for modified scheduler now reduces to only 8 compared to 16 for original scheduler.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"2022 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114051840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669488
O. Najari, T. Arnborg, A. Alvandpour
This paper presents a wideband inductorless Low Noise Amplifier (LNA) using a technique for canceling 2nd and 3rd order intermodulation products at the same time and hence achieving high second and third order Input Intercept Point (IIP2 and IIP3) at RF and microwave frequencies. The LNA also makes use of noise canceling stage to achieve low noise characteristics and low noise figure in the whole bandwidth. The LNA was designed in 90-nm CMOS process and consists of a shunt feedback common-source input stage to provide wideband input impedance matching, followed by a noise canceling stage. The common source input stage employs two transistors in parallel biased at different operating regions which perform distortion cancellation. IIP2 and IIP3 of the designed LNA are +41dBm and +2.4dBm respectively. The LNA achieved the voltage gain of 17dB while having the noise figure below 2dB from 500MHz–5GHz.
{"title":"Wideband inductorless LNA employing simultaneous 2nd and 3rd order distortion cancellation","authors":"O. Najari, T. Arnborg, A. Alvandpour","doi":"10.1109/NORCHIP.2010.5669488","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669488","url":null,"abstract":"This paper presents a wideband inductorless Low Noise Amplifier (LNA) using a technique for canceling 2nd and 3rd order intermodulation products at the same time and hence achieving high second and third order Input Intercept Point (IIP2 and IIP3) at RF and microwave frequencies. The LNA also makes use of noise canceling stage to achieve low noise characteristics and low noise figure in the whole bandwidth. The LNA was designed in 90-nm CMOS process and consists of a shunt feedback common-source input stage to provide wideband input impedance matching, followed by a noise canceling stage. The common source input stage employs two transistors in parallel biased at different operating regions which perform distortion cancellation. IIP2 and IIP3 of the designed LNA are +41dBm and +2.4dBm respectively. The LNA achieved the voltage gain of 17dB while having the noise figure below 2dB from 500MHz–5GHz.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114054652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669431
Jian Chen, F. Jonsson, Lirong Zheng
This paper presents a practical phase noise measurement approach, which only requires a spectrum analyzer and a computer, featuring fast setups, accurate results and low cost. Not like the conventional methods using extra assistant circuits to get rid of the frequency drift problem, this approach takes advantage of modern spectrum analyzers to acquire IQ data to calculate phase noise. The low quantization noise of the instrument makes this approach suitable for most CMOS integrated oscillators. The IQ data sampling time can be made small enough so that the frequency drift is not so obvious to harm the measurement accuracy. The experimental results clearly demonstrates the accuracy and the effectiveness of this method through measuring phase noise of two voltage controlled oscillators (VCOs) in 180nm CMOS process at 2.6 GHz and 3.0 GHz respectively.
{"title":"A fast and accurate phase noise measurement of free running oscillators using a single spectrum analyzer","authors":"Jian Chen, F. Jonsson, Lirong Zheng","doi":"10.1109/NORCHIP.2010.5669431","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669431","url":null,"abstract":"This paper presents a practical phase noise measurement approach, which only requires a spectrum analyzer and a computer, featuring fast setups, accurate results and low cost. Not like the conventional methods using extra assistant circuits to get rid of the frequency drift problem, this approach takes advantage of modern spectrum analyzers to acquire IQ data to calculate phase noise. The low quantization noise of the instrument makes this approach suitable for most CMOS integrated oscillators. The IQ data sampling time can be made small enough so that the frequency drift is not so obvious to harm the measurement accuracy. The experimental results clearly demonstrates the accuracy and the effectiveness of this method through measuring phase noise of two voltage controlled oscillators (VCOs) in 180nm CMOS process at 2.6 GHz and 3.0 GHz respectively.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132553503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669474
A. Rahmani, P. Liljeberg, J. Plosila, H. Tenhunen
In this paper, a Johnson-encoded Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. The proposed FIFO which can be used to interface modules in Voltage/Frequency Islands (VFI) based Networks-on-chip, is capable of alleviating the excessive energy consumption and high performance overhead of the conventional bi-synchronous FIFOs. The FIFO is scalable and synthesizable in synchronous standard cells. In addition, a technique for mesochronous adaptation of the proposed FIFO is presented. Our extensive experiments show significant power and performance improvements compared to non-reconfigurable architectures.
{"title":"An efficient VFI-based NoC architecture using Johnson-encoded Reconfigurable FIFOs","authors":"A. Rahmani, P. Liljeberg, J. Plosila, H. Tenhunen","doi":"10.1109/NORCHIP.2010.5669474","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669474","url":null,"abstract":"In this paper, a Johnson-encoded Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. The proposed FIFO which can be used to interface modules in Voltage/Frequency Islands (VFI) based Networks-on-chip, is capable of alleviating the excessive energy consumption and high performance overhead of the conventional bi-synchronous FIFOs. The FIFO is scalable and synthesizable in synchronous standard cells. In addition, a technique for mesochronous adaptation of the proposed FIFO is presented. Our extensive experiments show significant power and performance improvements compared to non-reconfigurable architectures.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115438206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669457
M. Baláz
The aim of the presented work is to improve the quality of testing of SoC digital cores surrounded with test wrappers. The paper presents a new effective delay fault test generation method for the transition faults based on the skewed-load test. The generated delay fault test can be applied to a SoC core through a test wrapper architecture with only a simple boundary scan chain. This eliminates the necessity to use an enhanced boundary scan chain for the application of the delay fault test. The effectiveness of the developed method for a transition delay test generation was verified on the set of combinational and sequential circuits. The experiments show a significant reduction of test vector application time.
{"title":"SfW method: Delay test generation for simple chain wrapper architecture","authors":"M. Baláz","doi":"10.1109/NORCHIP.2010.5669457","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669457","url":null,"abstract":"The aim of the presented work is to improve the quality of testing of SoC digital cores surrounded with test wrappers. The paper presents a new effective delay fault test generation method for the transition faults based on the skewed-load test. The generated delay fault test can be applied to a SoC core through a test wrapper architecture with only a simple boundary scan chain. This eliminates the necessity to use an enhanced boundary scan chain for the application of the delay fault test. The effectiveness of the developed method for a transition delay test generation was verified on the set of combinational and sequential circuits. The experiments show a significant reduction of test vector application time.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122851160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669442
Shuo Li, Fahimeh Jafari, A. Hemani, Shashi Kumar
In this paper, Layered Spiral Algorithm (LSA) is proposed for memory-aware application mapping and scheduling onto Network-on-Chip (NoC) based Multi-Processor System-on-Chip (MPSoC). The energy consumption is optimized while keeping high task level parallelism. The experimental evaluation indicates that if memory-awareness is not considered during mapping and scheduling, memory overflows may occur. The underlying problem is also modeled as a Mixed Integer Linear Programming (MILP) problem and solved using an efficient branch-and-bound algorithm to compare optimal solutions with results achieved by LSA. Comparing to MILP solutions, the LSA results demonstrate only about 20% and 12% increase of total communication cost in case of a small and middle size synthetic problem, respectively, while it is order of magnitude faster than the MILP solutions. Therefore, the LSA can find acceptable total communication cost with a low runtime complexity, enabling quick exploration of large design spaces, which is infeasible for exhaustive search.
{"title":"Layered Spiral Algorithm for memory-aware mapping and scheduling on Network-on-Chip","authors":"Shuo Li, Fahimeh Jafari, A. Hemani, Shashi Kumar","doi":"10.1109/NORCHIP.2010.5669442","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669442","url":null,"abstract":"In this paper, Layered Spiral Algorithm (LSA) is proposed for memory-aware application mapping and scheduling onto Network-on-Chip (NoC) based Multi-Processor System-on-Chip (MPSoC). The energy consumption is optimized while keeping high task level parallelism. The experimental evaluation indicates that if memory-awareness is not considered during mapping and scheduling, memory overflows may occur. The underlying problem is also modeled as a Mixed Integer Linear Programming (MILP) problem and solved using an efficient branch-and-bound algorithm to compare optimal solutions with results achieved by LSA. Comparing to MILP solutions, the LSA results demonstrate only about 20% and 12% increase of total communication cost in case of a small and middle size synthetic problem, respectively, while it is order of magnitude faster than the MILP solutions. Therefore, the LSA can find acceptable total communication cost with a low runtime complexity, enabling quick exploration of large design spaces, which is infeasible for exhaustive search.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132632358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669448
Lasse Lehtonen, E. Salminen, T. Hamalainen
This paper analyses the effects of Network-on-Chip (NoC) models written in SystemC on simulation speed. Two Register Transfer Level (RTL) models and Approximately Timed (AT) and Loosely Timed (LT) Transaction Level (TL) models are compared against reference RTL VHDL 2D mesh model. Three different mesh sizes are evaluated using a commercial simulator and OSCI SystemC reference kernel. Studied AT model achieved 13–40x speedup with modest 10% estimation error.
{"title":"Analysis of modeling styles on Network-on-Chip simulation","authors":"Lasse Lehtonen, E. Salminen, T. Hamalainen","doi":"10.1109/NORCHIP.2010.5669448","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669448","url":null,"abstract":"This paper analyses the effects of Network-on-Chip (NoC) models written in SystemC on simulation speed. Two Register Transfer Level (RTL) models and Approximately Timed (AT) and Loosely Timed (LT) Transaction Level (TL) models are compared against reference RTL VHDL 2D mesh model. Three different mesh sizes are evaluated using a commercial simulator and OSCI SystemC reference kernel. Studied AT model achieved 13–40x speedup with modest 10% estimation error.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127180606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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