Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669462
T. Santti, J. Tyystjárvi, J. Plosila
This paper presents a significantly improved strategy for accelerating the method calls in the REALJava coprocessor. The hardware assisted virtual machine architecture is described shortly to provide context for the method call acceleration. The strategy is implemented in an FPGA prototype. It allows measurements of real life performance increase, and validates the whole co-processor concept. The system is intended to be used in embedded environments, with limited CPU performance and memory available to the virtual machine. The co-processor is designed in a highly modular fashion, especially separating the communication from the actual core. This modularity of the design makes the co-processor more reusable and allows system level scalability. This work is a part of a project focusing on design of a hardware accelerated multicore Java Virtual Machine for embedded systems.
{"title":"An improved hardware acceleration scheme for Java method calls","authors":"T. Santti, J. Tyystjárvi, J. Plosila","doi":"10.1109/NORCHIP.2010.5669462","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669462","url":null,"abstract":"This paper presents a significantly improved strategy for accelerating the method calls in the REALJava coprocessor. The hardware assisted virtual machine architecture is described shortly to provide context for the method call acceleration. The strategy is implemented in an FPGA prototype. It allows measurements of real life performance increase, and validates the whole co-processor concept. The system is intended to be used in embedded environments, with limited CPU performance and memory available to the virtual machine. The co-processor is designed in a highly modular fashion, especially separating the communication from the actual core. This modularity of the design makes the co-processor more reusable and allows system level scalability. This work is a part of a project focusing on design of a hardware accelerated multicore Java Virtual Machine for embedded systems.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127922978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669492
A. Rantala, D. G. Martins, M. Sopanen, M. Åberg
In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented. The system is providing a temperature compensated 48 MHz clock signal for the range of − 40 to 85 °C. The temperature compensation is achieved by a combination of initial and an autonomous background calibration. The main design guidelines have been on high integration level and minimum silicon area while maintaining a low timing jitter and power consumption. The design was implemented by utilizing Austria Micro Systems (AMS) 0.35 µm standard CMOS process technology. The implementation occupies 1.75 mm2 of silicon area.
{"title":"DLL based temperature compensated MEMS clock","authors":"A. Rantala, D. G. Martins, M. Sopanen, M. Åberg","doi":"10.1109/NORCHIP.2010.5669492","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669492","url":null,"abstract":"In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented. The system is providing a temperature compensated 48 MHz clock signal for the range of − 40 to 85 °C. The temperature compensation is achieved by a combination of initial and an autonomous background calibration. The main design guidelines have been on high integration level and minimum silicon area while maintaining a low timing jitter and power consumption. The design was implemented by utilizing Austria Micro Systems (AMS) 0.35 µm standard CMOS process technology. The implementation occupies 1.75 mm2 of silicon area.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133790539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669491
S. Al-Ahdab, A. Mantyniemi, J. Kostamovaara
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling both the unit load capacitors and the discharge current of the load capacitance. The proposed DTC achieves 610 fs resolution and ∼1.25 ns dynamic range. The total simulated power consumption is 3.5 mW with 125 MHz input signal frequency with 3 V supply. The design was simulated using a 0.35 µm CMOS process.
{"title":"A 12-bit digital-to-time converter (DTC) for time-to-digital converter (TDC) and other time domain signal processing applications","authors":"S. Al-Ahdab, A. Mantyniemi, J. Kostamovaara","doi":"10.1109/NORCHIP.2010.5669491","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669491","url":null,"abstract":"This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling both the unit load capacitors and the discharge current of the load capacitance. The proposed DTC achieves 610 fs resolution and ∼1.25 ns dynamic range. The total simulated power consumption is 3.5 mW with 125 MHz input signal frequency with 3 V supply. The design was simulated using a 0.35 µm CMOS process.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"343 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133321884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669435
M. David Sarmiento, H. Tenhunen, Lirong Zheng, Majid Baghaei Nejad
This paper presents a transmitter design for Ultra Wideband Impulse Radio (UWB-IR) communications. The design is targeted towards the implementation of passive Wireless Sensor Tags (WST) where micro-power consumption is required. The transmitter has been implemented in UMC 0.18µm CMOS and placed inside a QFN lead-less package. It complies with the FCC regulations for Pulse Rate Frequencies (PRF) up to 10MHz using OOK modulation. It is capable of adjusting the Power Spectral Emissions (PSE) modifying the transmitted pulse amplitude to always achieve the best BER/Power performance depending on the application demands. The power emission tunability has been validated implementing a complete communication link using a low sensitivity non-coherent energy receiver. Measurements show a maximum power consumption of 92uW@10MHz PRF having a maximum energy/pulse of 9.2 pJ.
{"title":"A 9.2pJ/pulse UWB-IR transmitter with tunable amplitude for wireless sensor tags in 0.18um CMOS","authors":"M. David Sarmiento, H. Tenhunen, Lirong Zheng, Majid Baghaei Nejad","doi":"10.1109/NORCHIP.2010.5669435","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669435","url":null,"abstract":"This paper presents a transmitter design for Ultra Wideband Impulse Radio (UWB-IR) communications. The design is targeted towards the implementation of passive Wireless Sensor Tags (WST) where micro-power consumption is required. The transmitter has been implemented in UMC 0.18µm CMOS and placed inside a QFN lead-less package. It complies with the FCC regulations for Pulse Rate Frequencies (PRF) up to 10MHz using OOK modulation. It is capable of adjusting the Power Spectral Emissions (PSE) modifying the transmitted pulse amplitude to always achieve the best BER/Power performance depending on the application demands. The power emission tunability has been validated implementing a complete communication link using a low sensitivity non-coherent energy receiver. Measurements show a maximum power consumption of 92uW@10MHz PRF having a maximum energy/pulse of 9.2 pJ.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122371460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669483
B. Jonsson
The influence of CMOS scaling on A/D-converter performance is investigated by observing the entire body of experimental CMOS ADCs reported in IEEE journals and conferences central to the field from 1976 to 2010. Based on the near-exhaustive set of scientific data, empirically observed scaling trends are derived for performance in terms of noisefloor, speed and resolution, as well as for power efficiency expressed by two commonly used figures-of-merit. The trends are used to estimate limits on the achievable ADC performance in nanometer CMOS technologies, with implications for LTE and WCDMA infrastructure applications particularly highlighted.
{"title":"On CMOS scaling and A/D-converter performance","authors":"B. Jonsson","doi":"10.1109/NORCHIP.2010.5669483","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669483","url":null,"abstract":"The influence of CMOS scaling on A/D-converter performance is investigated by observing the entire body of experimental CMOS ADCs reported in IEEE journals and conferences central to the field from 1976 to 2010. Based on the near-exhaustive set of scientific data, empirically observed scaling trends are derived for performance in terms of noisefloor, speed and resolution, as well as for power efficiency expressed by two commonly used figures-of-merit. The trends are used to estimate limits on the achievable ADC performance in nanometer CMOS technologies, with implications for LTE and WCDMA infrastructure applications particularly highlighted.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129260929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669487
I. Kianpour, Z. Zou, M. Nejad, Lirong Zheng
SAR ADCs have been mostly used for moderate-speed, moderate-resolution applications that power consumption is one of the major concerns (e. g. RFID). Furthermore two-step ADCs are classified as high-speed, low to moderate-accuracy ADC. In this paper an ultra low power two-step-SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power comparator with no static current and a dual-stage (Resistor-string / capacitive dividing) architecture as digital-to-analog converter (DAC). In this DAC architecture fine search will be performed by only two C and 15C capacitors which reduced the silicon area significantly. The circuit designed in 0.18um CMOS technology and simulations show that the 8-bit ADC, consumes almost 166nW at 11.25kS/s. The results show that the proposed ADC has higher speed with almost the same power consumption in comparison with its charge redistribution counterpart.
SAR adc主要用于中速，中等分辨率的应用，功耗是主要问题之一(例如RFID)。此外，两步ADC被分类为高速、低到中等精度的ADC。本文介绍了一种用于RFID应用的超低功耗两步sar ADC。采用了几种技术来进一步降低功耗并相对提高ADC的速度。这些技术包括无静态电流的低功率比较器和作为数模转换器(DAC)的双级(电阻串/电容分频)架构。在该DAC架构中，只需两个C和15C电容器即可进行精细搜索，从而显着减少了硅面积。电路采用0.18um CMOS技术设计，仿真结果表明，该8位ADC在11.25kS/s下的功耗接近166nW。结果表明，所提出的ADC与电荷再分配ADC相比具有更高的速度和几乎相同的功耗。
{"title":"An 8-bit 166nw 11.25 kS/s 0.18um two-Step-SAR ADC for RFID applications using novel DAC architecture","authors":"I. Kianpour, Z. Zou, M. Nejad, Lirong Zheng","doi":"10.1109/NORCHIP.2010.5669487","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669487","url":null,"abstract":"SAR ADCs have been mostly used for moderate-speed, moderate-resolution applications that power consumption is one of the major concerns (e. g. RFID). Furthermore two-step ADCs are classified as high-speed, low to moderate-accuracy ADC. In this paper an ultra low power two-step-SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power comparator with no static current and a dual-stage (Resistor-string / capacitive dividing) architecture as digital-to-analog converter (DAC). In this DAC architecture fine search will be performed by only two C and 15C capacitors which reduced the silicon area significantly. The circuit designed in 0.18um CMOS technology and simulations show that the 8-bit ADC, consumes almost 166nW at 11.25kS/s. The results show that the proposed ADC has higher speed with almost the same power consumption in comparison with its charge redistribution counterpart.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127917294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669479
J. Typpo, S. Hietakangas, T. Rahkonen
This work demonstrates a new integrated inverse class E amplifier circuit, employing a pHEMT switching device and fully integrated output network for pulse shaping. The circuit is particularly suitable for full integration, since it does not need any RF choke for biasing, and no DC blocking capacitor is needed between the switch and the output network parallel resonance circuit. The back plate capacitances of the additional capacitors are not connected to nodes that carry RF voltage signals. A commercial GaAs monolithic microwave integrated circuit process was used for fabricating the prototype circuit. 11.5 mW output power and 39% drain efficiency with 0.9 V supply voltage was measured at 895 MHz operating frequency. The output power remains over 10mW across 850–925 MHz, and the drain efficiency remains above 32% across this frequency range.
{"title":"A 900 MHz 10 mW monolithically integrated inverse class E power amplifier","authors":"J. Typpo, S. Hietakangas, T. Rahkonen","doi":"10.1109/NORCHIP.2010.5669479","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669479","url":null,"abstract":"This work demonstrates a new integrated inverse class E amplifier circuit, employing a pHEMT switching device and fully integrated output network for pulse shaping. The circuit is particularly suitable for full integration, since it does not need any RF choke for biasing, and no DC blocking capacitor is needed between the switch and the output network parallel resonance circuit. The back plate capacitances of the additional capacitors are not connected to nodes that carry RF voltage signals. A commercial GaAs monolithic microwave integrated circuit process was used for fabricating the prototype circuit. 11.5 mW output power and 39% drain efficiency with 0.9 V supply voltage was measured at 895 MHz operating frequency. The output power remains over 10mW across 850–925 MHz, and the drain efficiency remains above 32% across this frequency range.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124144762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669438
D. Meganathan, A. Jantsch
This paper presents the systematic design approach of a low-power, medium-resolution, high-speed pipelined Analog-to-Digital Converter (ADC). The ADC is implemented in 180nm digital CMOS technology. The converter achieves signal-to-noise distortion ratio of 59.8 dB, spurious-free dynamic range of 89 dB and effective number of bits of 9.64-bits at sampling speed of 50MHz with an input signal frequency of 4MHz. The peak differential-nonlinearity of the converter is 0.28/−0.17LSB and integral-nonlinearity of the converter is +0.42/−0.41LSB. The proposed 10-bit, 50MS/sec pipelined ADC consumes 24.5mW amount of power from 1.8V supply.
{"title":"A low-power, medium-resolution, high-speed CMOS pipelined ADC","authors":"D. Meganathan, A. Jantsch","doi":"10.1109/NORCHIP.2010.5669438","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669438","url":null,"abstract":"This paper presents the systematic design approach of a low-power, medium-resolution, high-speed pipelined Analog-to-Digital Converter (ADC). The ADC is implemented in 180nm digital CMOS technology. The converter achieves signal-to-noise distortion ratio of 59.8 dB, spurious-free dynamic range of 89 dB and effective number of bits of 9.64-bits at sampling speed of 50MHz with an input signal frequency of 4MHz. The peak differential-nonlinearity of the converter is 0.28/−0.17LSB and integral-nonlinearity of the converter is +0.42/−0.41LSB. The proposed 10-bit, 50MS/sec pipelined ADC consumes 24.5mW amount of power from 1.8V supply.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115985127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669445
Anja Niedermeier, R. Wester, K. Rovers, Christiaan Baaij, J. Kuper, G. Smit
In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code. The VHDL code was synthesised with 90 nm TSMC libraries and placed and routed. Simulation of the final netlist showed correct behaviour. We conclude that Haskell and CλaSH are well-suited to define hardware on a very high level of abstraction which is close to the mathematical description of the desired architecture. By using CλaSH, the designer does not have to care about internal implementation details like when designing with VHDL. The complete processor was described in 300 lines of code, some snippets are shown as illustration.
{"title":"Designing a dataflow processor using CλaSH","authors":"Anja Niedermeier, R. Wester, K. Rovers, Christiaan Baaij, J. Kuper, G. Smit","doi":"10.1109/NORCHIP.2010.5669445","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669445","url":null,"abstract":"In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code. The VHDL code was synthesised with 90 nm TSMC libraries and placed and routed. Simulation of the final netlist showed correct behaviour. We conclude that Haskell and CλaSH are well-suited to define hardware on a very high level of abstraction which is close to the mathematical description of the desired architecture. By using CλaSH, the designer does not have to care about internal implementation details like when designing with VHDL. The complete processor was described in 300 lines of code, some snippets are shown as illustration.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129787916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669477
M. Straka, Jan Kastil, Z. Kotásek
In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented.
{"title":"Generic partial dynamic reconfiguration controller for fault tolerant designs based on FPGA","authors":"M. Straka, Jan Kastil, Z. Kotásek","doi":"10.1109/NORCHIP.2010.5669477","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669477","url":null,"abstract":"In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132889378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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