Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669466
R. Naik
Minimizing power consumption without compromising speed in any integrated circuit (IC) is a challenge. Employing multiple supply voltages (multi-Vdd) is an effective technique to achieve this. In order to minimize the power dissipation in an integrated circuit, voltage level converter circuits are required. There are two novel multi-threshold voltage (multi-Vth) based level converters are proposed. When these novel level converters are applied in an integrated circuit and compared with the previous level converter which are of feed back based circuit. The power dissipation is decreased in this approach up to 47% and the Delay is optimized by 50% with multi threshold based level converter in a 0.18- µm technology.
{"title":"Low power and optimal delay multi threshold voltage level converters","authors":"R. Naik","doi":"10.1109/NORCHIP.2010.5669466","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669466","url":null,"abstract":"Minimizing power consumption without compromising speed in any integrated circuit (IC) is a challenge. Employing multiple supply voltages (multi-Vdd) is an effective technique to achieve this. In order to minimize the power dissipation in an integrated circuit, voltage level converter circuits are required. There are two novel multi-threshold voltage (multi-Vth) based level converters are proposed. When these novel level converters are applied in an integrated circuit and compared with the previous level converter which are of feed back based circuit. The power dissipation is decreased in this approach up to 47% and the Delay is optimized by 50% with multi threshold based level converter in a 0.18- µm technology.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130807265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669449
H. Kariniemi, J. Nurmi
This paper presents a new NoC Interface (NI) targeted for improving the performance of the Micronmesh Multiprocessor System-on-Chip (MPSoC). The previous version of the NI called Micronswitch Interface (MSI) can zero-copy messages as it sends and receives them. It offloads also some functionalities of the communication protocol from software (SW) to hardware (HW), but interrupt processing produces extra SW overhead and reduces the performance. For this reason, an improved version of the MSI called MSI-with-Queues (MSIQ) was designed with a new queue mechanism in order to reduce the frequency of interrupts and the SW overhead. Owing to the new queue mechanism of the MSIQ it is possible to batch and service multiple interrupt service requests by every execution of the Interrupt Service Routine (ISR). Additionally, the new MSIQ HW is able to send and receive messages while the processor is running the ISR. The performance of the MSIQ is also analyzed in this paper. The results show that the queue mechanism improves the performance with moderate hardware costs.
{"title":"High-performance NoC Interface with interrupt batching for Micronmesh MPSoC prototype platform on FPGA","authors":"H. Kariniemi, J. Nurmi","doi":"10.1109/NORCHIP.2010.5669449","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669449","url":null,"abstract":"This paper presents a new NoC Interface (NI) targeted for improving the performance of the Micronmesh Multiprocessor System-on-Chip (MPSoC). The previous version of the NI called Micronswitch Interface (MSI) can zero-copy messages as it sends and receives them. It offloads also some functionalities of the communication protocol from software (SW) to hardware (HW), but interrupt processing produces extra SW overhead and reduces the performance. For this reason, an improved version of the MSI called MSI-with-Queues (MSIQ) was designed with a new queue mechanism in order to reduce the frequency of interrupts and the SW overhead. Owing to the new queue mechanism of the MSIQ it is possible to batch and service multiple interrupt service requests by every execution of the Interrupt Service Routine (ISR). Additionally, the new MSIQ HW is able to send and receive messages while the processor is running the ISR. The performance of the MSIQ is also analyzed in this paper. The results show that the queue mechanism improves the performance with moderate hardware costs.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128751007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669433
T. Xu, L. Guang, A. Yin, Bo Yang, P. Liljeberg, H. Tenhunen
Network-on-Chip (NoC) has become a widely accepted on-chip communication architecture which provides a promising solution to integrate a large number of components on a single chip. However, with the increasingly higher performance demands for on-chip systems, NoCs are facing several critical challenges such as wire delay and power consumption. Therefore, in this paper, we explore different cache architecture designs in 2D/3D NoC architectures. Integrated core/cache and split and wire delay. We present benchmark results using a cycle accurate full system simulator. Experiments show that, by using the proposed 3D NoC architecture, compared with the integrated core/cache design, the average network latency and average link utilization are reduced by 5.01% and 26.07% respectively.
{"title":"An analysis of designing 2D/3D chip multiprocessor wit different cache architecture","authors":"T. Xu, L. Guang, A. Yin, Bo Yang, P. Liljeberg, H. Tenhunen","doi":"10.1109/NORCHIP.2010.5669433","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669433","url":null,"abstract":"Network-on-Chip (NoC) has become a widely accepted on-chip communication architecture which provides a promising solution to integrate a large number of components on a single chip. However, with the increasingly higher performance demands for on-chip systems, NoCs are facing several critical challenges such as wire delay and power consumption. Therefore, in this paper, we explore different cache architecture designs in 2D/3D NoC architectures. Integrated core/cache and split and wire delay. We present benchmark results using a cycle accurate full system simulator. Experiments show that, by using the proposed 3D NoC architecture, compared with the integrated core/cache design, the average network latency and average link utilization are reduced by 5.01% and 26.07% respectively.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114889246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669429
J. R. Custódio, L. B. Oliveira, J. Goes, J. Oliveira, E. Bruun, P. Andreani
In this paper we present a low-power and small-area balun LNA. The proposed inverter-based topology uses self-biasing and noise cancelling, yielding a very robust LNA with a low NF. Comparing this circuit with a conventional inverter-based circuit, we obtain a ∼3 dB enhancement in voltage gain, with improved robustness against PVT variations. Simulations results in a 130 nm CMOS technology show a 17.7dB voltage gain, nearly flat over a wide bandwidth (200MHz–1GHz), and an NF of approximately 4dB. The total power consumption is below 7.5 mW, with a very small die area of 0.007 mm2. All data are extracted from post-layout simulations.
{"title":"A small-area self-biased wideband CMOS balun LNA with noise cancelling and gain enhancement","authors":"J. R. Custódio, L. B. Oliveira, J. Goes, J. Oliveira, E. Bruun, P. Andreani","doi":"10.1109/NORCHIP.2010.5669429","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669429","url":null,"abstract":"In this paper we present a low-power and small-area balun LNA. The proposed inverter-based topology uses self-biasing and noise cancelling, yielding a very robust LNA with a low NF. Comparing this circuit with a conventional inverter-based circuit, we obtain a ∼3 dB enhancement in voltage gain, with improved robustness against PVT variations. Simulations results in a 130 nm CMOS technology show a 17.7dB voltage gain, nearly flat over a wide bandwidth (200MHz–1GHz), and an NF of approximately 4dB. The total power consumption is below 7.5 mW, with a very small die area of 0.007 mm2. All data are extracted from post-layout simulations.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128748990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669493
B. Banerjee, C. Enz, E. Le Roux
This paper presents an implemented 4-bit phase ADC circuit. It introduces a model to calculate its dynamic range considering second order effects including non-linearity and offsets. The study also encompasses the phase resolution and validates the model with measurement results from the implemented chip. Our analysis shows that the phase ADC is extremely robust against circuit non-idealities and provides higher dynamic range compared to traditional amplitude ADCs while consuming lower power.
{"title":"A 290µA, 3.2MHz 4-bit phase ADC for constant envelope, ultra-low power radio","authors":"B. Banerjee, C. Enz, E. Le Roux","doi":"10.1109/NORCHIP.2010.5669493","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669493","url":null,"abstract":"This paper presents an implemented 4-bit phase ADC circuit. It introduces a model to calculate its dynamic range considering second order effects including non-linearity and offsets. The study also encompasses the phase resolution and validates the model with measurement results from the implemented chip. Our analysis shows that the phase ADC is extremely robust against circuit non-idealities and provides higher dynamic range compared to traditional amplitude ADCs while consuming lower power.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"264 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125808886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669476
H. Hurskainen, J. Raasakka, J. Nurmi
The most of the upcoming global satellite navigation system (GNSS) signals will be composite type. Composite satellite signals have unique spreading codes both for data channel and dataless (pilot) channel. The combination allows both data extraction for navigation and longer integration of pilot for better timing and thus positioning accuracy. The non-coherent and coherent collaborative tracking algorithms are presented in literature. In this paper we present our work on flexible hardware implementation, capable for both types of collaborative tracking. The implementation is done with FPGA based TUTGNSS receiver platform, and synthesis results for implementation are presented. From results it can be seen that the logic consumption overhead for 16-channel collaborative tracking unit is 56.9% with full hardware support and 26.6% with optimized hardware support when compared to design without the presented structure.
{"title":"Flexible hardware implementation of collaborative GNSS tracking channel","authors":"H. Hurskainen, J. Raasakka, J. Nurmi","doi":"10.1109/NORCHIP.2010.5669476","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669476","url":null,"abstract":"The most of the upcoming global satellite navigation system (GNSS) signals will be composite type. Composite satellite signals have unique spreading codes both for data channel and dataless (pilot) channel. The combination allows both data extraction for navigation and longer integration of pilot for better timing and thus positioning accuracy. The non-coherent and coherent collaborative tracking algorithms are presented in literature. In this paper we present our work on flexible hardware implementation, capable for both types of collaborative tracking. The implementation is done with FPGA based TUTGNSS receiver platform, and synthesis results for implementation are presented. From results it can be seen that the logic consumption overhead for 16-channel collaborative tracking unit is 56.9% with full hardware support and 26.6% with optimized hardware support when compared to design without the presented structure.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"17 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133977831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669494
Clement Foucher, F. Muller, A. Giulieri
Reconfigurable hardware is now used in high performance computers, introducing the high performance reconfigurable computing. Dynamic hardware allows processors to devolve intensive computations to dedicated hardware circuitry optimized for that purpose. Our aim is to make larger use of hardware capabilities by pooling the hardware and software computations resources in a unified design in order to allow replacing the ones by the others depending on the application needs. For that purpose, we needed a test platform to evaluate FPGA capabilities to operate as a high performance computer node. We designed an architecture allowing the separation of a parallel program communication from its kernels computation in order to make easier the future partial dynamic reconfiguration of the processing elements. This architecture implements static softcores as test IPs, keeping in mind that the future platform implementing dynamic reconfiguration will allow changing the processing elements. In this paper, we present this test architecture and its implementation upon Xilinx Virtex 5 FPGAs. We then present a benchmark of the platform using the NAS parallel benchmark integer sort in order to compare various use cases.
{"title":"Exploring FPGAs capability to host a HPC design","authors":"Clement Foucher, F. Muller, A. Giulieri","doi":"10.1109/NORCHIP.2010.5669494","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669494","url":null,"abstract":"Reconfigurable hardware is now used in high performance computers, introducing the high performance reconfigurable computing. Dynamic hardware allows processors to devolve intensive computations to dedicated hardware circuitry optimized for that purpose. Our aim is to make larger use of hardware capabilities by pooling the hardware and software computations resources in a unified design in order to allow replacing the ones by the others depending on the application needs. For that purpose, we needed a test platform to evaluate FPGA capabilities to operate as a high performance computer node. We designed an architecture allowing the separation of a parallel program communication from its kernels computation in order to make easier the future partial dynamic reconfiguration of the processing elements. This architecture implements static softcores as test IPs, keeping in mind that the future platform implementing dynamic reconfiguration will allow changing the processing elements. In this paper, we present this test architecture and its implementation upon Xilinx Virtex 5 FPGAs. We then present a benchmark of the platform using the NAS parallel benchmark integer sort in order to compare various use cases.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124600768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669461
Nadeem Afzal, J. Wikner
In this paper, modified low-complex, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and subDAC complexity. The studied techniques illustrate the trade-off in terms of noise-shaper and DAC implementation complexity and loss in SNR. It is found that a fair amount of improvement in SNR is achieved by maintaining low-complexity of noise shaper. The complexity of the subDAC is yet a parameter, directly related to the number of output bits from the noise shaper. Two different architectures are investigated with respect to subDAC complexity and noise shaper complexity. It is shown that the required number of DAC unit elements (DUE) can be reduced to half.
{"title":"Study of modified noise-shaper architectures for oversampled sigma-delta DACs","authors":"Nadeem Afzal, J. Wikner","doi":"10.1109/NORCHIP.2010.5669461","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669461","url":null,"abstract":"In this paper, modified low-complex, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and subDAC complexity. The studied techniques illustrate the trade-off in terms of noise-shaper and DAC implementation complexity and loss in SNR. It is found that a fair amount of improvement in SNR is achieved by maintaining low-complexity of noise shaper. The complexity of the subDAC is yet a parameter, directly related to the number of output bits from the noise shaper. Two different architectures are investigated with respect to subDAC complexity and noise shaper complexity. It is shown that the required number of DAC unit elements (DUE) can be reduced to half.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125896668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669489
Elena Hammari, F. Catthoor, J. Huisken, P. G. Kjeldsberg
In this paper we present a methodology that enables mapping and scheduling of a dynamic real-time medical signal processing application onto an MPSoC platform. We apply the Task Concurrency Management (TCM) methodology on Lyapunov Exponent calculator, which is a part of an epileptic seizure predictor. TCM requires a division of an application into thread frames and thread nodes. In particular, we demonstrate a new technique for thread node splitting so as to reduce execution time variance. This is necessary to meet stringent energy and performance requirements during mapping and scheduling. Through experiments we verify that the resulting model of the Lyapunov Exponent calculator fulfills the requirements of the TCM methodology.
{"title":"Application Of medium-grain multiprocessor mapping methodology to epileptic seizure predictor","authors":"Elena Hammari, F. Catthoor, J. Huisken, P. G. Kjeldsberg","doi":"10.1109/NORCHIP.2010.5669489","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669489","url":null,"abstract":"In this paper we present a methodology that enables mapping and scheduling of a dynamic real-time medical signal processing application onto an MPSoC platform. We apply the Task Concurrency Management (TCM) methodology on Lyapunov Exponent calculator, which is a part of an epileptic seizure predictor. TCM requires a division of an application into thread frames and thread nodes. In particular, we demonstrate a new technique for thread node splitting so as to reduce execution time variance. This is necessary to meet stringent energy and performance requirements during mapping and scheduling. Through experiments we verify that the resulting model of the Lyapunov Exponent calculator fulfills the requirements of the TCM methodology.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114221127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669481
M. Wei, Sheng-Fuh Chang, R. Negra
A DC-invariant gain control technique is introduced for differential CMOS variable-gain low-noise amplifiers (VG-LNA). Such technique provides an advantage of invariant DC bias current when the RF power gain is tuned over the gain control range. Therefore, the transconductance of NMOS transistor is unchanged, which minimizes the input match detuning. Consequently, the optimal design for noise, gain and power linearity becomes easier to achieve. The implemented 0.18 µm CMOS VG-LNA shows a nearly constant DC current of 7.8±0.5 mA from a 1.5 V supply when the RF power gain is tuned from 0 to 12.3 dB at 3.5 GHz. Over this gain tuning range, the input return loss is almost unchanged around 11.5 dB. The minimum noise figure is 2.59 dB and the input-referred P1dB is −4.5 dBm corresponding to the high gain (12.3 dB) situation. The in-band gain flatness is as flat as ±0.2 dB. A very high FOM of 20.6 is obtained.
{"title":"A DC-invariant gain control technique for CMOS differential variable-gain low-noise amplifiers","authors":"M. Wei, Sheng-Fuh Chang, R. Negra","doi":"10.1109/NORCHIP.2010.5669481","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669481","url":null,"abstract":"A DC-invariant gain control technique is introduced for differential CMOS variable-gain low-noise amplifiers (VG-LNA). Such technique provides an advantage of invariant DC bias current when the RF power gain is tuned over the gain control range. Therefore, the transconductance of NMOS transistor is unchanged, which minimizes the input match detuning. Consequently, the optimal design for noise, gain and power linearity becomes easier to achieve. The implemented 0.18 µm CMOS VG-LNA shows a nearly constant DC current of 7.8±0.5 mA from a 1.5 V supply when the RF power gain is tuned from 0 to 12.3 dB at 3.5 GHz. Over this gain tuning range, the input return loss is almost unchanged around 11.5 dB. The minimum noise figure is 2.59 dB and the input-referred P1dB is −4.5 dBm corresponding to the high gain (12.3 dB) situation. The in-band gain flatness is as flat as ±0.2 dB. A very high FOM of 20.6 is obtained.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126540621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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