Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669472
Tim Wegner, C. Cornelius, Martin Gag, Andreas Tockhorn, A. Uhrmacher
Due to increasing integration densities and the emergence of nanotechnology, especially reliability and power related design aspects become critical for chip design. Since the arising problems are enforced by high circuit temperatures, the need for a possibility to model thermal behavior of a system in an accurate and physically correct way becomes inevitable. Hence, in this paper VulcaNoCs, a SystemC-based simulation environment for systems based on NoCs, is introduced. VulcaNoCs is designed to enable simultaneous execution of both high-level system simulation and dynamic modeling of temperature distributions in NoC-based systems. To emulate a system's thermal properties equivalent RC-circuits are used, exploiting the dualism between heat flow and electrical phenomena. To verify the temperature model, VulcaNoCs is compared to a more commonly used SPICE-based approach, exhibiting significant increases in simulation performance of up to 98,5% for modeling a 2×2 NoC, for example.
{"title":"Simulation of thermal behavior for Networks-on-Chip","authors":"Tim Wegner, C. Cornelius, Martin Gag, Andreas Tockhorn, A. Uhrmacher","doi":"10.1109/NORCHIP.2010.5669472","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669472","url":null,"abstract":"Due to increasing integration densities and the emergence of nanotechnology, especially reliability and power related design aspects become critical for chip design. Since the arising problems are enforced by high circuit temperatures, the need for a possibility to model thermal behavior of a system in an accurate and physically correct way becomes inevitable. Hence, in this paper VulcaNoCs, a SystemC-based simulation environment for systems based on NoCs, is introduced. VulcaNoCs is designed to enable simultaneous execution of both high-level system simulation and dynamic modeling of temperature distributions in NoC-based systems. To emulate a system's thermal properties equivalent RC-circuits are used, exploiting the dualism between heat flow and electrical phenomena. To verify the temperature model, VulcaNoCs is compared to a more commonly used SPICE-based approach, exhibiting significant increases in simulation performance of up to 98,5% for modeling a 2×2 NoC, for example.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133528727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669443
Reza Meraji, John B. Anderson, H. Sjoland, V. Owall
This paper presents the architecture and the corresponding simulation results for a digitally interfaced ultra-low power extended Hamming decoder implemented in analog integrated circuitry. ST's 65nm low power CMOS design library was used to simulate the complete decoder including a serial input digital interface, an analog decoding core and a serial output digital interface. The simulated bit error rate (BER) performance of the decoder is presented and compared to the ideal performance of the Hamming code. Transistor-level simulation results show that an ultra low power, high throughput Hamming decoder up to 2.5 Mb/s can be implemented using analog circuitry working in sub-threshold (sub-VT ) region with a total power consumption below 40 µW. The decoder consumes less than 16 µW when a lower throughput of 250 kb/s is desired.
{"title":"A low power analog channel decoder for Ultra Portable Devices in 65 nm technology","authors":"Reza Meraji, John B. Anderson, H. Sjoland, V. Owall","doi":"10.1109/NORCHIP.2010.5669443","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669443","url":null,"abstract":"This paper presents the architecture and the corresponding simulation results for a digitally interfaced ultra-low power extended Hamming decoder implemented in analog integrated circuitry. ST's 65nm low power CMOS design library was used to simulate the complete decoder including a serial input digital interface, an analog decoding core and a serial output digital interface. The simulated bit error rate (BER) performance of the decoder is presented and compared to the ideal performance of the Hamming code. Transistor-level simulation results show that an ultra low power, high throughput Hamming decoder up to 2.5 Mb/s can be implemented using analog circuitry working in sub-threshold (sub-VT ) region with a total power consumption below 40 µW. The decoder consumes less than 16 µW when a lower throughput of 250 kb/s is desired.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131293613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669464
T. Rahkonen, J. Aikio, M. Mustaparta
The distortion of a current-steering digital-to-analog converter (DAC) is often dominated by the signal-dependent output impedance. This has normally been analysed by assuming a purely resistive load. When a digital IF signal is generated, the different harmonic bands are separated and can also be filtered separately. This paper illustrates that linearity can be improved considerably by shorting the generated 2nd harmonic and low-frequency voltage immediately at the DAC's output, so that these can not mix further to any higher order products.
{"title":"Effects of filtering on the linearity of current-steering IF DAC","authors":"T. Rahkonen, J. Aikio, M. Mustaparta","doi":"10.1109/NORCHIP.2010.5669464","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669464","url":null,"abstract":"The distortion of a current-steering digital-to-analog converter (DAC) is often dominated by the signal-dependent output impedance. This has normally been analysed by assuming a purely resistive load. When a digital IF signal is generated, the different harmonic bands are separated and can also be filtered separately. This paper illustrates that linearity can be improved considerably by shorting the generated 2nd harmonic and low-frequency voltage immediately at the DAC's output, so that these can not mix further to any higher order products.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121238839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669450
Syed Ahmed Aamir, J. Wikner
This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process.
{"title":"A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS","authors":"Syed Ahmed Aamir, J. Wikner","doi":"10.1109/NORCHIP.2010.5669450","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669450","url":null,"abstract":"This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"391 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123262257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669440
Mohammad Adeel Tajammul, M. A. Shami, A. Hemani, S. Moorthi
The paper focuses on the design of a Network-on-chip based programmable and partitionable distributed memory architecture which can be integrated with a Coarse Grain Reconfigurable Architecture (CGRA). The proposed interconnect enables better interaction between computation fabric and memory fabric. The system can modify its memory to computation element ratio at runtime. The extensive capabilities of the memory system are analyzed by interfacing it with a Dynamically Reconfigurable Resource Array (DRRA), a CGRA. The interconnect can provide multiple interfaces which supports upto 8 GB/s per interface.
{"title":"A NoC based distributed memory architecture with programmable and partitionable capabilities","authors":"Mohammad Adeel Tajammul, M. A. Shami, A. Hemani, S. Moorthi","doi":"10.1109/NORCHIP.2010.5669440","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669440","url":null,"abstract":"The paper focuses on the design of a Network-on-chip based programmable and partitionable distributed memory architecture which can be integrated with a Coarse Grain Reconfigurable Architecture (CGRA). The proposed interconnect enables better interaction between computation fabric and memory fabric. The system can modify its memory to computation element ratio at runtime. The extensive capabilities of the memory system are analyzed by interfacing it with a Dynamically Reconfigurable Resource Array (DRRA), a CGRA. The interconnect can provide multiple interfaces which supports upto 8 GB/s per interface.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128927907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669467
P. Lu, P. Andreani
A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves the in-band TDC noise contribution for an ADPLL. Operating at 1.2-V supply with 250MHz clock, the chip achieves a less-than-10ps coarse resolution (varies with digital control bits) and consumes only 3.6-mA.
{"title":"A high-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS","authors":"P. Lu, P. Andreani","doi":"10.1109/NORCHIP.2010.5669467","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669467","url":null,"abstract":"A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves the in-band TDC noise contribution for an ADPLL. Operating at 1.2-V supply with 250MHz clock, the chip achieves a less-than-10ps coarse resolution (varies with digital control bits) and consumes only 3.6-mA.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126735626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669490
Muhammad Imran, Khursheed Khursheed, M. O’nils, N. Lawal
The challenges associated with wireless vision sensor networks are low energy consumption, less bandwidth and limited processing capabilities. In order to meet these challenges different approaches are proposed. Research in wireless vision sensor networks has been focused on two different assumptions, first is sending all data to the central base station without local processing, second approach is based on conducting all processing locally at the sensor node and transmitting only the final results. Our research is focused on partitioning the vision processing tasks between Senor node and central base station. In this paper we have added the exploration dimension to perform some of the vision tasks such as image capturing, background subtraction, segmentation and Tiff Group4 compression on FPGA while communication on microcontroller. The remaining vision processing tasks i.e. morphology, labeling, bubble remover and classification are processed on central base station. Our results show that the introduction of FPGA for some of the visual tasks will result in a longer life time for the visual sensor node while the architecture is still programmable.
{"title":"Exploration of target architecture for a wireless camera based sensor node","authors":"Muhammad Imran, Khursheed Khursheed, M. O’nils, N. Lawal","doi":"10.1109/NORCHIP.2010.5669490","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669490","url":null,"abstract":"The challenges associated with wireless vision sensor networks are low energy consumption, less bandwidth and limited processing capabilities. In order to meet these challenges different approaches are proposed. Research in wireless vision sensor networks has been focused on two different assumptions, first is sending all data to the central base station without local processing, second approach is based on conducting all processing locally at the sensor node and transmitting only the final results. Our research is focused on partitioning the vision processing tasks between Senor node and central base station. In this paper we have added the exploration dimension to perform some of the vision tasks such as image capturing, background subtraction, segmentation and Tiff Group4 compression on FPGA while communication on microcontroller. The remaining vision processing tasks i.e. morphology, labeling, bubble remover and classification are processed on central base station. Our results show that the introduction of FPGA for some of the visual tasks will result in a longer life time for the visual sensor node while the architecture is still programmable.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121545153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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