Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292529
J. Darnauer, Wei-Ming Dai
The problem of redistributing IO from bondpads on the periphery of an IC to an array of solder bumps occurs frequently in MCM layout. We show that the commonly held belief that providing enough escapes at the perimeter of the array is not sufficient to guarantee routability of the design. We analyze the even wiring distribution (EWD) routing heuristic and show that it produces designs whose critical wire density is no greater that /spl radic/2 times the best possible design. Then, we employ the bound on EWD to establish a surprisingly non-monotonic relationship between bump pitch and design routability, and present our implementation of a design system that employs these principles.<>
{"title":"Fast pad redistribution from periphery-IO to area-IO","authors":"J. Darnauer, Wei-Ming Dai","doi":"10.1109/MCMC.1994.292529","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292529","url":null,"abstract":"The problem of redistributing IO from bondpads on the periphery of an IC to an array of solder bumps occurs frequently in MCM layout. We show that the commonly held belief that providing enough escapes at the perimeter of the array is not sufficient to guarantee routability of the design. We analyze the even wiring distribution (EWD) routing heuristic and show that it produces designs whose critical wire density is no greater that /spl radic/2 times the best possible design. Then, we employ the bound on EWD to establish a surprisingly non-monotonic relationship between bump pitch and design routability, and present our implementation of a design system that employs these principles.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131943770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292526
D. Tuckerman, L.-O. Bauer, N. Brathwaite, J. Demmin, K. Flatow, R. Hsu, P. Kim, C.-M. Lin, K. Lin, S. Nguyen, V. Thipphavong
A new, low-cost, manufacturable process for stacking memory chips up to four-high on a multichip module (MCM) substrate is described. The process is particularly useful when utilized with a high-performance thin-film interconnection substrate ("MCM-D"), as the technique typically enables large (2-4x) reductions in substrate cost for memory-intensive designs, with only a small increment in assembly cost, thereby achieving lower total MCM cost, and greater utilization of the high wiring density and good thermal conductivity of the MCM substrate. The technology was developed and demonstrated using commercially available MCM assembly equipment (dicing, adhesive die attach, and wire bonding equipment). Fully functional memory modules incorporating 2-high stacks have been fabricated, and have passed basic thermal shock tests.<>
{"title":"Laminated memory: a new 3-dimensional packaging technology for MCMs","authors":"D. Tuckerman, L.-O. Bauer, N. Brathwaite, J. Demmin, K. Flatow, R. Hsu, P. Kim, C.-M. Lin, K. Lin, S. Nguyen, V. Thipphavong","doi":"10.1109/MCMC.1994.292526","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292526","url":null,"abstract":"A new, low-cost, manufacturable process for stacking memory chips up to four-high on a multichip module (MCM) substrate is described. The process is particularly useful when utilized with a high-performance thin-film interconnection substrate (\"MCM-D\"), as the technique typically enables large (2-4x) reductions in substrate cost for memory-intensive designs, with only a small increment in assembly cost, thereby achieving lower total MCM cost, and greater utilization of the high wiring density and good thermal conductivity of the MCM substrate. The technology was developed and demonstrated using commercially available MCM assembly equipment (dicing, adhesive die attach, and wire bonding equipment). Fully functional memory modules incorporating 2-high stacks have been fabricated, and have passed basic thermal shock tests.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128709584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292518
M. Lubaszewski, M. Marzouki, M. H. Touati
Current MCM market cannot afford yet 100% product testability. This paper presents a way to get along with partial testability. Under the assumption that module-level boundary scan is available and that, at the chip-level, it is only implemented in some of the dies, we propose a methodology for simultaneous test and diagnosis of boundary scan and non boundary scan parts.<>
{"title":"A pragmatic test and diagnosis methodology for partially testable MCMs","authors":"M. Lubaszewski, M. Marzouki, M. H. Touati","doi":"10.1109/MCMC.1994.292518","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292518","url":null,"abstract":"Current MCM market cannot afford yet 100% product testability. This paper presents a way to get along with partial testability. Under the assumption that module-level boundary scan is available and that, at the chip-level, it is only implemented in some of the dies, we propose a methodology for simultaneous test and diagnosis of boundary scan and non boundary scan parts.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115458022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292512
S. Khan, V. Madisetti
We propose a new quantitative approach to MCM and ASEM system partitioning under yield, I/O, and area constraints. The objective is to minimize the off-chip communication/wiring cost while improving the yield of an MCM or ASEM (using smaller partitions without violating I/O and area constraints). We formulate this as a 0/spl minus/1 quadratic programming problem with linear constraints. This paper describes the quantitative model and results from detailed partitioning of large benchmark VLSI circuits.<>
{"title":"Yield-based system partitioning strategies for MCM and ASEM design","authors":"S. Khan, V. Madisetti","doi":"10.1109/MCMC.1994.292512","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292512","url":null,"abstract":"We propose a new quantitative approach to MCM and ASEM system partitioning under yield, I/O, and area constraints. The objective is to minimize the off-chip communication/wiring cost while improving the yield of an MCM or ASEM (using smaller partitions without violating I/O and area constraints). We formulate this as a 0/spl minus/1 quadratic programming problem with linear constraints. This paper describes the quantitative model and results from detailed partitioning of large benchmark VLSI circuits.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129800712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292530
T. Okada, T. Sudo
An investigation of the design considerations for MCMs based on CMOS VLSI has been carried out with the aim of achieving a higher performance system. Included in the investigation were output driver and receiver characteristics and net configurations in MCM. Four MCM types have been introduced: MCM-D, MCM-Si, MCM-C, and MCM-L. Time domain analysis using the SPICE simulation program was carried out taking into consideration a lossy transmission line model. A simpler criterion for the critical damping condition and an estimation method for the signal delay of the network with a lumped circuit approximation is proposed to determine a preferable interconnect network including the output driver and the loads. The effect of the net configuration was also analyzed and the preferences among the net configurations have been represented with only two net parameters, the total net length and the far-end length.<>
{"title":"Characterization of net configurations for multichip modules","authors":"T. Okada, T. Sudo","doi":"10.1109/MCMC.1994.292530","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292530","url":null,"abstract":"An investigation of the design considerations for MCMs based on CMOS VLSI has been carried out with the aim of achieving a higher performance system. Included in the investigation were output driver and receiver characteristics and net configurations in MCM. Four MCM types have been introduced: MCM-D, MCM-Si, MCM-C, and MCM-L. Time domain analysis using the SPICE simulation program was carried out taking into consideration a lossy transmission line model. A simpler criterion for the critical damping condition and an estimation method for the signal delay of the network with a lumped circuit approximation is proposed to determine a preferable interconnect network including the output driver and the loads. The effect of the net configuration was also analyzed and the preferences among the net configurations have been represented with only two net parameters, the total net length and the far-end length.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124591302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292540
B. Willner
Summary form only given, as follows. The confluence of social and technological readiness signals that the widespread use of a new technology is coming. New developments, both technical and business, regarding the digital highway, networked multimedia and interactive TV are reported everyday. This field is both a large driver and consumer of technology. Large scale multimedia and interactive TV will provide personal interactive access to vast quantities of information in video and multimedia forms. The end user will have available many exciting applications for use in entertainment, education, and business. End to end systems comprised of electronic repositories, high speed networks, TVs, PCs, and other personal devices will be integrated. These systems depend on a variety of new technologies that are just now emerging. The author focuses on applications, end to end systems and the various new technologies. In particular he discusses the following applications; video on demand, near video on demand, home shopping, education in school and home, training, manufacturing, and marketing. The following technologies are also discussed; large, scalable servers, ATM networking, RF modem technologies (QAM and VSB), ADSL, MPEG compression and transport.<>
{"title":"Large scale multimedia and interactive television","authors":"B. Willner","doi":"10.1109/MCMC.1994.292540","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292540","url":null,"abstract":"Summary form only given, as follows. The confluence of social and technological readiness signals that the widespread use of a new technology is coming. New developments, both technical and business, regarding the digital highway, networked multimedia and interactive TV are reported everyday. This field is both a large driver and consumer of technology. Large scale multimedia and interactive TV will provide personal interactive access to vast quantities of information in video and multimedia forms. The end user will have available many exciting applications for use in entertainment, education, and business. End to end systems comprised of electronic repositories, high speed networks, TVs, PCs, and other personal devices will be integrated. These systems depend on a variety of new technologies that are just now emerging. The author focuses on applications, end to end systems and the various new technologies. In particular he discusses the following applications; video on demand, near video on demand, home shopping, education in school and home, training, manufacturing, and marketing. The following technologies are also discussed; large, scalable servers, ATM networking, RF modem technologies (QAM and VSB), ADSL, MPEG compression and transport.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"14 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132822822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292539
E. J. Vardaman
MCM technology has moved past the proof-of-concept phase, entered the first production phase, and continues into expanding fields of application. Multichip modules are used in supercomputer and mainframe computers, workstations, personal computers, telecommunications, military products, medical, and consumer electronics products. Many of these applications will see additional MCM use in the next few years, but the industry has not grown as fast, or as large, as many projected. Some barriers to MCM use remain. The merchant market has matured and substrate cost have dropped. Known good die (KGD) strategies are being implemented. Additional work is required in MCM testing to lower the system cost, but many companies are developing new or improved test equipment and methods. The remaining question is how does the MCM investment strategy differ between Japanese and US companies, and which set of companies have the winning strategy? This paper seeks to examine the positions of US and Japanese companies with respect to infrastructure development strategies for the MCM market.<>
{"title":"MCM infrastructure in Japan and the United States: consumer vs. industrial strategies","authors":"E. J. Vardaman","doi":"10.1109/MCMC.1994.292539","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292539","url":null,"abstract":"MCM technology has moved past the proof-of-concept phase, entered the first production phase, and continues into expanding fields of application. Multichip modules are used in supercomputer and mainframe computers, workstations, personal computers, telecommunications, military products, medical, and consumer electronics products. Many of these applications will see additional MCM use in the next few years, but the industry has not grown as fast, or as large, as many projected. Some barriers to MCM use remain. The merchant market has matured and substrate cost have dropped. Known good die (KGD) strategies are being implemented. Additional work is required in MCM testing to lower the system cost, but many companies are developing new or improved test equipment and methods. The remaining question is how does the MCM investment strategy differ between Japanese and US companies, and which set of companies have the winning strategy? This paper seeks to examine the positions of US and Japanese companies with respect to infrastructure development strategies for the MCM market.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129514971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292536
J. Demmin
Summary form given, as follows. nCHIP's "quick-turnaround, low cost MCM prototyping" program is simplifying the development of new MCM designs by reducing the long cycle times and large non-recurring engineering (NRE) costs that have created a barrier to entry for many potential MCM users. Much of the time and expense for MCMs arises from the custom nature of most current MCM substrates and packages, as well as the design, manufacturing, and test procedures typical of a young industry. Consequently, the focus of this program is standardization. The effort includes: standard MCM packages and substrate sizes, MCM design kits for user generation and analysis of layouts, improved CAM interfaces linking design and manufacturing, standard MCM test flows, bare die procurement, and MCM component model libraries. Three development vehicles demonstrating the progress during the course of the program with real MCM designs are also included. The progress, current status, and future plans for all of these tasks are presented.<>
{"title":"Quick-turnaround, low-cost MCM prototyping","authors":"J. Demmin","doi":"10.1109/MCMC.1994.292536","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292536","url":null,"abstract":"Summary form given, as follows. nCHIP's \"quick-turnaround, low cost MCM prototyping\" program is simplifying the development of new MCM designs by reducing the long cycle times and large non-recurring engineering (NRE) costs that have created a barrier to entry for many potential MCM users. Much of the time and expense for MCMs arises from the custom nature of most current MCM substrates and packages, as well as the design, manufacturing, and test procedures typical of a young industry. Consequently, the focus of this program is standardization. The effort includes: standard MCM packages and substrate sizes, MCM design kits for user generation and analysis of layouts, improved CAM interfaces linking design and manufacturing, standard MCM test flows, bare die procurement, and MCM component model libraries. Three development vehicles demonstrating the progress during the course of the program with real MCM designs are also included. The progress, current status, and future plans for all of these tasks are presented.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122109013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292514
S. Luo, Jyh-Ming Jang, V. Tripathi
A method for the time domain simulation of coupled interconnects in a layered medium with meshed ground planes is presented. The method, based on the quasi-TEM spectral domain analysis of the layered structure and the SPICE model consisting of delay elements and linear dependent sources, is used to study crosstalk in coupled interconnects. The theoretical results are validated by experimental data, and it is shown that the presence of slots and meshes in ground planes can reduce the far-end crosstalk in coupled interconnects.<>
{"title":"Crosstalk in coupled interconnects with meshed ground planes","authors":"S. Luo, Jyh-Ming Jang, V. Tripathi","doi":"10.1109/MCMC.1994.292514","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292514","url":null,"abstract":"A method for the time domain simulation of coupled interconnects in a layered medium with meshed ground planes is presented. The method, based on the quasi-TEM spectral domain analysis of the layered structure and the SPICE model consisting of delay elements and linear dependent sources, is used to study crosstalk in coupled interconnects. The theoretical results are validated by experimental data, and it is shown that the presence of slots and meshes in ground planes can reduce the far-end crosstalk in coupled interconnects.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128122357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292516
Y. Sugiuchi, B. Katz, R. Rohrer
The asymptotic waveform evaluation (AWE) technique is utilized for performance evaluation and optimization of interconnect circuits consisting of both lumped and distributed elements. An efficient method for distributed element sensitivity, a gradient based optimization scheme, and several techniques to enhance both efficiency and accuracy of simulation performance are presented and evaluated in this paper.<>
{"title":"Interconnect optimization using asymptotic waveform evaluation (AWE)","authors":"Y. Sugiuchi, B. Katz, R. Rohrer","doi":"10.1109/MCMC.1994.292516","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292516","url":null,"abstract":"The asymptotic waveform evaluation (AWE) technique is utilized for performance evaluation and optimization of interconnect circuits consisting of both lumped and distributed elements. An efficient method for distributed element sensitivity, a gradient based optimization scheme, and several techniques to enhance both efficiency and accuracy of simulation performance are presented and evaluated in this paper.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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