Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292524
M. Mita, T. Kumakura, S. Inoue, Y. Hiraki
A newly advanced design for a TAB/BGA multi-chip stacked module has been developed for high density LSI packages. The configuration of this module is designed to reduce package body size and to lighten the weight. Electrical and thermal performance of this module was carefully considered and estimated by simulation or experiments. This module is called a COCB module which means the Chip On Chip Ball Grid Array module. Two chips are mounted on both top and bottom sides of a small substrate by TAB technology using a new Au-Sn (Au10-40%-Sn) eutectic micro-connection method. Two chips are electrically connected by routing wires and through holes of an interposed substrate respectively. This module is useful when packages are mounted on a board with solder paste, directly to its surface, with some discrete packages on the assembly line. The authors propose the concept of the micro bare chip module.<>
{"title":"Advanced TAB/BGA multi-chip stacked module for high density LSI packages","authors":"M. Mita, T. Kumakura, S. Inoue, Y. Hiraki","doi":"10.1109/MCMC.1994.292524","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292524","url":null,"abstract":"A newly advanced design for a TAB/BGA multi-chip stacked module has been developed for high density LSI packages. The configuration of this module is designed to reduce package body size and to lighten the weight. Electrical and thermal performance of this module was carefully considered and estimated by simulation or experiments. This module is called a COCB module which means the Chip On Chip Ball Grid Array module. Two chips are mounted on both top and bottom sides of a small substrate by TAB technology using a new Au-Sn (Au10-40%-Sn) eutectic micro-connection method. Two chips are electrically connected by routing wires and through holes of an interposed substrate respectively. This module is useful when packages are mounted on a board with solder paste, directly to its surface, with some discrete packages on the assembly line. The authors propose the concept of the micro bare chip module.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127212253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292534
S. Kikuchi, H. Yamamoto, K. Seyama, M. Hirano, K. Moriizumi
FUJITSU has developed an MCM-D technology which uses bare chips on composite thin films for mounting CMOS chips with high density and low cost. The first use of this technology is for the K6000 Series business server. This MCM technology can be applied to a wide range of computers, from workstations to mainframes to reduce costs and improve performance. This paper focuses on the MCM packaging technology, MCM substrate technology, cooling technology and numerical analysis technique.<>
{"title":"High performance MCM-D technology","authors":"S. Kikuchi, H. Yamamoto, K. Seyama, M. Hirano, K. Moriizumi","doi":"10.1109/MCMC.1994.292534","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292534","url":null,"abstract":"FUJITSU has developed an MCM-D technology which uses bare chips on composite thin films for mounting CMOS chips with high density and low cost. The first use of this technology is for the K6000 Series business server. This MCM technology can be applied to a wide range of computers, from workstations to mainframes to reduce costs and improve performance. This paper focuses on the MCM packaging technology, MCM substrate technology, cooling technology and numerical analysis technique.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125888629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292528
K. Drake, M. Abadir, S. Stark, T. Rhyne, M. Eskew, L. Lockwood, K. Salsburg, R. Harr, L. Concha
This paper introduces a new industry alliance of ASEM merchant foundries, customers, EDA vendors, and suppliers. The objective of this Alliance is to establish an interface specification (guide) and an information model for the bidirectional exchange of electronic design data and information between customers and foundries. The goal of this ARPA funded effort is to reduce the barriers in exchanging design and component data/information between customers and foundries, thus minimizing cost and maximizing efficiency in the design-to-manufacture of ASEMs.<>
{"title":"Application specific electronic modules (ASEM) CAD/CAE/CAM interface specification alliance","authors":"K. Drake, M. Abadir, S. Stark, T. Rhyne, M. Eskew, L. Lockwood, K. Salsburg, R. Harr, L. Concha","doi":"10.1109/MCMC.1994.292528","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292528","url":null,"abstract":"This paper introduces a new industry alliance of ASEM merchant foundries, customers, EDA vendors, and suppliers. The objective of this Alliance is to establish an interface specification (guide) and an information model for the bidirectional exchange of electronic design data and information between customers and foundries. The goal of this ARPA funded effort is to reduce the barriers in exchanging design and component data/information between customers and foundries, thus minimizing cost and maximizing efficiency in the design-to-manufacture of ASEMs.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121668824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292515
Yuzhe Chen, Zhonghua Wu, Amit Agrawal, Yaowu Liu, J. Fang
Delta-I noise, which refers to the voltage fluctuations between power and ground conductors caused by sudden current surges, has been well recognized as a limiting factor for the reliable operation of high-speed integrated circuits. A novel technique for modeling Delta-I noise associated with power and ground planes is presented in this paper. This new approach considers not only the wave propagation and resonance in power and ground planes, also the geometry of the interconnections such as the via radius, which results in accurate prediction of the Delta-I noise waveforms. An electromagnetic field solver is employed to model the power/ground planes connected with vias, and is linked to SPICE type circuit solvers to analyze the components off the planes. This simulation technique is found to be very fast in computation speed and also highly accurate. Simulation results are provided together with a comparison of Delta-I analysis performed by the method of this paper and IBM's ASTAP.<>
{"title":"Modeling of Delta-I noise in digital electronics packaging","authors":"Yuzhe Chen, Zhonghua Wu, Amit Agrawal, Yaowu Liu, J. Fang","doi":"10.1109/MCMC.1994.292515","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292515","url":null,"abstract":"Delta-I noise, which refers to the voltage fluctuations between power and ground conductors caused by sudden current surges, has been well recognized as a limiting factor for the reliable operation of high-speed integrated circuits. A novel technique for modeling Delta-I noise associated with power and ground planes is presented in this paper. This new approach considers not only the wave propagation and resonance in power and ground planes, also the geometry of the interconnections such as the via radius, which results in accurate prediction of the Delta-I noise waveforms. An electromagnetic field solver is employed to model the power/ground planes connected with vias, and is linked to SPICE type circuit solvers to analyze the components off the planes. This simulation technique is found to be very fast in computation speed and also highly accurate. Simulation results are provided together with a comparison of Delta-I analysis performed by the method of this paper and IBM's ASTAP.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115340896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292522
A. Halperin, T. Distefano, S. Chiang
Alternating and direct electric currents are applied through the metal interconnections in electronic packaging to detect potential electrical opens, such as line narrowings, notches, nicks, cracks, weak connections, and interface contaminations. Due to the nonlinear relationship between the voltage across and current through the metal conductor, distorted signals are generated by the defect region as well as the good conductor. The signal generated from a latent open defect can be detected by comparing the defect signal phase with the reference phase produced by the good conductor. Application of this technique to electronic packaging development and manufacturing can improve product reliability and reduce cost by early detection of latent open defects.<>
{"title":"Latent open testing of electronic packaging","authors":"A. Halperin, T. Distefano, S. Chiang","doi":"10.1109/MCMC.1994.292522","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292522","url":null,"abstract":"Alternating and direct electric currents are applied through the metal interconnections in electronic packaging to detect potential electrical opens, such as line narrowings, notches, nicks, cracks, weak connections, and interface contaminations. Due to the nonlinear relationship between the voltage across and current through the metal conductor, distorted signals are generated by the defect region as well as the good conductor. The signal generated from a latent open defect can be detected by comparing the defect signal phase with the reference phase produced by the good conductor. Application of this technique to electronic packaging development and manufacturing can improve product reliability and reduce cost by early detection of latent open defects.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114631838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292535
Y.-M. Ting
Summary form only given, as follows. IBM Federal Systems Company, as a prime contractor, has been awarded a $9.5 Million contract by the Advanced Research Projects Agency (ARPA), entitled "Low Volume Access to High Volume Production". The objectives of the contract are the development of a design system that allows customers to enter their design into the IBM Technology Products' Foundry in Hopewell Junction, New York, at various design stages, hybrid chip interconnection technology on a single substrate, participation in the development of industry standards for both known-good-die and the CAD Framework Initiative, and to fabricate, assemble and test multichip modules (MCMs) for use in commercial and military products. The final objective of this contract is to show an order of magnitude reduction in netlist to prototype turn-around-time and non-recurring engineering costs which are consistent with the ARPA ASEM Project goals.<>
{"title":"IBM ARPA ASEM foundry","authors":"Y.-M. Ting","doi":"10.1109/MCMC.1994.292535","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292535","url":null,"abstract":"Summary form only given, as follows. IBM Federal Systems Company, as a prime contractor, has been awarded a $9.5 Million contract by the Advanced Research Projects Agency (ARPA), entitled \"Low Volume Access to High Volume Production\". The objectives of the contract are the development of a design system that allows customers to enter their design into the IBM Technology Products' Foundry in Hopewell Junction, New York, at various design stages, hybrid chip interconnection technology on a single substrate, participation in the development of industry standards for both known-good-die and the CAD Framework Initiative, and to fabricate, assemble and test multichip modules (MCMs) for use in commercial and military products. The final objective of this contract is to show an order of magnitude reduction in netlist to prototype turn-around-time and non-recurring engineering costs which are consistent with the ARPA ASEM Project goals.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134220815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292533
T. Gabara, K. Tai, M. Lau, S. Pei, R. Frye, P. Sullivan
A low power dissipation oscillator circuit in CMOS has been fabricated. The circuit uses inductors and capacitors to form a tank circuit while cross-coupled MOS devices provide the positive feedback to sustain oscillations. The inductors are formed on glass and are solder bumped to the die. The measured power dissipation is 1/10 of the simulated CV/sup 2/F generated by conventional means.<>
{"title":"A 27 mW CMOS RF oscillator operating at 1.2 GHz","authors":"T. Gabara, K. Tai, M. Lau, S. Pei, R. Frye, P. Sullivan","doi":"10.1109/MCMC.1994.292533","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292533","url":null,"abstract":"A low power dissipation oscillator circuit in CMOS has been fabricated. The circuit uses inductors and capacitors to form a tank circuit while cross-coupled MOS devices provide the positive feedback to sustain oscillations. The inductors are formed on glass and are solder bumped to the die. The measured power dissipation is 1/10 of the simulated CV/sup 2/F generated by conventional means.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134149970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292537
W. Hansford
Summary form only given, as follows. The author discusses the status of the ARPA (ASEM) sponsored MCM brokerage service at USC/ISI which interfaces system designers to domestic MCM foundries. The brokerage provides access to low cost, prototype multichip module fabrication. Comparisons are made between interfaces for ICs and MCMs to illustrate how the MOSIS Service has been extended to access MCM-D and MCM-L technologies. This is achieved through cost sharing of tooling and manufacturing along with the use of standard module sizes and packages. A "generic" sample design has been developed and is being implemented in each MCM technology. This design allows testing the interface for fabrication, assembly and test from those existing CAD tools preferred by the foundry. The design will help determine the initial price list and fabrication schedule. The set of standard module sizes has been added to the vendor's design kits which are implemented in commercial MCM CAD tools.<>
{"title":"The ARPA (ASEM) MCM brokerage service","authors":"W. Hansford","doi":"10.1109/MCMC.1994.292537","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292537","url":null,"abstract":"Summary form only given, as follows. The author discusses the status of the ARPA (ASEM) sponsored MCM brokerage service at USC/ISI which interfaces system designers to domestic MCM foundries. The brokerage provides access to low cost, prototype multichip module fabrication. Comparisons are made between interfaces for ICs and MCMs to illustrate how the MOSIS Service has been extended to access MCM-D and MCM-L technologies. This is achieved through cost sharing of tooling and manufacturing along with the use of standard module sizes and packages. A \"generic\" sample design has been developed and is being implemented in each MCM technology. This design allows testing the interface for fabrication, assembly and test from those existing CAD tools preferred by the foundry. The design will help determine the initial price list and fabrication schedule. The set of standard module sizes has been added to the vendor's design kits which are implemented in commercial MCM CAD tools.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"26 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114498326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-03-15DOI: 10.1109/MCMC.1994.292532
M. G. Stout, L. Salmon, G. Rudolph, T. Martinez
The requirement for dense interconnect in artificial neural network systems has led researchers to seek high-density interconnect technologies. This paper reports an implementation using multi-chip modules (MCMs) as the interconnect medium. The specific system described is a self-organizing, parallel, and dynamic learning model which requires a dense interconnect technology for effective implementation; this requirement is fulfilled by exploiting MCM technology. The ideas presented in this paper regarding an MCM implementation of artificial neural networks are versatile and can be adapted to apply to other neural network and connectionist models.<>
{"title":"A multi-chip module implementation of a neural network","authors":"M. G. Stout, L. Salmon, G. Rudolph, T. Martinez","doi":"10.1109/MCMC.1994.292532","DOIUrl":"https://doi.org/10.1109/MCMC.1994.292532","url":null,"abstract":"The requirement for dense interconnect in artificial neural network systems has led researchers to seek high-density interconnect technologies. This paper reports an implementation using multi-chip modules (MCMs) as the interconnect medium. The specific system described is a self-organizing, parallel, and dynamic learning model which requires a dense interconnect technology for effective implementation; this requirement is fulfilled by exploiting MCM technology. The ideas presented in this paper regarding an MCM implementation of artificial neural networks are versatile and can be adapted to apply to other neural network and connectionist models.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124112961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：