Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00096
K. Lata, A. Bansal
In today’s digital world, security is required at each level of the implementation, even for Cryptographic algorithms, as we depend digitally on various needs of our daily life. Also, hackers are trying many ways to hack confidential information, and side-channel attacks are one of them. Key Derivation Functions (KDFs) are the basic and essential components of cryptographic systems; therefore, their security becomes more crucial for such systems. This paper presents the implementation of KDFs based on Block Ciphers and Hash functions (AES-128 and SHA-256, SHA- 512). The key feature of this implementation is that it generates a unique and secure key. Moreover, the generated key is less prone to the Timing side-channel attacks. These KDFs are implemented using high-level language C in Xilinx Vivado HLS. The results show that the proposed design offers a highly secure generated key while mitigating the Timing side-channel attacks possibility. Security analysis is done in terms of Hamming Distance and Avalanche Effects. The reported KDF based on AES-128 operates at 152.3 MHz with a max throughput of 9.728 Gbps, whereas KDF based on Hash Function, i.e., SHA-256 and SHA-512, operate at 108.6 MHz and 118.1 MHz with the max throughput of 2.28 Mbps and 2.28 Mbps, respectively.
{"title":"Timing Side-Channel Attack Resistant Key Derivation Functions for Cryptosystems","authors":"K. Lata, A. Bansal","doi":"10.1109/iSES52644.2021.00096","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00096","url":null,"abstract":"In today’s digital world, security is required at each level of the implementation, even for Cryptographic algorithms, as we depend digitally on various needs of our daily life. Also, hackers are trying many ways to hack confidential information, and side-channel attacks are one of them. Key Derivation Functions (KDFs) are the basic and essential components of cryptographic systems; therefore, their security becomes more crucial for such systems. This paper presents the implementation of KDFs based on Block Ciphers and Hash functions (AES-128 and SHA-256, SHA- 512). The key feature of this implementation is that it generates a unique and secure key. Moreover, the generated key is less prone to the Timing side-channel attacks. These KDFs are implemented using high-level language C in Xilinx Vivado HLS. The results show that the proposed design offers a highly secure generated key while mitigating the Timing side-channel attacks possibility. Security analysis is done in terms of Hamming Distance and Avalanche Effects. The reported KDF based on AES-128 operates at 152.3 MHz with a max throughput of 9.728 Gbps, whereas KDF based on Hash Function, i.e., SHA-256 and SHA-512, operate at 108.6 MHz and 118.1 MHz with the max throughput of 2.28 Mbps and 2.28 Mbps, respectively.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130248701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00107
Mohinish Paturi, Sampath Puvvada, Badhari Sai Ponnuru, Mounika Simhadri, B. S. Egala, A. K. Pradhan
Because of urbanization and industrialization, non-biodegradable garbage is growing at an exponential rate. Industries have their own waste management and treatment divisions to take care of their waste products. However, civilian entities are facing many issues in waste management due to the lack of proper systems for segregating waste materials. This article proposed a unique smart waste management system using Blockchain and Internet of Things (IoT) to simplify the waste segregation with the help of smart bins. The proposed system distributes rewards to users for proper disposal of waste into smart bins using smart contracts. We deployed a prototype model on different test networks to compare its real-time performance. From the experimental analysis, we can conclude that the proposed model performs better on the Matic test network than the Binance Smart Chain (BSC) and Ropsten test networks. Finally, the proposed solution ensures system transparency, traceability, and scalability, as well as eliminating single points of failure (SPoF).
{"title":"Smart Solid Waste Management System Using Blockchain and IoT for Smart Cities","authors":"Mohinish Paturi, Sampath Puvvada, Badhari Sai Ponnuru, Mounika Simhadri, B. S. Egala, A. K. Pradhan","doi":"10.1109/iSES52644.2021.00107","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00107","url":null,"abstract":"Because of urbanization and industrialization, non-biodegradable garbage is growing at an exponential rate. Industries have their own waste management and treatment divisions to take care of their waste products. However, civilian entities are facing many issues in waste management due to the lack of proper systems for segregating waste materials. This article proposed a unique smart waste management system using Blockchain and Internet of Things (IoT) to simplify the waste segregation with the help of smart bins. The proposed system distributes rewards to users for proper disposal of waste into smart bins using smart contracts. We deployed a prototype model on different test networks to compare its real-time performance. From the experimental analysis, we can conclude that the proposed model performs better on the Matic test network than the Binance Smart Chain (BSC) and Ropsten test networks. Finally, the proposed solution ensures system transparency, traceability, and scalability, as well as eliminating single points of failure (SPoF).","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130260653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00031
U. A. Kumar, Ratna Kumari Chintakunta, Surinder Kumar, K. Jamal, Syed Ershad Ahmed
Approximate computing is an emerging paradigm to achieve substantial improvement in the area, speed, and power in image processing applications where exact computation is not required. This paper proposes new approximate unsigned multiplier architectures which aim to reduce the power consumption and area with better accuracy. For the 8-bit multiplier scheme, experimental results show an improvement of 41.4% and 34.02% in power and area respectively, when the proposed design is compared against the exact design, and 22.88% and 26.72% respectively when compared against other approximate designs, without compromising on the accuracy.
{"title":"Approximate Multiplier Architectures for Error Resilient Applications","authors":"U. A. Kumar, Ratna Kumari Chintakunta, Surinder Kumar, K. Jamal, Syed Ershad Ahmed","doi":"10.1109/iSES52644.2021.00031","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00031","url":null,"abstract":"Approximate computing is an emerging paradigm to achieve substantial improvement in the area, speed, and power in image processing applications where exact computation is not required. This paper proposes new approximate unsigned multiplier architectures which aim to reduce the power consumption and area with better accuracy. For the 8-bit multiplier scheme, experimental results show an improvement of 41.4% and 34.02% in power and area respectively, when the proposed design is compared against the exact design, and 22.88% and 26.72% respectively when compared against other approximate designs, without compromising on the accuracy.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128932783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00095
N. Saxena, Ram Venkat Narayanan, Juneet Kumar Meka, R. Vemuri
Logic encryption is a method to improve hardware security by inserting key gates on carefully selected signals in a logic design. Various logic encryption schemes have been proposed in the past decade. Many attack methods to thwart these logic locking schemes have also emerged. The satisfiability (SAT) attack can recover correct keys for many logic obfuscation methods. Recently proposed sensitivity analysis attack can decrypt stripped functionality based logic encryption schemes. This article presents a new encryption scheme named SRTLock, which is resilient against both attacks. SRTLock method first generates 0-injection circuits and encrypts the functionality of these nodes with the key inputs. In the next step, these values are used to control the sensitivity of the functionally stripped output for specific input patterns. The resultant locked circuit is resilient against the SAT and sensitivity analysis attacks. Experimental results demonstrating this on several attacks using standard benchmark circuits are presented.
{"title":"SRTLock: A Sensitivity Resilient Two-Tier Logic Encryption Scheme","authors":"N. Saxena, Ram Venkat Narayanan, Juneet Kumar Meka, R. Vemuri","doi":"10.1109/iSES52644.2021.00095","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00095","url":null,"abstract":"Logic encryption is a method to improve hardware security by inserting key gates on carefully selected signals in a logic design. Various logic encryption schemes have been proposed in the past decade. Many attack methods to thwart these logic locking schemes have also emerged. The satisfiability (SAT) attack can recover correct keys for many logic obfuscation methods. Recently proposed sensitivity analysis attack can decrypt stripped functionality based logic encryption schemes. This article presents a new encryption scheme named SRTLock, which is resilient against both attacks. SRTLock method first generates 0-injection circuits and encrypts the functionality of these nodes with the key inputs. In the next step, these values are used to control the sensitivity of the functionally stripped output for specific input patterns. The resultant locked circuit is resilient against the SAT and sensitivity analysis attacks. Experimental results demonstrating this on several attacks using standard benchmark circuits are presented.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120961798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00040
Sai Akash Dusi, B. T. Sundari
Silicon has been the major driving force behind the technological advancement of humanity for the past 50 years. Silicon is used for manufacturing transistors, memory, Printed Circuit Broads, etc. Gordon Moore predicted that “the number of transistors on a silicon chip would double approximately every eighteen months”. The semiconductor industry had taken this prediction as the primary driving force behind the innovation of faster and efficient electronics manufacturing. This is achieved by miniaturizing devices, also know as scaling. Silicon is limited by performance degradation due to effects such as band to band tunneling, scattering phenomenon, etc, so the search to replace silicon in semiconductors has started. Many different methods to increase performance and efficiency were introduced before jumping wagon to beyond silicon materials such as designing 3-D transistors, FINFETs, replacing Silicon Dioxide with high-k dielectrics, etc. These proved to be increasing the manufacturing costs. The prime candidates for replacing Silicon are Carbon based materials, owing to their extraordinary electronic, thermal, optical and mechanical properties. The most researched are Carbon Nano Tubes and Graphene. The work focuses on modelling a Bilayer Graphene Field Effect Transistor with different mobility of holes and electrons taken into consideration.
{"title":"Bilayer Graphene Field Effect Transistor Modelling with Improved Mobility Analysis","authors":"Sai Akash Dusi, B. T. Sundari","doi":"10.1109/iSES52644.2021.00040","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00040","url":null,"abstract":"Silicon has been the major driving force behind the technological advancement of humanity for the past 50 years. Silicon is used for manufacturing transistors, memory, Printed Circuit Broads, etc. Gordon Moore predicted that “the number of transistors on a silicon chip would double approximately every eighteen months”. The semiconductor industry had taken this prediction as the primary driving force behind the innovation of faster and efficient electronics manufacturing. This is achieved by miniaturizing devices, also know as scaling. Silicon is limited by performance degradation due to effects such as band to band tunneling, scattering phenomenon, etc, so the search to replace silicon in semiconductors has started. Many different methods to increase performance and efficiency were introduced before jumping wagon to beyond silicon materials such as designing 3-D transistors, FINFETs, replacing Silicon Dioxide with high-k dielectrics, etc. These proved to be increasing the manufacturing costs. The prime candidates for replacing Silicon are Carbon based materials, owing to their extraordinary electronic, thermal, optical and mechanical properties. The most researched are Carbon Nano Tubes and Graphene. The work focuses on modelling a Bilayer Graphene Field Effect Transistor with different mobility of holes and electrons taken into consideration.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115318266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00053
Jaya Dofe, Aaron Nguyen, Andy Nguyen
The Internet of Things (IoT) impacts how we interact with the world around us for good. While IoT benefits are undeniable, it is a double-edged sword. The security aspect is the major concern in the IoT realm, especially side-channel attacks since there are abundant channels due to physical effects. IoT devices have been widely used in many fields of production and social living, such as healthcare, energy and industrial automation and military application, to name a few. Much research focuses on software, network, and cloud security; however, hardware security in these devices has been overlooked. The low-power, heterogeneous and resource-constrained nature of IoT devices makes incorporating security features extremely challenging. Conventional security measures, such as encryption, are infeasible for deployment under such constraints. This survey paper discusses the existing countermeasures for isolated side-channel attacks (SCA) and then dives into unified countermeasures that benefit IoT devices to address the area footprint and power constraints. Further, to defeat the IoT system from the advanced SCA, we proposed to use 3D integration as an IoT platform. 3D technology provides various advantages such as heterogeneous integration, split manufacturing, disparate technologies for IoT like MEMS sensors, etc., making 3D integration the best choice for IoT platforms.
{"title":"Unified Countermeasures against Physical Attacks in Internet of Things - A survey","authors":"Jaya Dofe, Aaron Nguyen, Andy Nguyen","doi":"10.1109/iSES52644.2021.00053","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00053","url":null,"abstract":"The Internet of Things (IoT) impacts how we interact with the world around us for good. While IoT benefits are undeniable, it is a double-edged sword. The security aspect is the major concern in the IoT realm, especially side-channel attacks since there are abundant channels due to physical effects. IoT devices have been widely used in many fields of production and social living, such as healthcare, energy and industrial automation and military application, to name a few. Much research focuses on software, network, and cloud security; however, hardware security in these devices has been overlooked. The low-power, heterogeneous and resource-constrained nature of IoT devices makes incorporating security features extremely challenging. Conventional security measures, such as encryption, are infeasible for deployment under such constraints. This survey paper discusses the existing countermeasures for isolated side-channel attacks (SCA) and then dives into unified countermeasures that benefit IoT devices to address the area footprint and power constraints. Further, to defeat the IoT system from the advanced SCA, we proposed to use 3D integration as an IoT platform. 3D technology provides various advantages such as heterogeneous integration, split manufacturing, disparate technologies for IoT like MEMS sensors, etc., making 3D integration the best choice for IoT platforms.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131637559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00065
P. Joshi, Debanjan Das, Venkanna Udutalapally, S. Misra
Ensuring higher crop yield helps in optimal utilisation of available land and man power along with agriculture inputs. Factors such as poor crop health, soil infertility and limited access to resources lead to low crop yield. Existing solutions offer cloud based services to the farmers which are not available to farmers residing in remote areas with no internet access. To prevent this, FarmEdge introduces an end-to-end edge based unified computing platform in the form of an android application - Hamar Kisaan for rural farmers to monitor crop field, track real time developments and propose solutions for higher crop yield. The crop health monitoring feature of Hamar Kisaan with an accuracy of 94.2% when paired with soil health monitoring enabled by IoT Krishi nodes, provides a one stop agriculture solution for the farmer community.
确保更高的作物产量有助于优化利用可用土地和人力以及农业投入。作物健康状况差、土壤不孕症和获取资源的机会有限等因素导致作物产量低。现有的解决方案为农民提供基于云的服务，而这些服务对于居住在没有互联网接入的偏远地区的农民来说是不可用的。为了防止这种情况，FarmEdge引入了一个基于端到端边缘的统一计算平台，以android应用程序的形式- Hamar Kisaan，用于农村农民监控农田，跟踪实时发展并提出提高作物产量的解决方案。Hamar Kisaan的作物健康监测功能与物联网Krishi节点支持的土壤健康监测相结合，准确率为94.2%，为农民社区提供一站式农业解决方案。
{"title":"FarmEdge: A Unified Edge Computing Framework Enabling Digital Agriculture","authors":"P. Joshi, Debanjan Das, Venkanna Udutalapally, S. Misra","doi":"10.1109/iSES52644.2021.00065","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00065","url":null,"abstract":"Ensuring higher crop yield helps in optimal utilisation of available land and man power along with agriculture inputs. Factors such as poor crop health, soil infertility and limited access to resources lead to low crop yield. Existing solutions offer cloud based services to the farmers which are not available to farmers residing in remote areas with no internet access. To prevent this, FarmEdge introduces an end-to-end edge based unified computing platform in the form of an android application - Hamar Kisaan for rural farmers to monitor crop field, track real time developments and propose solutions for higher crop yield. The crop health monitoring feature of Hamar Kisaan with an accuracy of 94.2% when paired with soil health monitoring enabled by IoT Krishi nodes, provides a one stop agriculture solution for the farmer community.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126717297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00051
R. Selvam, A. Tyagi
In power side-channel attacks (SCA), the adversary observes the power leakage at the external power pin to reverse engineer the secrets embedded in sensitive circuits. Mitigation techniques are often integrated into the logic to make power consumption data independent. In this paper, we develop a new design strategy for designing the on-chip power distribution network using a decoupling capacitance to thwart the power side-channel attack. The decoupling capacitances are introduced along the power lanes in a distributed fashion, to suppress the data-leakage from the sensitive-circuit. To facilitate the computer-aided design of such PDNs, we also develop approximate heuristics to extract feature vectors from the current (I) profile of the internal logic blocks, and for feature vector propagation over the on-chip power distribution network. We study the sensitivity of decoupling capacitance value and its placement over the power distribution network. Finally, we evaluate the side-channel resistance with and without decoupling capacitance using Spice level simulations. Machine Learning (ML) classifiers are used to quantify the side-channel strength in terms of success rate for power side-channel adversary. A 100pf decoupling capacitance, in some cases, reduces the ML success rate from 80% to 21% to provide significant SCA resistance.
{"title":"Power Distribution Network Capacitive Decoupling for Side-Channel Resistance","authors":"R. Selvam, A. Tyagi","doi":"10.1109/iSES52644.2021.00051","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00051","url":null,"abstract":"In power side-channel attacks (SCA), the adversary observes the power leakage at the external power pin to reverse engineer the secrets embedded in sensitive circuits. Mitigation techniques are often integrated into the logic to make power consumption data independent. In this paper, we develop a new design strategy for designing the on-chip power distribution network using a decoupling capacitance to thwart the power side-channel attack. The decoupling capacitances are introduced along the power lanes in a distributed fashion, to suppress the data-leakage from the sensitive-circuit. To facilitate the computer-aided design of such PDNs, we also develop approximate heuristics to extract feature vectors from the current (I) profile of the internal logic blocks, and for feature vector propagation over the on-chip power distribution network. We study the sensitivity of decoupling capacitance value and its placement over the power distribution network. Finally, we evaluate the side-channel resistance with and without decoupling capacitance using Spice level simulations. Machine Learning (ML) classifiers are used to quantify the side-channel strength in terms of success rate for power side-channel adversary. A 100pf decoupling capacitance, in some cases, reduces the ML success rate from 80% to 21% to provide significant SCA resistance.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122573587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00064
Puspendu Biswas Paul, S. Biswas, A. Bairagi, Mehedi Masud
With the advancement of modern technology, traditional agriculture is drastically changing, especially with the utilization of Information and Communication Technology (ICT). Ubiquitous sensors and the Internet of Things (IoT) are being used independently for helping the farmers to understand better the condition of overall field condition targeting to monitor soil characteristics, climatic conditions, humidity, temperature, etc. These sensors and systems work individually and produce different data that requires analysis to understand. The typical process is time-consuming, and farmers should have technological knowledge. Contrary, most of the farmers are not technologically advanced to understand the term. A ready-made result can help farmers quick decision-making. In this paper, we have developed a remote field monitoring and controlling IoT system architecture. The system process and analyze the collected data to prepare a ready-made report for farmers with suggestions for further steps. It leverages the management process with real-time monitoring, nursing (i.e., irrigation, pesticide distribution, etc.), ultimately increasing productivity. The overall system records every successful case, and machine learning-based prediction helps further nursing guidelines.
{"title":"Data-Driven Decision Making for Smart Cultivation","authors":"Puspendu Biswas Paul, S. Biswas, A. Bairagi, Mehedi Masud","doi":"10.1109/iSES52644.2021.00064","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00064","url":null,"abstract":"With the advancement of modern technology, traditional agriculture is drastically changing, especially with the utilization of Information and Communication Technology (ICT). Ubiquitous sensors and the Internet of Things (IoT) are being used independently for helping the farmers to understand better the condition of overall field condition targeting to monitor soil characteristics, climatic conditions, humidity, temperature, etc. These sensors and systems work individually and produce different data that requires analysis to understand. The typical process is time-consuming, and farmers should have technological knowledge. Contrary, most of the farmers are not technologically advanced to understand the term. A ready-made result can help farmers quick decision-making. In this paper, we have developed a remote field monitoring and controlling IoT system architecture. The system process and analyze the collected data to prepare a ready-made report for farmers with suggestions for further steps. It leverages the management process with real-time monitoring, nursing (i.e., irrigation, pesticide distribution, etc.), ultimately increasing productivity. The overall system records every successful case, and machine learning-based prediction helps further nursing guidelines.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123416847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00033
G. Ramya, S. Nanda
A hyperspectral image collects the spectral information across the electromagnetic spectrum as a continuous set of hundreds of bands with a very narrow bandwidths ranging from 5-10nm. The bands are high correlated with each other and some of the bands carry negligible information. So, there is a need to reduce the dimensionality of the hyperspectral image. Thus the aim is to extract only those bands which are informative and eliminate the noisy and redundant bands. If the redundant bands are eliminated, the dimensionality of the hyperspectral image reduces. This reduction in dimensionality reduces the cost of computation and increases the accuracy of the analysis. In this paper, a dimension reduction technique based on binary multi-objective CLONAL algorithm has been proposed. The method uses two objective functions as entropy and Pearson correlation. The extracted spectral bands are taken and extracted hyperspectral image obtained is segmented using K-modes algorithm. Comparative results reveal superior performance of band selection by the proposed method over NSGA-II, BSSO and PCA based reduction.
{"title":"A Binary Multi-objective CLONAL Algorithm for Band Selection in Hyper-Spectral Images","authors":"G. Ramya, S. Nanda","doi":"10.1109/iSES52644.2021.00033","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00033","url":null,"abstract":"A hyperspectral image collects the spectral information across the electromagnetic spectrum as a continuous set of hundreds of bands with a very narrow bandwidths ranging from 5-10nm. The bands are high correlated with each other and some of the bands carry negligible information. So, there is a need to reduce the dimensionality of the hyperspectral image. Thus the aim is to extract only those bands which are informative and eliminate the noisy and redundant bands. If the redundant bands are eliminated, the dimensionality of the hyperspectral image reduces. This reduction in dimensionality reduces the cost of computation and increases the accuracy of the analysis. In this paper, a dimension reduction technique based on binary multi-objective CLONAL algorithm has been proposed. The method uses two objective functions as entropy and Pearson correlation. The extracted spectral bands are taken and extracted hyperspectral image obtained is segmented using K-modes algorithm. Comparative results reveal superior performance of band selection by the proposed method over NSGA-II, BSSO and PCA based reduction.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122001401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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