Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00041
K. Kumar, K. Reddy, V. Pudi, S. Bodapati
In this paper, we designed a CNTFET based Systolic serial parallel multiplier. This systolic serial parallel multiplier is 100% efficient and operates on selection of either 0, X, 2X, 3X product terms, where X is a serial input to the multiplier. This multiplier design requires modules like 4$times$ 1 MUX, 2$times$ 1 MUX, OR gate, Full Adder, and Delay elements known as D-Flipflops. In this paper, we have used Gate Diffusion Input (GDI) technique for designing combinational logic gates to reduce the area and power. This multiplier design require more number of D-Flipflops compared to other logic circuits. In this paper we proposed a new D-Flipflop with 10 transistors with a single clock load and a IOT-based full adder design to reduce area and power consumption. The proposed systolic serial parallel multiplier has a saving of 41% of area compared to recent design. Our simulation results shows that proposed systolic serial parallel multiplier design has a reduction in transistor count by 82.65%, a drop in power dissipation by 95.96%, decrease in delay by 98.12% and a decrease in PDP by 99.92% compared to the existing systolic array multiplier.
{"title":"Design of Low Area and Low Power Systolic Serial Parallel Multiplier using CNTFETs","authors":"K. Kumar, K. Reddy, V. Pudi, S. Bodapati","doi":"10.1109/iSES52644.2021.00041","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00041","url":null,"abstract":"In this paper, we designed a CNTFET based Systolic serial parallel multiplier. This systolic serial parallel multiplier is 100% efficient and operates on selection of either 0, X, 2X, 3X product terms, where X is a serial input to the multiplier. This multiplier design requires modules like 4$times$ 1 MUX, 2$times$ 1 MUX, OR gate, Full Adder, and Delay elements known as D-Flipflops. In this paper, we have used Gate Diffusion Input (GDI) technique for designing combinational logic gates to reduce the area and power. This multiplier design require more number of D-Flipflops compared to other logic circuits. In this paper we proposed a new D-Flipflop with 10 transistors with a single clock load and a IOT-based full adder design to reduce area and power consumption. The proposed systolic serial parallel multiplier has a saving of 41% of area compared to recent design. Our simulation results shows that proposed systolic serial parallel multiplier design has a reduction in transistor count by 82.65%, a drop in power dissipation by 95.96%, decrease in delay by 98.12% and a decrease in PDP by 99.92% compared to the existing systolic array multiplier.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123728605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00078
S. Rekha, K. Suraj, K. S. Kumar
Globalization of semiconductor design and manufacturing process has led to several hardware security issues in last two decades is well known. Counterfeit electronic parts entering the supply chain as genuine chips lead to loss of revenue and reputation for chip makers and counterfeit parts will have serious reliability issues, which will harm customers. Research towards mitigating the counterfeit parts entering supply chains is well researched topic in last one decade and IC traceability is one such technique. Blockchain based IC traceability techniques are also proposed and existing IC traceability techniques keep track of ICs in the post sales domain means how IC ownership change hands from Original Design Manufacturer (ODM) to end user through sales channel. Fabless chip makers depend upon multiple contract firms to manufacture the chips and Outsourced Test and Assembly (OSAT) centers to test the chips. Fabless chip makers must keep track of chips coming from multiple foundries and several OSAT centers and IC traceability techniques will be helpful in this task. In this paper, we propose an IC traceability technique which facilitates fabless ODMs to keep track of IC from fabrication and test facilities along with sales channel.
{"title":"A Holistic Blockchain Based IC Traceability Technique","authors":"S. Rekha, K. Suraj, K. S. Kumar","doi":"10.1109/iSES52644.2021.00078","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00078","url":null,"abstract":"Globalization of semiconductor design and manufacturing process has led to several hardware security issues in last two decades is well known. Counterfeit electronic parts entering the supply chain as genuine chips lead to loss of revenue and reputation for chip makers and counterfeit parts will have serious reliability issues, which will harm customers. Research towards mitigating the counterfeit parts entering supply chains is well researched topic in last one decade and IC traceability is one such technique. Blockchain based IC traceability techniques are also proposed and existing IC traceability techniques keep track of ICs in the post sales domain means how IC ownership change hands from Original Design Manufacturer (ODM) to end user through sales channel. Fabless chip makers depend upon multiple contract firms to manufacture the chips and Outsourced Test and Assembly (OSAT) centers to test the chips. Fabless chip makers must keep track of chips coming from multiple foundries and several OSAT centers and IC traceability techniques will be helpful in this task. In this paper, we propose an IC traceability technique which facilitates fabless ODMs to keep track of IC from fabrication and test facilities along with sales channel.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121843545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00038
K. G. Shreeharsha, Charudatta Korde, M. H. Vasantha, Y. B. N. Kumar
In this paper, a particle swarm optimization (PSO) based solution is proposed for the training of generative adversarial networks (GANs). Conventional GAN networks take around 5x times more number of iterations to generate plausible images compared to the proposed method, thereby increasing the simulation time and decreasing the Frechet Inception Distance (FID) score. To overcome the problems of non-convergence and mode collapse associated with the conventional GANs, proposed work uses a PSO algorithm to stabilize the inertia weights during the training duration followed by conventional optimization method for the remaining iterations. The proposed solution is implemented on Nvidia Tesla VI00-PCIE-16GB GPU, using tensorflow and keras. The efficiency of the proposed solution is verified using MNIST dataset. The results showed that the iteration at which images are generated for the proposed method is faster as compared to the conventional GAN architectures, quantified with lower FID score.
本文提出了一种基于粒子群优化(PSO)的生成对抗网络(gan)训练方法。与提出的方法相比，传统的GAN网络需要大约5倍的迭代次数来生成可信的图像，从而增加了模拟时间并降低了Frechet Inception Distance (FID)分数。为了克服传统gan存在的不收敛性和模态崩溃问题，本文采用粒子群算法稳定训练期间的惯性权值，然后采用常规优化方法对剩余迭代进行优化。该方案在Nvidia Tesla VI00-PCIE-16GB GPU上使用tensorflow和keras实现。利用MNIST数据集验证了该方法的有效性。结果表明，与传统的GAN架构相比，该方法生成图像的迭代速度更快，FID评分更低。
{"title":"Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm","authors":"K. G. Shreeharsha, Charudatta Korde, M. H. Vasantha, Y. B. N. Kumar","doi":"10.1109/iSES52644.2021.00038","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00038","url":null,"abstract":"In this paper, a particle swarm optimization (PSO) based solution is proposed for the training of generative adversarial networks (GANs). Conventional GAN networks take around 5x times more number of iterations to generate plausible images compared to the proposed method, thereby increasing the simulation time and decreasing the Frechet Inception Distance (FID) score. To overcome the problems of non-convergence and mode collapse associated with the conventional GANs, proposed work uses a PSO algorithm to stabilize the inertia weights during the training duration followed by conventional optimization method for the remaining iterations. The proposed solution is implemented on Nvidia Tesla VI00-PCIE-16GB GPU, using tensorflow and keras. The efficiency of the proposed solution is verified using MNIST dataset. The results showed that the iteration at which images are generated for the proposed method is faster as compared to the conventional GAN architectures, quantified with lower FID score.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127847390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the increasing complexity of system-on-chip (SoC) designs, security has become a vital requirement. The confidentiality and integrity of critical information, access controls as well as chip authentication at both software and hardware levels should be guaranteed for SoCs. A secure and trusted component is necessary to provide those required security and trust mechanisms in SoCs. The goal of this component is to provide support for security-critical operations and functionalities like provisioning and protection of assets, watermark generation, intellectual property (IP) unlocking, as well as providing isolation at the hardware and software levels. In this paper, we provide a comprehensive overview of the requirements and components for the design of a root-of-trust (RoT) termed as Security Engine that protects against various attacks at the manufacturing floor and during in-field operations while providing security-critical functionalities and features. In addition to that, we identify several critical protocols and security policies for RoT. Policies ensure secure operations and safe transfer of assets while maintaining confidentiality and integrity. Policies are in the form of access control, data integrity and retention, encryption, and asset management for a Security Engine. Similarly, we identify several critical functionalities and protocols of the SoC development like secure boot, self-test, provisioning protocols, security IPs, watermark generation, secure debug, etc., and give a conceivable solution for every one of them with the assistance of the proposed Security Engine while making not many presumptions. Policies and protocols can be implemented in hardware and software with minimum overhead. They can also be checked and enforced by integrating them into the firmware code of the RoT processor. Moreover, this paper will define different types of security policies like access control, data integrity and retention, encryption, and asset management policy for a Security Engine, which is the hub of security operations in an SoC.
{"title":"Required Policies and Properties of the Security Engine of an SoC","authors":"Sajeed Mohammad, Mridha Md Mashahedur Rahman, Farimah Farahmandi","doi":"10.1109/iSES52644.2021.00100","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00100","url":null,"abstract":"With the increasing complexity of system-on-chip (SoC) designs, security has become a vital requirement. The confidentiality and integrity of critical information, access controls as well as chip authentication at both software and hardware levels should be guaranteed for SoCs. A secure and trusted component is necessary to provide those required security and trust mechanisms in SoCs. The goal of this component is to provide support for security-critical operations and functionalities like provisioning and protection of assets, watermark generation, intellectual property (IP) unlocking, as well as providing isolation at the hardware and software levels. In this paper, we provide a comprehensive overview of the requirements and components for the design of a root-of-trust (RoT) termed as Security Engine that protects against various attacks at the manufacturing floor and during in-field operations while providing security-critical functionalities and features. In addition to that, we identify several critical protocols and security policies for RoT. Policies ensure secure operations and safe transfer of assets while maintaining confidentiality and integrity. Policies are in the form of access control, data integrity and retention, encryption, and asset management for a Security Engine. Similarly, we identify several critical functionalities and protocols of the SoC development like secure boot, self-test, provisioning protocols, security IPs, watermark generation, secure debug, etc., and give a conceivable solution for every one of them with the assistance of the proposed Security Engine while making not many presumptions. Policies and protocols can be implemented in hardware and software with minimum overhead. They can also be checked and enforced by integrating them into the firmware code of the RoT processor. Moreover, this paper will define different types of security policies like access control, data integrity and retention, encryption, and asset management policy for a Security Engine, which is the hub of security operations in an SoC.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132302654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00086
Gaurav Jain, A. Joshi, R. Maddila, S. Vipparthi
Hemoglobin is a protein in Red Blood Cells (RBC) which supplies oxygen to the human body. A person’s hemoglobin becomes glycosylated as per the increase in the level of blood sugar. Glycated hemoglobin (HbA1c) is a widely used measure of glycemic control which measures the glucose attached to hemoglobin. Different methods are adopted and utilized for the measurement of HbA1c. Several invasive methods are widely used in pathological laboratories across the globe. The current status of non-invasive HbA1c and blood glucose measurement techniques is summarized in this paper.
{"title":"A Review of Non-Invasive HbA1c and Blood Glucose Measurement Methods","authors":"Gaurav Jain, A. Joshi, R. Maddila, S. Vipparthi","doi":"10.1109/iSES52644.2021.00086","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00086","url":null,"abstract":"Hemoglobin is a protein in Red Blood Cells (RBC) which supplies oxygen to the human body. A person’s hemoglobin becomes glycosylated as per the increase in the level of blood sugar. Glycated hemoglobin (HbA1c) is a widely used measure of glycemic control which measures the glucose attached to hemoglobin. Different methods are adopted and utilized for the measurement of HbA1c. Several invasive methods are widely used in pathological laboratories across the globe. The current status of non-invasive HbA1c and blood glucose measurement techniques is summarized in this paper.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132781767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00018
Vinod Kumar, Ram Murti Rawat
In this paper Swing restoring inverter (SRI), a fast speed and low power circuit technology for VLSI applications that is discussed. In this technology, high speed low power SRAMs circuit performance is achieved by using an SRI to execute threshold voltage reductions and a swing restoring circuit of the latch kind to drive dual node voltages. Cadence Virtuoso schematics tool was used to design an SRI-based SRAM circuit with 130 nm technology for very high speed, low-power VLSI applications. This Paper is organized as follows: - I. Introduction II. Related work III. The proposed work IV. Results and discussion and V. Conclusion.
{"title":"Low Power Swing Restoration Circuit Reduce Threshold Voltages of SRAMs Improve Read and Write Operations","authors":"Vinod Kumar, Ram Murti Rawat","doi":"10.1109/iSES52644.2021.00018","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00018","url":null,"abstract":"In this paper Swing restoring inverter (SRI), a fast speed and low power circuit technology for VLSI applications that is discussed. In this technology, high speed low power SRAMs circuit performance is achieved by using an SRI to execute threshold voltage reductions and a swing restoring circuit of the latch kind to drive dual node voltages. Cadence Virtuoso schematics tool was used to design an SRI-based SRAM circuit with 130 nm technology for very high speed, low-power VLSI applications. This Paper is organized as follows: - I. Introduction II. Related work III. The proposed work IV. Results and discussion and V. Conclusion.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133519483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00020
Tejal Dave, U. Pandya, M. Joshi
Continuous monitoring of blood pressure (BP) can control hypertension and cardiac diseases. Blood pressure measurement using cuff based technique provides intermittent measurement and inconvenient for long term monitoring. This work is focused on estimation of continuous blood pressure from electrocardiogram (ECG) and photoplethysmogram (PPG). The proposed work extracts ECG and PPG time domain features acquired through wireless hardware system. Using Support Vector Regression of machine learning, a light weight model for Blood Pressure estimation is trained. The proposed work is tested on wireless signals captured from 87 subjects using hardware device. According to the British Hypertension Society (BHS) standard, the proposed method achieves grade A in the estimation of systolic and diastolic pressure for wireless data. The values of mean error and standard deviation by proposed method are within limits of Association for the Advancement of Medical Instrumentation (AAMI) standards. The proposed work is helpful in wireless monitoring of patients to track the physiological conditions without interrupting their routine activities.
{"title":"Cuff-less Blood Pressure measurement from Wireless ECG and PPG signals","authors":"Tejal Dave, U. Pandya, M. Joshi","doi":"10.1109/iSES52644.2021.00020","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00020","url":null,"abstract":"Continuous monitoring of blood pressure (BP) can control hypertension and cardiac diseases. Blood pressure measurement using cuff based technique provides intermittent measurement and inconvenient for long term monitoring. This work is focused on estimation of continuous blood pressure from electrocardiogram (ECG) and photoplethysmogram (PPG). The proposed work extracts ECG and PPG time domain features acquired through wireless hardware system. Using Support Vector Regression of machine learning, a light weight model for Blood Pressure estimation is trained. The proposed work is tested on wireless signals captured from 87 subjects using hardware device. According to the British Hypertension Society (BHS) standard, the proposed method achieves grade A in the estimation of systolic and diastolic pressure for wireless data. The values of mean error and standard deviation by proposed method are within limits of Association for the Advancement of Medical Instrumentation (AAMI) standards. The proposed work is helpful in wireless monitoring of patients to track the physiological conditions without interrupting their routine activities.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130512068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00094
Mahendra Rathor, A. Sengupta
Intellectual property (IP) piracy has emerged as a potential hardware security threat in the last few decades. Growing usage of electronic systems in critical applications such as military and healthcare entails integrating only authentic functional blocks or IP cores into the system-on-chips (SoCs). The usage of only authentic IP cores can be ensured by detecting the designer’s secret information hidden into the IP core designs, thereby protecting from the pirated or fake IPs. This paper proposes first time the designer’s handwritten signature biometric based authentication of IP cores. In this paper, a digest of the designer’s signature biometric is generated using the proposed approach. Further, the digest of the signature biometric is mapped into the corresponding hardware security constraints to be implanted into the IP core design during the behavioral synthesis process. The presence of designer’s signature biometric into the IP core design ensures unique identification of the genuine vendor during authentication. The robustness of the proposed approach has been measured using a probability of coincidence metric based security analysis. Finally, the results reveal that the proposed approach yields higher security at negligible cost overhead.
{"title":"Signature Biometric based Authentication of IP Cores for Secure Electronic Systems","authors":"Mahendra Rathor, A. Sengupta","doi":"10.1109/iSES52644.2021.00094","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00094","url":null,"abstract":"Intellectual property (IP) piracy has emerged as a potential hardware security threat in the last few decades. Growing usage of electronic systems in critical applications such as military and healthcare entails integrating only authentic functional blocks or IP cores into the system-on-chips (SoCs). The usage of only authentic IP cores can be ensured by detecting the designer’s secret information hidden into the IP core designs, thereby protecting from the pirated or fake IPs. This paper proposes first time the designer’s handwritten signature biometric based authentication of IP cores. In this paper, a digest of the designer’s signature biometric is generated using the proposed approach. Further, the digest of the signature biometric is mapped into the corresponding hardware security constraints to be implanted into the IP core design during the behavioral synthesis process. The presence of designer’s signature biometric into the IP core design ensures unique identification of the genuine vendor during authentication. The robustness of the proposed approach has been measured using a probability of coincidence metric based security analysis. Finally, the results reveal that the proposed approach yields higher security at negligible cost overhead.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130032292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00098
Narahari Komanduri, S. Sankaran
Access Points (AP) are traditionally used to provide cost-effective, high speed Wi-Fi connectivity to homes, organizations and communities. Despite Wi-Fi providing numerous benefits such as flexibility, scalability and ease of deployment, it is susceptible to numerous vulnerabilities due to the presence of rogue access points (Rogue AP). In particular, intruders can eavesdrop, exploit, launch remote backdoors and manipulate legitimate clients and APs through Rogue APs thus leading to data breaches or possible network compromise. In this work, we build a real-time Wireless LAN testbed using commodity Wi-Fi devices such as Wi-Fi Pineapple Nano that acts as a rogue AP. Further, we perform different attacks on 802.11 Association process between clients and access points through the rogue AP and analyze their impact on the overall performance. Finally, we leverage a sniffer to capture genuine and malicious traffic and develop a mechanism for signature-based detection for mitigating the attacks caused by rogue APs. Evaluation shows that the proposed signature-based approach effectively detects the attacks caused by rogue APs with a detection rate of 91%.
{"title":"Experimental Assessment of Wireless LANs against Rogue Access Points","authors":"Narahari Komanduri, S. Sankaran","doi":"10.1109/iSES52644.2021.00098","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00098","url":null,"abstract":"Access Points (AP) are traditionally used to provide cost-effective, high speed Wi-Fi connectivity to homes, organizations and communities. Despite Wi-Fi providing numerous benefits such as flexibility, scalability and ease of deployment, it is susceptible to numerous vulnerabilities due to the presence of rogue access points (Rogue AP). In particular, intruders can eavesdrop, exploit, launch remote backdoors and manipulate legitimate clients and APs through Rogue APs thus leading to data breaches or possible network compromise. In this work, we build a real-time Wireless LAN testbed using commodity Wi-Fi devices such as Wi-Fi Pineapple Nano that acts as a rogue AP. Further, we perform different attacks on 802.11 Association process between clients and access points through the rogue AP and analyze their impact on the overall performance. Finally, we leverage a sniffer to capture genuine and malicious traffic and develop a mechanism for signature-based detection for mitigating the attacks caused by rogue APs. Evaluation shows that the proposed signature-based approach effectively detects the attacks caused by rogue APs with a detection rate of 91%.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130243675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00052
Jayadeep Akasam, C. Anoop
The paper presents a simple operational amplifier based circuit that can emulate different types of behaviour including hyper chaotic attractor. The circuit implements the governing jerk equations using few integrators and a non-linear Opamp acting as a comparator. The mathematical foundation behind the working of this circuit is established in the paper. Further, the performance of the circuit is studied using simulation studies in LTspice software. A hardware model of the circuit is developed and tested. Results from these studies show the ability of the emulator circuit to generate various waveforms such as hyper chaotic waveforms, chaotic waveforms and periodic attractors. The developed circuit can be used for random number generation which in turn can be used in encryption studies, design of secure communication system, etc.
{"title":"Studies on a Operational-Amplifier Based Circuit for Simple and Hyper Chaotic Signal Emulation","authors":"Jayadeep Akasam, C. Anoop","doi":"10.1109/iSES52644.2021.00052","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00052","url":null,"abstract":"The paper presents a simple operational amplifier based circuit that can emulate different types of behaviour including hyper chaotic attractor. The circuit implements the governing jerk equations using few integrators and a non-linear Opamp acting as a comparator. The mathematical foundation behind the working of this circuit is established in the paper. Further, the performance of the circuit is studied using simulation studies in LTspice software. A hardware model of the circuit is developed and tested. Results from these studies show the ability of the emulator circuit to generate various waveforms such as hyper chaotic waveforms, chaotic waveforms and periodic attractors. The developed circuit can be used for random number generation which in turn can be used in encryption studies, design of secure communication system, etc.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128392988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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