Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00060
Anitha Subramanian, S. C. Sethuraman, Ritwik Badola, Priyam Sahoo, N. Kumaravelu
The need for automated prosthetic arms for managing upper limbs is growing, however prosthetic arms available in the market perform predefined functions that might seem alien to the user and many smart prosthetic arms require various user inputs to properly perform desired grips and perform functions. This research involves developing a prototype for the same by designing and making it operational using - a smart arm capable of detecting objects and adjusting it’s grip appropriate for the detected object. The device is capable of autonomously identifying an object and it’s position using a camera embedded in the arm. It utilizes the arm including the wrist with a two degree-of-freedom to track and orient itself relative to the object, and then finally apply appropriate grip that are prerecorded using leap-motion sensor.
{"title":"Vision enabled Smart Prosthetic Arm for Amputees","authors":"Anitha Subramanian, S. C. Sethuraman, Ritwik Badola, Priyam Sahoo, N. Kumaravelu","doi":"10.1109/iSES52644.2021.00060","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00060","url":null,"abstract":"The need for automated prosthetic arms for managing upper limbs is growing, however prosthetic arms available in the market perform predefined functions that might seem alien to the user and many smart prosthetic arms require various user inputs to properly perform desired grips and perform functions. This research involves developing a prototype for the same by designing and making it operational using - a smart arm capable of detecting objects and adjusting it’s grip appropriate for the detected object. The device is capable of autonomously identifying an object and it’s position using a camera embedded in the arm. It utilizes the arm including the wrist with a two degree-of-freedom to track and orient itself relative to the object, and then finally apply appropriate grip that are prerecorded using leap-motion sensor.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133625484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00027
M. Hari, K. Rakesh, R. Divya, Lintu Rajan, C. K. Subash, S. Varghese
Technology advancements in piezoelectric materials have significantly impacted the design of wearable and flexible electromechanical sensors. Although many inorganic and ceramic materials have piezoelectric effects and high piezoelectric coefficients, their characteristics, such as high hardness and low tenacity, render them unsuitable for flexible device design. Polyvinyli-dene fluoride (PVDF) and copolymers have been widely used in flexible device design because of their inherent flexibility, high sensitivity, high ductility, and a specific piezoelectric coefficient. The effects of nanosilica on the piezoelectric behavior of PVDF are investigated in this paper. The piezoelectric characteristics of PVDF nanocomposites could be greatly improved by including nanosilica into the material.
{"title":"Influence of Nanosilica in PVDF Thin Films for Sensing Applications","authors":"M. Hari, K. Rakesh, R. Divya, Lintu Rajan, C. K. Subash, S. Varghese","doi":"10.1109/iSES52644.2021.00027","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00027","url":null,"abstract":"Technology advancements in piezoelectric materials have significantly impacted the design of wearable and flexible electromechanical sensors. Although many inorganic and ceramic materials have piezoelectric effects and high piezoelectric coefficients, their characteristics, such as high hardness and low tenacity, render them unsuitable for flexible device design. Polyvinyli-dene fluoride (PVDF) and copolymers have been widely used in flexible device design because of their inherent flexibility, high sensitivity, high ductility, and a specific piezoelectric coefficient. The effects of nanosilica on the piezoelectric behavior of PVDF are investigated in this paper. The piezoelectric characteristics of PVDF nanocomposites could be greatly improved by including nanosilica into the material.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114998497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00089
Shilpa Gottam, S. Nanda, R. Maddila
Recent trends in research reveal evolution of hybrid machine learning models based on deep neural networks and nature inspired computing. In this paper, a combined model of convolutional neural network (CNN) and long-short term memory (LSTM) termed as CNN-LSTM network has been used for modelling. A popular swarm intelligence technique Grey Wolf optimizer (GWO) is used to compute the meaningful and best hyper-parameters of the CNN-LSTM network. The GWO algorithm has become popular due to its ability of fast convergence and determining accurate solutions among other meta-heuristic techniques. The proposed hybrid model has been suitably applied to predict the household power consumption. Simulation results reveal the superior accuracy achieved by the proposed model compared to the same CNN-LSTM model trained with particle swarm optimization, artificial bee colony and social spider optimization.
{"title":"A CNN-LSTM Model Trained with Grey Wolf Optimizer for Prediction of Household Power Consumption","authors":"Shilpa Gottam, S. Nanda, R. Maddila","doi":"10.1109/iSES52644.2021.00089","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00089","url":null,"abstract":"Recent trends in research reveal evolution of hybrid machine learning models based on deep neural networks and nature inspired computing. In this paper, a combined model of convolutional neural network (CNN) and long-short term memory (LSTM) termed as CNN-LSTM network has been used for modelling. A popular swarm intelligence technique Grey Wolf optimizer (GWO) is used to compute the meaningful and best hyper-parameters of the CNN-LSTM network. The GWO algorithm has become popular due to its ability of fast convergence and determining accurate solutions among other meta-heuristic techniques. The proposed hybrid model has been suitably applied to predict the household power consumption. Simulation results reveal the superior accuracy achieved by the proposed model compared to the same CNN-LSTM model trained with particle swarm optimization, artificial bee colony and social spider optimization.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116928330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00024
Anirban Bhattacharjee, H. Rahaman
In the last few years, tremendous improvement in the field of quantum computing has been witnessed. Although quantum technologies such as ion-trap, NMR, quantum dots have emerged as the promising platforms for implementing quantum circuits but these technologies have faced several design issues. One such important design problem is the nearest neighbor condition, which requires the qubits to interact with adjacent neighbors. This problem can be addressed by adding SWAP gates in the circuit. By doing so, the overhead in the circuit increases thus NN designs with minimum number of SWAP gates need to be developed. Focusing on this, here, in this work, we introduce a heuristic design method for efficient NN realization of quantum circuits in 2D architecture. Our NN transformation process is carried out in two phases, where initially in the first phase, the input circuit is mapped to 2D configuration using a qubit placement strategy and then in the second phase NN designs are obtained through SWAP gate insertion. At the end, the design algorithm has been evaluated over a large set of benchmark functions and the results are compared with some of the existing works. From this comparison, it is seen that our proposed method performs better than the reported works.
{"title":"An Efficient 2D Mapping of Quantum Circuits to Nearest Neighbor Designs","authors":"Anirban Bhattacharjee, H. Rahaman","doi":"10.1109/iSES52644.2021.00024","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00024","url":null,"abstract":"In the last few years, tremendous improvement in the field of quantum computing has been witnessed. Although quantum technologies such as ion-trap, NMR, quantum dots have emerged as the promising platforms for implementing quantum circuits but these technologies have faced several design issues. One such important design problem is the nearest neighbor condition, which requires the qubits to interact with adjacent neighbors. This problem can be addressed by adding SWAP gates in the circuit. By doing so, the overhead in the circuit increases thus NN designs with minimum number of SWAP gates need to be developed. Focusing on this, here, in this work, we introduce a heuristic design method for efficient NN realization of quantum circuits in 2D architecture. Our NN transformation process is carried out in two phases, where initially in the first phase, the input circuit is mapped to 2D configuration using a qubit placement strategy and then in the second phase NN designs are obtained through SWAP gate insertion. At the end, the design algorithm has been evaluated over a large set of benchmark functions and the results are compared with some of the existing works. From this comparison, it is seen that our proposed method performs better than the reported works.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129721379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00101
Giriraj Sharma, A. Joshi, S. Mohanty
With the advancement of ICT, the Electrical vehicles (EVs) are connected to the smart grid and this type of network known as Vehicle to Grid (V2G). During the Energy trading process, EV consumers also receives an economic benefit where they buy energy at low cost during slack hours and sell same to grid during higher traffic. However, the V2G network faces various security challenges like hardware security, integrity, identity preservation, mutual authentication, etc. Since EVs and CSs (charging stations) are generally unmanned hence physical security is also an important concern. In this paper, we proposed a secure, lightweight, and hardware-based key agreement scheme using Physical Unclonable Function (PUF). The proposed scheme uses the PUF concept to perform mutual authentication (MA) among EV, CS, and the GS. The formal security analysis has been performed using AVISPA tool. Further, the performance evaluation results show that overhead costs in communication and computation are less compared to the existing schemes.
{"title":"An Efficient Physically Unclonable Function based Authentication Scheme for V2G Network","authors":"Giriraj Sharma, A. Joshi, S. Mohanty","doi":"10.1109/iSES52644.2021.00101","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00101","url":null,"abstract":"With the advancement of ICT, the Electrical vehicles (EVs) are connected to the smart grid and this type of network known as Vehicle to Grid (V2G). During the Energy trading process, EV consumers also receives an economic benefit where they buy energy at low cost during slack hours and sell same to grid during higher traffic. However, the V2G network faces various security challenges like hardware security, integrity, identity preservation, mutual authentication, etc. Since EVs and CSs (charging stations) are generally unmanned hence physical security is also an important concern. In this paper, we proposed a secure, lightweight, and hardware-based key agreement scheme using Physical Unclonable Function (PUF). The proposed scheme uses the PUF concept to perform mutual authentication (MA) among EV, CS, and the GS. The formal security analysis has been performed using AVISPA tool. Further, the performance evaluation results show that overhead costs in communication and computation are less compared to the existing schemes.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131709271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00069
S. Ghosh, V. Sahula, Lava Bhargava
Multi-core processors improve performance, but they can create unpredictability owing to shared resources such as caches interfering. Cache partitioning is used to alleviate the Worst-Case Execution Time (WCET) estimation by isolating the shared cache across each thread to reduce interference. It does, however, prohibit data from being transferred between parallel threads running on different cores. In this paper we present (SRCP) a cache replacement mechanism for partitioned caches that is aware of data being shared across threads, prevents shared data from being replicated across partitions and frequently used data from being evicted from caches. Our technique outperforms TA-DRRIP and EHC, which are existing state-of-the-art cache replacement algorithms, by 13.34% in cache hit-rate and 10.4% in performance over LRU (least recently used) cache replacement policy.
{"title":"Reuse-Aware Cache Partitioning Framework for Data-Sharing Multicore Systems","authors":"S. Ghosh, V. Sahula, Lava Bhargava","doi":"10.1109/iSES52644.2021.00069","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00069","url":null,"abstract":"Multi-core processors improve performance, but they can create unpredictability owing to shared resources such as caches interfering. Cache partitioning is used to alleviate the Worst-Case Execution Time (WCET) estimation by isolating the shared cache across each thread to reduce interference. It does, however, prohibit data from being transferred between parallel threads running on different cores. In this paper we present (SRCP) a cache replacement mechanism for partitioned caches that is aware of data being shared across threads, prevents shared data from being replicated across partitions and frequently used data from being evicted from caches. Our technique outperforms TA-DRRIP and EHC, which are existing state-of-the-art cache replacement algorithms, by 13.34% in cache hit-rate and 10.4% in performance over LRU (least recently used) cache replacement policy.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115143462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00044
Kattekola Naresh, S. Majumdar, Y. Sai, P. R. Sai
Nowadays, Artificial Neural Networks (ANNs) secured impressive results with multiple applications and approaches in various research fields, as well as image processing, face recognition and semantic segmentation. Here, the focus is to minimize the complexity of ANN hardware in keeping accuracy as a major concern. ANN is a subsystem that is approximate, in machine learning where it trains the neurons to get the relevant output according to the target value. By using this ANN, interfacing can be possible between approximate arithmetic circuits. 3:2, 4:2 compressors are designed with unique error positions, usually gives better power area and delay constraints in between 5 to 25%. The designed approximate ANN gains the design constraints in the range of 3 to 30%. The simulation results were done by using synopsys design compiler at 90nm Technology.
{"title":"Efficient Design of Artificial Neural Networks using Approximate Compressors and Multipliers","authors":"Kattekola Naresh, S. Majumdar, Y. Sai, P. R. Sai","doi":"10.1109/iSES52644.2021.00044","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00044","url":null,"abstract":"Nowadays, Artificial Neural Networks (ANNs) secured impressive results with multiple applications and approaches in various research fields, as well as image processing, face recognition and semantic segmentation. Here, the focus is to minimize the complexity of ANN hardware in keeping accuracy as a major concern. ANN is a subsystem that is approximate, in machine learning where it trains the neurons to get the relevant output according to the target value. By using this ANN, interfacing can be possible between approximate arithmetic circuits. 3:2, 4:2 compressors are designed with unique error positions, usually gives better power area and delay constraints in between 5 to 25%. The designed approximate ANN gains the design constraints in the range of 3 to 30%. The simulation results were done by using synopsys design compiler at 90nm Technology.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134379415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00014
Shivdeep, Sahibia Kaur Vohra, N. Goel, D. Das
There is a perpetual need of evolution in data converters to cater the demand of high speed and accurate data acquisition and processing. The trainable neural data converters can be trained using supervised learning techniques to produce precise data conversions. Such data converters are PVT immune and can be trained in real time using on-chip training signal generators. A trainable digital to analog converter needs accurate labeled analog signals as training signal. This paper proposes a CMOS-memristor hybrid training signal generator circuit and a memristive variable slope ramp generator circuit design. Proposed architecture is PVT immune and robust against mismatches and manufacturing imprecision in circuit component parameters. Proposed design is scalable to produce training signal for N-bit digital to analog converters. Proposed work is implemented and validated in standard CMOS 180nm technology node with SPICE model for the memristor.
{"title":"A Robust Training Signal Generator for Trainable Memristive Digital to Analog Converter","authors":"Shivdeep, Sahibia Kaur Vohra, N. Goel, D. Das","doi":"10.1109/iSES52644.2021.00014","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00014","url":null,"abstract":"There is a perpetual need of evolution in data converters to cater the demand of high speed and accurate data acquisition and processing. The trainable neural data converters can be trained using supervised learning techniques to produce precise data conversions. Such data converters are PVT immune and can be trained in real time using on-chip training signal generators. A trainable digital to analog converter needs accurate labeled analog signals as training signal. This paper proposes a CMOS-memristor hybrid training signal generator circuit and a memristive variable slope ramp generator circuit design. Proposed architecture is PVT immune and robust against mismatches and manufacturing imprecision in circuit component parameters. Proposed design is scalable to produce training signal for N-bit digital to analog converters. Proposed work is implemented and validated in standard CMOS 180nm technology node with SPICE model for the memristor.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115537425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00062
R. Kumawat, Aman Dayal, Seshadhari Srinivasan
A self-controlled automatic wheelchair extremely important for physically challenged people. In this paper, we have presented, the design and implementation details of three schemes for a self-controlled wheelchair and discussed their comparative analysis. These designs include: a) Joystick Controlled Wheelchair b) Gesture Controlled Wheelchair and c) Voice Controlled Wheelchair. The first scheme presents a prototype of movement of the wheelchair using a joystick. The second scheme uses a pseudo glove carrying an accelerometer as an input to the wheelchair. The last scheme uses a HC-05 Bluetooth Module and Bluetooth Controller mobile application for the working of the wheelchair. All these schemes are implemented using an Arduino UNO microcontroller board. Arduino Integrated Development Environment (IDE) is used for developing the necessary software. The UPPAAL software is used for verification of the design. Various test cases are applied to the prototype models under varying environmental conditions. Based on these test results, a combination of voice controlled as well as gesture controlled wheelchair is proposed and designed for obtaining higher efficiency. Besides wheelchairs, these prototype designs can be extended for several other application areas.
{"title":"Implementation of Self-Controlled Wheelchairs based on Joystick, Gesture Motion and Voice Recognition","authors":"R. Kumawat, Aman Dayal, Seshadhari Srinivasan","doi":"10.1109/iSES52644.2021.00062","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00062","url":null,"abstract":"A self-controlled automatic wheelchair extremely important for physically challenged people. In this paper, we have presented, the design and implementation details of three schemes for a self-controlled wheelchair and discussed their comparative analysis. These designs include: a) Joystick Controlled Wheelchair b) Gesture Controlled Wheelchair and c) Voice Controlled Wheelchair. The first scheme presents a prototype of movement of the wheelchair using a joystick. The second scheme uses a pseudo glove carrying an accelerometer as an input to the wheelchair. The last scheme uses a HC-05 Bluetooth Module and Bluetooth Controller mobile application for the working of the wheelchair. All these schemes are implemented using an Arduino UNO microcontroller board. Arduino Integrated Development Environment (IDE) is used for developing the necessary software. The UPPAAL software is used for verification of the design. Various test cases are applied to the prototype models under varying environmental conditions. Based on these test results, a combination of voice controlled as well as gesture controlled wheelchair is proposed and designed for obtaining higher efficiency. Besides wheelchairs, these prototype designs can be extended for several other application areas.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114601444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00043
Shubham Kumar, D. Das
Neuromorphic computing attempts to mimic the neural architecture of human brain by delivering a non vonNeumann hardware which can run even the most complex artificial intelligence algorithms at extremely fast computational speeds at power requirement as low in order as few tens of watts just like the human brain does. Since the brain is a complex mesh of millions of neurons communicating via the synapses and spiking signals in between them, there is a requirement of a circuit based memory element which can play the role of these synapses in electronic circuits. The memristors with there unique pinched hysteresis property have been proposed and modelled to act as these synapses. This paper introduces LTspice modelling of a simple artificial neural network with memristive synapses and training it for the universal gates-NOR and NAND by providing a mechanism for interpreting the compressed binary data generated by parametric LTspice simulations. The results show potential for application in many other crucial neuromorphic simulations and their numeric interpretation using the tool developed for Co-simulation of LTspice with the open source programming language, Python.
{"title":"Python-LTspice Co-Simulation to Train Neural Networks with Memristive Synapses to Learn Logic Gate Operations","authors":"Shubham Kumar, D. Das","doi":"10.1109/iSES52644.2021.00043","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00043","url":null,"abstract":"Neuromorphic computing attempts to mimic the neural architecture of human brain by delivering a non vonNeumann hardware which can run even the most complex artificial intelligence algorithms at extremely fast computational speeds at power requirement as low in order as few tens of watts just like the human brain does. Since the brain is a complex mesh of millions of neurons communicating via the synapses and spiking signals in between them, there is a requirement of a circuit based memory element which can play the role of these synapses in electronic circuits. The memristors with there unique pinched hysteresis property have been proposed and modelled to act as these synapses. This paper introduces LTspice modelling of a simple artificial neural network with memristive synapses and training it for the universal gates-NOR and NAND by providing a mechanism for interpreting the compressed binary data generated by parametric LTspice simulations. The results show potential for application in many other crucial neuromorphic simulations and their numeric interpretation using the tool developed for Co-simulation of LTspice with the open source programming language, Python.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115310633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：