Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00102
R. Prajapat, Rajesh Bhadada, Giriraj Sharma
Global System for Mobile (GSM) is still widely used cellular standard providing many services like Voice, SMS & Data Service with mobility. To secure information in the GSM cellular network, security is implemented at two levels i.e. initially to authorize the valid users for every location update and then during call, encryption is applied over the information being transmitted on GSM channel to protect from being intercepted and decoded by unauthorized persons. This protection is achieved by converting the original message into an encoded form (cipher form) that appears to be a random stream of symbols. Under “Challenge-Response” mechanism, A3 and A8 algorithms are used to generate triplet (RAND, SRES & Kc) for authentication of any user at GSM network. But the actual information is encrypted using A5 algorithm to generate cipher stream for better protection from interception. This A5 stream cipher has three versions: A5/1, A5/2 and A5/3. A5/1 works on Liner Feedback Shift Registers (LFSRs) with irregular clocking and generates pseudo random binary stream. These three versions of A5 algorithm are being used for encryption of information over GSM since the launching of GSM services and have been cryptographically analyzed by Reverse-Engineering. With passage of time, many hackers & crackers are becoming able to break this encryption identifying some weaknesses of these algorithms and can decrypt the original information. These stream ciphers are facing some weaknesses like poor Liner Complexity (LC) & clocking mechanism (Majority Rule), short clocking period, weak choice of clocking taps and collision problem. Because of such weaknesses, these stream ciphers can be decrypted by intruders. In this papers an attempt has been made to reduce these weaknesses and enhance the security by introducing non-linear combinational generator (NLFSRs), reuse of 32 bits SRES generated by A3 algorithm and finally combining the output stream with last 32 bits of CGI. The randomness analysis of proposed stream cipher is carried out by NIST Statistical Test Suite and it is confirmed by comparison of the randomness parameters results that the randomness of bit-stream produced by the proposed stream cipher has improved significantly hence the enhanced security can be achieved.
{"title":"Implementation of Enhanced A5/1 Stream Cipher and its Randomness Analysis by NIST Test Suite","authors":"R. Prajapat, Rajesh Bhadada, Giriraj Sharma","doi":"10.1109/iSES52644.2021.00102","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00102","url":null,"abstract":"Global System for Mobile (GSM) is still widely used cellular standard providing many services like Voice, SMS & Data Service with mobility. To secure information in the GSM cellular network, security is implemented at two levels i.e. initially to authorize the valid users for every location update and then during call, encryption is applied over the information being transmitted on GSM channel to protect from being intercepted and decoded by unauthorized persons. This protection is achieved by converting the original message into an encoded form (cipher form) that appears to be a random stream of symbols. Under “Challenge-Response” mechanism, A3 and A8 algorithms are used to generate triplet (RAND, SRES & Kc) for authentication of any user at GSM network. But the actual information is encrypted using A5 algorithm to generate cipher stream for better protection from interception. This A5 stream cipher has three versions: A5/1, A5/2 and A5/3. A5/1 works on Liner Feedback Shift Registers (LFSRs) with irregular clocking and generates pseudo random binary stream. These three versions of A5 algorithm are being used for encryption of information over GSM since the launching of GSM services and have been cryptographically analyzed by Reverse-Engineering. With passage of time, many hackers & crackers are becoming able to break this encryption identifying some weaknesses of these algorithms and can decrypt the original information. These stream ciphers are facing some weaknesses like poor Liner Complexity (LC) & clocking mechanism (Majority Rule), short clocking period, weak choice of clocking taps and collision problem. Because of such weaknesses, these stream ciphers can be decrypted by intruders. In this papers an attempt has been made to reduce these weaknesses and enhance the security by introducing non-linear combinational generator (NLFSRs), reuse of 32 bits SRES generated by A3 algorithm and finally combining the output stream with last 32 bits of CGI. The randomness analysis of proposed stream cipher is carried out by NIST Statistical Test Suite and it is confirmed by comparison of the randomness parameters results that the randomness of bit-stream produced by the proposed stream cipher has improved significantly hence the enhanced security can be achieved.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126003251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/ises52644.2021.00003
{"title":"[Copyright notice]","authors":"","doi":"10.1109/ises52644.2021.00003","DOIUrl":"https://doi.org/10.1109/ises52644.2021.00003","url":null,"abstract":"","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126878196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00070
G. Saxena, Chitrakant Sahu, A. Joshi
Bacterial growth in foods can be prevented by applying various controls to the food product, including adjusting the acidity of the food. Research has indicated that a pH level of 4.6 or lower will be effective to prevent most bacterial growth. The pH detection system has been proposed in order to verify pH level through experimental calibrated pH meter(potentiometric). pH is a measure of acidity or alkalinity of a solution, the pH scale ranges from 0 to 14. The paper presents development of signal conditioning circuit with integrated sensor using NodeMcu through IoT framework.
{"title":"Detection and transmission of pH from food substances using IoT","authors":"G. Saxena, Chitrakant Sahu, A. Joshi","doi":"10.1109/iSES52644.2021.00070","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00070","url":null,"abstract":"Bacterial growth in foods can be prevented by applying various controls to the food product, including adjusting the acidity of the food. Research has indicated that a pH level of 4.6 or lower will be effective to prevent most bacterial growth. The pH detection system has been proposed in order to verify pH level through experimental calibrated pH meter(potentiometric). pH is a measure of acidity or alkalinity of a solution, the pH scale ranges from 0 to 14. The paper presents development of signal conditioning circuit with integrated sensor using NodeMcu through IoT framework.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130672248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00087
Sarfraz Hussain, Sujay Deb
As the human population is growing drastically fast, the need for medical attention is also increasing proportionally. New methods and ways to reduce visits to a doctor or hospital is becoming a priority. Healthcare is an important aspect of one’s daily life. With the evolving technology and advancement in science, smart healthcare applications are being implemented. Big data and IoT brought the smartness in healthcare system. The data can be accessed by anyone, anytime and from anywhere, which gives a flexibility to use the online platform for multiple users at the same time. It is faster, cheaper, and easily accessible. Although, the applications are cost effective and impressive to a certain extent, a major issue arises in the form of security of data which is being shared online. Fraudsters make use of the patient or doctor details to claim insurance and buy drugs. This paper presents a study on the development of smart healthcare applications and discuses the security measures to protect user’s ID and their details.
{"title":"A Study on Securing Data in Smart Healthcare Applications","authors":"Sarfraz Hussain, Sujay Deb","doi":"10.1109/iSES52644.2021.00087","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00087","url":null,"abstract":"As the human population is growing drastically fast, the need for medical attention is also increasing proportionally. New methods and ways to reduce visits to a doctor or hospital is becoming a priority. Healthcare is an important aspect of one’s daily life. With the evolving technology and advancement in science, smart healthcare applications are being implemented. Big data and IoT brought the smartness in healthcare system. The data can be accessed by anyone, anytime and from anywhere, which gives a flexibility to use the online platform for multiple users at the same time. It is faster, cheaper, and easily accessible. Although, the applications are cost effective and impressive to a certain extent, a major issue arises in the form of security of data which is being shared online. Fraudsters make use of the patient or doctor details to claim insurance and buy drugs. This paper presents a study on the development of smart healthcare applications and discuses the security measures to protect user’s ID and their details.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130993635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00090
Alakananda Mitra, S. Mohanty, P. Corcoran, E. Kougianos
Digital ID is the gateway of “Smart City” for “Smart Citizens”. It gives citizen access to all other stakeholders of smart cities like smart healthcare, smart transport, smart finance, smart energy, etc. effectively and easily. In this paper, we propose a biometric based digital ID which is implemented in IoT environment. It is a secured and robust system against deepfake attacks. A convolutional neural network (CNN) based feature extraction method has been employed to defeat deepfake attacks. The dlib face detector has been used in detecting face landmark points and in calculating distances in the iris and nose region to obtain unique facial features. A bio-key is generated from the combination of features from facial landmarks and various facial distances along with the username. An encoded key is stored in a cloud database during the registration process of the user. For accessing any facilities in a smart city, the user needs to be authenticated. The authentication process is performed at the edge. Small changes in an image due to unconstrained settings are corrected using the Reed Solomon algorithm. Once authenticated at a particular smart facility, the user is now eligible to use that facility.
{"title":"iFace: A Deepfake Resilient Digital Identification Framework for Smart Cities","authors":"Alakananda Mitra, S. Mohanty, P. Corcoran, E. Kougianos","doi":"10.1109/iSES52644.2021.00090","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00090","url":null,"abstract":"Digital ID is the gateway of “Smart City” for “Smart Citizens”. It gives citizen access to all other stakeholders of smart cities like smart healthcare, smart transport, smart finance, smart energy, etc. effectively and easily. In this paper, we propose a biometric based digital ID which is implemented in IoT environment. It is a secured and robust system against deepfake attacks. A convolutional neural network (CNN) based feature extraction method has been employed to defeat deepfake attacks. The dlib face detector has been used in detecting face landmark points and in calculating distances in the iris and nose region to obtain unique facial features. A bio-key is generated from the combination of features from facial landmarks and various facial distances along with the username. An encoded key is stored in a cloud database during the registration process of the user. For accessing any facilities in a smart city, the user needs to be authenticated. The authentication process is performed at the edge. Small changes in an image due to unconstrained settings are corrected using the Reed Solomon algorithm. Once authenticated at a particular smart facility, the user is now eligible to use that facility.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129530594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00030
K. V. S. Kumar, Venkata Reddy Kopparthi, S. L. Sabat, K. ThulasiramVarma., Rangababu Peesapati
This work presents a system on chip (SoC) implementation of floating-point matrix inversion using the modified Gram-Schmidt based QR decomposition technique. The SoC realization is carried out using High-Level Synthesis on PYNQZl board. The latency and resource utilization of modified Gram-Schmidt is compared with classical Gram-Schmidt QR decomposition for different bus interface techniques by realizing a 100×100 matrix decomposition on a Xilinx PYNQZl board. Further, the designed QR hardware IP is used for realizing the floating-point matrix inversion of size 25×25. The accuracy, hardware execution time, and resource utilization are evaluated and compared with Givens rotation-based inverse. The implementation results on PYNQ-ZI demonstrate the successful realization of resource-efficient matrix inversion on Field Programmable Gate Array (FPGA).
{"title":"System on chip implementation of floating point matrix inversion using modified Gram-Schmidt based QR decomposition on PYNQ FPGA","authors":"K. V. S. Kumar, Venkata Reddy Kopparthi, S. L. Sabat, K. ThulasiramVarma., Rangababu Peesapati","doi":"10.1109/iSES52644.2021.00030","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00030","url":null,"abstract":"This work presents a system on chip (SoC) implementation of floating-point matrix inversion using the modified Gram-Schmidt based QR decomposition technique. The SoC realization is carried out using High-Level Synthesis on PYNQZl board. The latency and resource utilization of modified Gram-Schmidt is compared with classical Gram-Schmidt QR decomposition for different bus interface techniques by realizing a 100×100 matrix decomposition on a Xilinx PYNQZl board. Further, the designed QR hardware IP is used for realizing the floating-point matrix inversion of size 25×25. The accuracy, hardware execution time, and resource utilization are evaluated and compared with Givens rotation-based inverse. The implementation results on PYNQ-ZI demonstrate the successful realization of resource-efficient matrix inversion on Field Programmable Gate Array (FPGA).","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132066471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00050
S. Sankaran, Vamshi Sunku Mohan, A. Purushothaman
Hardware Trojans are modifications made by malicious insiders or third party providers during the design or fabrication phase of the IC (Integrated Circuits) design cycle in a covert manner. These cause catastrophic consequences ranging from manipulating the functionality of individual blocks to disabling the entire chip. Thus, a need for detecting trojans becomes necessary. In this work, we propose a deep learning based approach for detecting trojans in IC chips. In particular, we insert trojans at the circuit-level and generate data by measuring power during normal operation and under attack. Further, we develop deep learning models using Neural networks and Auto-encoders to analyze datasets for outlier detection by profiling the normal behavior and leveraging them to detect anomalies in power consumption. Our approach is generic and non-invasive in that it can be applied to any block without any modifications to the design. Evaluation of the proposed approach shows an accuracy ranging from 92.23% to 99.33% in detecting trojans.
{"title":"Deep Learning Based Approach for Hardware Trojan Detection","authors":"S. Sankaran, Vamshi Sunku Mohan, A. Purushothaman","doi":"10.1109/iSES52644.2021.00050","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00050","url":null,"abstract":"Hardware Trojans are modifications made by malicious insiders or third party providers during the design or fabrication phase of the IC (Integrated Circuits) design cycle in a covert manner. These cause catastrophic consequences ranging from manipulating the functionality of individual blocks to disabling the entire chip. Thus, a need for detecting trojans becomes necessary. In this work, we propose a deep learning based approach for detecting trojans in IC chips. In particular, we insert trojans at the circuit-level and generate data by measuring power during normal operation and under attack. Further, we develop deep learning models using Neural networks and Auto-encoders to analyze datasets for outlier detection by profiling the normal behavior and leveraging them to detect anomalies in power consumption. Our approach is generic and non-invasive in that it can be applied to any block without any modifications to the design. Evaluation of the proposed approach shows an accuracy ranging from 92.23% to 99.33% in detecting trojans.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133256530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00029
Sahith Guturu, Anil Kumar Uppugunduru, S. Thota, Syed Ershad Ahmed
Approximate Computing is a paradigm shift to meet the future demands of compute-intensive tasks such as media processing, data mining, and recognition. These applications can tolerate errors up to a specific limit. In such applications, addition is one unit that is power-hungry by approximating the adder savings in area, power, and delay can be achieved. This paper presents a technique of approximating the least significant portion in an adder while improvement in accuracy is achieved using OR-based logic. This results in a reduction of area and power without significant compromise in accuracy. Based on the approximation region, we propose three designs with a tradeoff in computation complexity and accuracy. The results prove the efficacy of the proposed designs and an improvement up to 51.39%, improvement in power w.r.t existing designs.
{"title":"Power-Efficient MLOA for error resilient applications","authors":"Sahith Guturu, Anil Kumar Uppugunduru, S. Thota, Syed Ershad Ahmed","doi":"10.1109/iSES52644.2021.00029","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00029","url":null,"abstract":"Approximate Computing is a paradigm shift to meet the future demands of compute-intensive tasks such as media processing, data mining, and recognition. These applications can tolerate errors up to a specific limit. In such applications, addition is one unit that is power-hungry by approximating the adder savings in area, power, and delay can be achieved. This paper presents a technique of approximating the least significant portion in an adder while improvement in accuracy is achieved using OR-based logic. This results in a reduction of area and power without significant compromise in accuracy. Based on the approximation region, we propose three designs with a tradeoff in computation complexity and accuracy. The results prove the efficacy of the proposed designs and an improvement up to 51.39%, improvement in power w.r.t existing designs.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124214674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00097
V. P. Yanambaka, S. Mohanty, E. Kougianos, B. K. Baniya, Bibhudutta Rout
This paper proposes a new controlled Physical Unclonable Function (PUF), Veda-PUF, which uses an algorithm for pre-processing and post-processing the input and output of PUF to increase the security of the keys generated in Internet-of-Things (IoT) devices. The key size of the PUF can be increased using the proposed protocol without compromising the integrity of the keys generated. The uniqueness of the generated keys was 50 % and the reliability of the keys generated is 99.9 % which are close to the ideal values. The proposed control algorithm also increases the uniqueness and reliability of the PUF keys after processing. This increases the number of PUF keys that can be used for various applications.
{"title":"Veda-PUF: A PUF based on Vedic Principles for Robust Lightweight Security for IoT","authors":"V. P. Yanambaka, S. Mohanty, E. Kougianos, B. K. Baniya, Bibhudutta Rout","doi":"10.1109/iSES52644.2021.00097","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00097","url":null,"abstract":"This paper proposes a new controlled Physical Unclonable Function (PUF), Veda-PUF, which uses an algorithm for pre-processing and post-processing the input and output of PUF to increase the security of the keys generated in Internet-of-Things (IoT) devices. The key size of the PUF can be increased using the proposed protocol without compromising the integrity of the keys generated. The uniqueness of the generated keys was 50 % and the reliability of the keys generated is 99.9 % which are close to the ideal values. The proposed control algorithm also increases the uniqueness and reliability of the PUF keys after processing. This increases the number of PUF keys that can be used for various applications.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116481789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-01DOI: 10.1109/iSES52644.2021.00015
Preethi, M. Kabadi, K. S. Kumar, K. Mahapatra
Sorting is a very important task which is widely used in several applications like signal processing and database management. The importance of sorting has increased significantly in modern data center applications serving the applications of Cloud computing and Internet of Things. Sorting which is generally implemented in software on CPU or GPU, which takes several cycles to finish the sorting process. The further improvement in performance in sorting is possible through hardware implementation either in FPGA or ASIC. The performance improvement and reducing the power consumption are the dominant concerns. The conventional sorting techniques like Bubble sort, bitonic sort and odd-even sort are found suitable for hardware implementation in the research literature. There are several endeavors from researchers to make these sorting techniques more modular and low power, which is required to design large scale sorting for data center-based applications. In this paper, we investigate application of generic and structured low power technique like clock gating in designing the low power sorters. The bubble sort, bitonic sort and odd-even sorting techniques are redesigned to make them low power using clock gating technique. The implementation results show that, the clock gating reduces the dynamic power consumption on sorters by 47.5% without much impact on the performance. The power reduction results obtained are comparable with state-of-the-art low power sorters which are complex in design. The proposed sorters are implemented and results are presented for Saed90nm standard cell libraries.
{"title":"Low Power Sorters Using Clock Gating","authors":"Preethi, M. Kabadi, K. S. Kumar, K. Mahapatra","doi":"10.1109/iSES52644.2021.00015","DOIUrl":"https://doi.org/10.1109/iSES52644.2021.00015","url":null,"abstract":"Sorting is a very important task which is widely used in several applications like signal processing and database management. The importance of sorting has increased significantly in modern data center applications serving the applications of Cloud computing and Internet of Things. Sorting which is generally implemented in software on CPU or GPU, which takes several cycles to finish the sorting process. The further improvement in performance in sorting is possible through hardware implementation either in FPGA or ASIC. The performance improvement and reducing the power consumption are the dominant concerns. The conventional sorting techniques like Bubble sort, bitonic sort and odd-even sort are found suitable for hardware implementation in the research literature. There are several endeavors from researchers to make these sorting techniques more modular and low power, which is required to design large scale sorting for data center-based applications. In this paper, we investigate application of generic and structured low power technique like clock gating in designing the low power sorters. The bubble sort, bitonic sort and odd-even sorting techniques are redesigned to make them low power using clock gating technique. The implementation results show that, the clock gating reduces the dynamic power consumption on sorters by 47.5% without much impact on the performance. The power reduction results obtained are comparable with state-of-the-art low power sorters which are complex in design. The proposed sorters are implemented and results are presented for Saed90nm standard cell libraries.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116527348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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