Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783405
C. Pandey, Avtar Singh, S. Chaudhury
In this brief, the reliability of SOI-TFET with dielectric pocket (DP SOI-TFET) has been investigated in the presence of fixed trap charges at the interface between dielectric pocket (DP) and drain region. During numerical simulation, both types of trap charges like donor (i.e. positive) and acceptor (i.e. negative) have been considered to analyse the impact on the performance of SOI-TFET having DP in drain region used for reduction of ambipolar conduction. We have compared the device performances such as ambipolar conduction, and OFF-state current of conventional SOI-TFET with both low and high- $pmb{k}$ DP SOI-TFET in the presence of interface trap charges (ITCs). It has been found that SOI-TFET is more immune to interface trap charges when high- $pmb{k}$ material is used as DP compared to low- $pmb{k}$. Since, high- $pmb{k}$ provides even more reduction in ambipolar conduction as compared to low- $pmb{k}$, it can be preferred to be used a dielectric pocket in SOI-TFET.
{"title":"Analysis of Interface Trap Charges on Dielectric Pocket SOI-TFET","authors":"C. Pandey, Avtar Singh, S. Chaudhury","doi":"10.1109/DEVIC.2019.8783405","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783405","url":null,"abstract":"In this brief, the reliability of SOI-TFET with dielectric pocket (DP SOI-TFET) has been investigated in the presence of fixed trap charges at the interface between dielectric pocket (DP) and drain region. During numerical simulation, both types of trap charges like donor (i.e. positive) and acceptor (i.e. negative) have been considered to analyse the impact on the performance of SOI-TFET having DP in drain region used for reduction of ambipolar conduction. We have compared the device performances such as ambipolar conduction, and OFF-state current of conventional SOI-TFET with both low and high- $pmb{k}$ DP SOI-TFET in the presence of interface trap charges (ITCs). It has been found that SOI-TFET is more immune to interface trap charges when high- $pmb{k}$ material is used as DP compared to low- $pmb{k}$. Since, high- $pmb{k}$ provides even more reduction in ambipolar conduction as compared to low- $pmb{k}$, it can be preferred to be used a dielectric pocket in SOI-TFET.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133501063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783735
S. Chakraborty, A. Acharyya, A. Biswas, Jayanta Roy
Noise analysis of 1.0 THz Wz-GaN IMPATT source has been carried out by the authors. A two-dimensional avalanche noise model for IMPATT diodes developed by the authors has been used in the present paper to study the avalanche noise characteristics of the said source. Results reveal that the mean-square noise voltage per unit bandwidth (i.e. noise spectral density) of the source lies in the order of 10–16 $mathrm{V}^{2} mathrm{s}$ and noise measure remains within the range of 7.3440 – 5.8755 dB due to the variation of bias current within the range of 78.54 – 98.17 mA for a fictitious value of zero series resistance. However, around 3 – 7% increase in noise measure has been obtained by considering earlier calculated series resistance values ranging from $1.5779 - 1.7879 Omega$.
{"title":"Noise Analysis of 1.0 THz GaN IMPATT Source","authors":"S. Chakraborty, A. Acharyya, A. Biswas, Jayanta Roy","doi":"10.1109/DEVIC.2019.8783735","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783735","url":null,"abstract":"Noise analysis of 1.0 THz Wz-GaN IMPATT source has been carried out by the authors. A two-dimensional avalanche noise model for IMPATT diodes developed by the authors has been used in the present paper to study the avalanche noise characteristics of the said source. Results reveal that the mean-square noise voltage per unit bandwidth (i.e. noise spectral density) of the source lies in the order of 10–16 $mathrm{V}^{2} mathrm{s}$ and noise measure remains within the range of 7.3440 – 5.8755 dB due to the variation of bias current within the range of 78.54 – 98.17 mA for a fictitious value of zero series resistance. However, around 3 – 7% increase in noise measure has been obtained by considering earlier calculated series resistance values ranging from $1.5779 - 1.7879 Omega$.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133754760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783601
Shrabanti Das, S. Chatterjee
This paper has been written to compare the performances of LC Voltage Controlled Oscillator (VCO) at 2.5 GHz to see the effects of device performances with different technology node on the same while keeping the circuits identical. Accordingly, as a case study, three instances of LC-VCO have been designed in Cadence Spectre using GPDK 45nm, 90nm, and 180nm technology and three different power supply levels of 0.8 V, 1 V, and 1.2 V respectively. ObservedPhase Noise (PN) for 45nm, 90nm, and 180nm technology are −120.8 dBc/Hz, −124.64 dBc/Hz and −126.12 dBc/Hz @ 1MHz offset respectively. Output power, Figure of Merit (FOM) and $mathbf{K}_{mathbf{VCO}}$ also have been measured subsequently. The best possible FOM obtained are −181.7dB, −184.9dB and −186.2dB for 45nm, 90nm and 180nm technology node respectively.
{"title":"Performance Comparison of 2.5-GHz LC Voltage-Controlled Oscillator for Three Different Technology Nodes","authors":"Shrabanti Das, S. Chatterjee","doi":"10.1109/DEVIC.2019.8783601","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783601","url":null,"abstract":"This paper has been written to compare the performances of LC Voltage Controlled Oscillator (VCO) at 2.5 GHz to see the effects of device performances with different technology node on the same while keeping the circuits identical. Accordingly, as a case study, three instances of LC-VCO have been designed in Cadence Spectre using GPDK 45nm, 90nm, and 180nm technology and three different power supply levels of 0.8 V, 1 V, and 1.2 V respectively. ObservedPhase Noise (PN) for 45nm, 90nm, and 180nm technology are −120.8 dBc/Hz, −124.64 dBc/Hz and −126.12 dBc/Hz @ 1MHz offset respectively. Output power, Figure of Merit (FOM) and $mathbf{K}_{mathbf{VCO}}$ also have been measured subsequently. The best possible FOM obtained are −181.7dB, −184.9dB and −186.2dB for 45nm, 90nm and 180nm technology node respectively.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134546704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The most vital requirement in today's world is to overcome the different types of attacks. Human behavioral and physiological features in biometrics have the largest scope as a solution for security issues. However, the existing biometric systems such as faces, iris, palm, voice or fingerprints are highly complex in terms of time or space or both, and thus are not suitable in high security. So the design and implementation of finger-vein authentication method is proposed in this paper. This system is implemented using a combination of image processing and machine learning algorithm. Lacunae, fractal dimension and gabor filter are the algorithms used for feature extraction and the classification of the extracted feature is done using the Support Vector Machine. The accuracy of classification algorithm for One-Versus-One and One-Versus-All is 98.75 % and 97.92 % and the execution time is 0.168 Seconds and 0.187 Seconds respectively. At the end the comparative analysis between different classification algorithm and previous research work related to Finger Vein Authentication System using Machine learning is provided.
{"title":"Design and Implementation of Gabor Filter and SVM based Authentication system using Machine Learning","authors":"Shalini Singh, Indrajit Das, Md Golam Mohiuddin, Amogh Banerjee, Sonali Gupta","doi":"10.1109/DEVIC.2019.8783650","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783650","url":null,"abstract":"The most vital requirement in today's world is to overcome the different types of attacks. Human behavioral and physiological features in biometrics have the largest scope as a solution for security issues. However, the existing biometric systems such as faces, iris, palm, voice or fingerprints are highly complex in terms of time or space or both, and thus are not suitable in high security. So the design and implementation of finger-vein authentication method is proposed in this paper. This system is implemented using a combination of image processing and machine learning algorithm. Lacunae, fractal dimension and gabor filter are the algorithms used for feature extraction and the classification of the extracted feature is done using the Support Vector Machine. The accuracy of classification algorithm for One-Versus-One and One-Versus-All is 98.75 % and 97.92 % and the execution time is 0.168 Seconds and 0.187 Seconds respectively. At the end the comparative analysis between different classification algorithm and previous research work related to Finger Vein Authentication System using Machine learning is provided.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122243049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783724
S. Naval, Prasun Kumar Sinha, Nikhil Kumar Das, Ashutosh Anand, S. Kundu
Piezoelectric energy harvesters have high power density and are simpler to fabricate as compared to other low power energy harvesters. There are certain issues which need to be addressed while designing a piezoelectric energy harvester. These are the requirements of maintaining a high output voltage, low resonant frequency, small size and wide bandwidth of operation. Achieving a wide bandwidth is one of the most prominent issues. It is because most of the vibrations occur over a range of frequencies. So, the challenge is to design an energy harvester which generates high output voltage over a wide range of frequencies. In this paper, a Microelectromechanical system (MEMS) based multi-beam energy harvester has been proposed. This energy harvester has been designed using two single cantilever beams and the top electrodes of both the beams are connected by a metal layer. The peak output voltage of the proposed structure is 18 V at 142 Hz. The multi-beam structure generates an output voltage of more than or equal to 5 V for a bandwidth of 15 Hz which is 1.5 times wider as compared to that of a single beam energy harvester.
{"title":"Bandwidth Increment of Piezoelectric Energy Harvester using Multi-beam Structure","authors":"S. Naval, Prasun Kumar Sinha, Nikhil Kumar Das, Ashutosh Anand, S. Kundu","doi":"10.1109/DEVIC.2019.8783724","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783724","url":null,"abstract":"Piezoelectric energy harvesters have high power density and are simpler to fabricate as compared to other low power energy harvesters. There are certain issues which need to be addressed while designing a piezoelectric energy harvester. These are the requirements of maintaining a high output voltage, low resonant frequency, small size and wide bandwidth of operation. Achieving a wide bandwidth is one of the most prominent issues. It is because most of the vibrations occur over a range of frequencies. So, the challenge is to design an energy harvester which generates high output voltage over a wide range of frequencies. In this paper, a Microelectromechanical system (MEMS) based multi-beam energy harvester has been proposed. This energy harvester has been designed using two single cantilever beams and the top electrodes of both the beams are connected by a metal layer. The peak output voltage of the proposed structure is 18 V at 142 Hz. The multi-beam structure generates an output voltage of more than or equal to 5 V for a bandwidth of 15 Hz which is 1.5 times wider as compared to that of a single beam energy harvester.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116713971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783961
Hasanujjaman, Arnab Banerjee, U. Biswas, M. Naskar
Researchers have made several efforts towards reduction of Compression ratio and improvement of PSNR of an image compressing algorithm. However little attention has been given to reduce the time complexity of the same except for few hardware approaches. In this particular work, a mystical atomic image was created, through the process of splitting the main image into two different blocks. Atomic image was formed by strategically calculating the significant bits from even and odd portion of the original image in spatial domain. Furthermore the most popular methods were implemented on atomic image for getting a lower time complexity, as well as, increased compression ratio and acceptable PSNR. As a result of application of the proposed algorithm we obtained maximum PSNR of 30.12dB for Lena Image and maximum compression ratio of 25.96 for MRI image
{"title":"Fractal Image Compression of an Atomic Image using Quadtree Decomposition","authors":"Hasanujjaman, Arnab Banerjee, U. Biswas, M. Naskar","doi":"10.1109/DEVIC.2019.8783961","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783961","url":null,"abstract":"Researchers have made several efforts towards reduction of Compression ratio and improvement of PSNR of an image compressing algorithm. However little attention has been given to reduce the time complexity of the same except for few hardware approaches. In this particular work, a mystical atomic image was created, through the process of splitting the main image into two different blocks. Atomic image was formed by strategically calculating the significant bits from even and odd portion of the original image in spatial domain. Furthermore the most popular methods were implemented on atomic image for getting a lower time complexity, as well as, increased compression ratio and acceptable PSNR. As a result of application of the proposed algorithm we obtained maximum PSNR of 30.12dB for Lena Image and maximum compression ratio of 25.96 for MRI image","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115310793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783820
Sayan Hazra
Automated Teller Machine (ATM) is an electronic telecommunications device, which enables customers to perform banking without the need for direct interaction with bank staff. For this, every account holder must have a unique id card for the individual account having a unique pin. On the absence of this card, whatever be the adverse situation the use of this ATM service is not permitted. So, an Internet Of Things and Computer Vision based Smart ATM service is being proposed here, using Raspberrypi microcontroller based embedded system, where each person will be their own identity, where Fingerprint, Face, OTP verifications are key features for security, which in turn reduces the issue of fraud transactions, fraud ATM cards, hence security issue gets resolved.
{"title":"Smart ATM Service","authors":"Sayan Hazra","doi":"10.1109/DEVIC.2019.8783820","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783820","url":null,"abstract":"Automated Teller Machine (ATM) is an electronic telecommunications device, which enables customers to perform banking without the need for direct interaction with bank staff. For this, every account holder must have a unique id card for the individual account having a unique pin. On the absence of this card, whatever be the adverse situation the use of this ATM service is not permitted. So, an Internet Of Things and Computer Vision based Smart ATM service is being proposed here, using Raspberrypi microcontroller based embedded system, where each person will be their own identity, where Fingerprint, Face, OTP verifications are key features for security, which in turn reduces the issue of fraud transactions, fraud ATM cards, hence security issue gets resolved.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129891567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783626
Arifuddin Sohel, Aayesha al Khadir, Maliha Naaz, Amena Najeeb
This paper presents a 1.8V fourth-order 12.64 bits active-passive delta-sigma modulator. Passive integrators reduce power consumption which employs a switched capacitor circuit that operates from 1V to 1.8V supply voltage. The modulator is implemented in a $mathbf{0.18}mu mathbf{m}$ CMOS process and achieves 77.85 dB SNR within 500 Hz at a sampling frequency of 256 kHz and consumes $mathbf{204.8}mu mathbf{W}$ from a 1.8V supply. The Sigma-Delta modulator becomes the appropriate choice for high resolution as well as low frequency applications due to its highly linear property derived from a linear single-bit quantizer and oversampling technique.
{"title":"A 1.8V 204.8-$mu mathrm{W}$ 12-Bit Fourth Order Active Passive $SigmaDelta$ Modulator for Biomedical Applications","authors":"Arifuddin Sohel, Aayesha al Khadir, Maliha Naaz, Amena Najeeb","doi":"10.1109/DEVIC.2019.8783626","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783626","url":null,"abstract":"This paper presents a 1.8V fourth-order 12.64 bits active-passive delta-sigma modulator. Passive integrators reduce power consumption which employs a switched capacitor circuit that operates from 1V to 1.8V supply voltage. The modulator is implemented in a $mathbf{0.18}mu mathbf{m}$ CMOS process and achieves 77.85 dB SNR within 500 Hz at a sampling frequency of 256 kHz and consumes $mathbf{204.8}mu mathbf{W}$ from a 1.8V supply. The Sigma-Delta modulator becomes the appropriate choice for high resolution as well as low frequency applications due to its highly linear property derived from a linear single-bit quantizer and oversampling technique.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124616482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783882
Virendra Prasad Maurya, Prashant Kumar, S. Halder
Qualitative feature extraction from Electromyogram (EMG) signal has become necessary to assess the fitness of human being. Till date, various analysis tools have been employed to examine the EMG signal. Here the authors are endeavored to apply PSO-ANN based optimisation and two classification tools, namely KNN (nearest neighbor) and SVM (support vector machine) to extract features from EMG signal. EMG signal represents the signal generated by neuron from the brain, which is transmitted through the spinal cord into the body to which part is guided by the brain. The EMG signal is computed by Biopac MP45 Biomedical measurement device which is further divided into five-second segments for each activity. Unwanted EMG signal is regarded as noise and is filtered by an appropriate filter to improve the signal to noise ratio. Fourteen different time-domain and frequency domain features have been extracted for different hand movement (Weight lifting Up, Weight lifting Down, movement of Hand Gripper). Both hands are utilized for acquisition of EMG for hand grip movement. Classifier Model is used in classifying the optimised features and calculation of sensitivity, selectivity and precision of those features. From results it is evident that better accuracy is achieved for classifier KNN with respect to SVM.
{"title":"Optimisation and Classification of EMG signal using PSO-ANN","authors":"Virendra Prasad Maurya, Prashant Kumar, S. Halder","doi":"10.1109/DEVIC.2019.8783882","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783882","url":null,"abstract":"Qualitative feature extraction from Electromyogram (EMG) signal has become necessary to assess the fitness of human being. Till date, various analysis tools have been employed to examine the EMG signal. Here the authors are endeavored to apply PSO-ANN based optimisation and two classification tools, namely KNN (nearest neighbor) and SVM (support vector machine) to extract features from EMG signal. EMG signal represents the signal generated by neuron from the brain, which is transmitted through the spinal cord into the body to which part is guided by the brain. The EMG signal is computed by Biopac MP45 Biomedical measurement device which is further divided into five-second segments for each activity. Unwanted EMG signal is regarded as noise and is filtered by an appropriate filter to improve the signal to noise ratio. Fourteen different time-domain and frequency domain features have been extracted for different hand movement (Weight lifting Up, Weight lifting Down, movement of Hand Gripper). Both hands are utilized for acquisition of EMG for hand grip movement. Classifier Model is used in classifying the optimised features and calculation of sensitivity, selectivity and precision of those features. From results it is evident that better accuracy is achieved for classifier KNN with respect to SVM.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122013770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783800
Monu Bhagat, Deobrata Kumar, Dilip Kumar
Presently there is huge improvement in technologies. Lots of tools and techniques are available in the agriculture sector. Internet of Things plays very important role to improve productivity, efficiency, global market. It also reduces human intervention, cost and time which are major factors in agriculture. The Internet of Things (IoT) can be defined as a system which interrelate computing devices, objects, machines (like mechanical and digital), living beings. The IoT components are provided with unique identifiers and have the ability to transfer data over a network without requiring human-to-human or human-to-computer interaction. So, in order to increase productivity, IoT works in synergy with agriculture to get smart farming. Role of IoT, different tools, hardware and software used in smart farming is discussed in this paper.
{"title":"Role of Internet of Things (IoT) in Smart Farming: A Brief Survey","authors":"Monu Bhagat, Deobrata Kumar, Dilip Kumar","doi":"10.1109/DEVIC.2019.8783800","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783800","url":null,"abstract":"Presently there is huge improvement in technologies. Lots of tools and techniques are available in the agriculture sector. Internet of Things plays very important role to improve productivity, efficiency, global market. It also reduces human intervention, cost and time which are major factors in agriculture. The Internet of Things (IoT) can be defined as a system which interrelate computing devices, objects, machines (like mechanical and digital), living beings. The IoT components are provided with unique identifiers and have the ability to transfer data over a network without requiring human-to-human or human-to-computer interaction. So, in order to increase productivity, IoT works in synergy with agriculture to get smart farming. Role of IoT, different tools, hardware and software used in smart farming is discussed in this paper.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"32 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120926220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：