Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783355
I. Sil, Sagar Mukherjee, Kalyan Biswas
In this paper, thermal energy harvesters (TEH) or Thermoelectric Power Generators (TPG) are designed to harvest electrical energy from heat. These Thermoelectric Power Generators are compatible to CMOS and MEMS fabrication technology. Detailed analysis of various models of thermoelectric power generators using FEA software are studied to achieve enhanced performance. Comparison has been made for both CMOS and MEMS based TPGs. From the analysis, it is observed that MEMS based TPG model produces 43.76% more output voltage than CMOS based TPG when the temperature difference across hot and cold junction is 5K. Analysis reveals that 91.23% increase in output power is also achieved with MEMS based TPG model. The design and simulation results provides a very good overview of the power generation capability of the TEG, which may be useful in future design of improved thermal energy harvesters.
{"title":"Performance Comparison of CMOS and MEMS Based Thermal Energy Harvesters Using Finite Element Analysis","authors":"I. Sil, Sagar Mukherjee, Kalyan Biswas","doi":"10.1109/DEVIC.2019.8783355","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783355","url":null,"abstract":"In this paper, thermal energy harvesters (TEH) or Thermoelectric Power Generators (TPG) are designed to harvest electrical energy from heat. These Thermoelectric Power Generators are compatible to CMOS and MEMS fabrication technology. Detailed analysis of various models of thermoelectric power generators using FEA software are studied to achieve enhanced performance. Comparison has been made for both CMOS and MEMS based TPGs. From the analysis, it is observed that MEMS based TPG model produces 43.76% more output voltage than CMOS based TPG when the temperature difference across hot and cold junction is 5K. Analysis reveals that 91.23% increase in output power is also achieved with MEMS based TPG model. The design and simulation results provides a very good overview of the power generation capability of the TEG, which may be useful in future design of improved thermal energy harvesters.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130099032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783912
S. Biswas, Subhrapratim Nath, J. Sing, S. Sarkar
The rapid improvement of semiconductor technologies have led to a digital revolution globally which accelerated the rate of generation of data exponentially. When researchers are working hard to develop better compression algorithms, they came up with the idea of Nucleic Acid Memory (NAM). Various papers have been studied with their respective merits and demerits. This paper proposes a new scheme of encoding digital data into genetic nucleotide sequence which demonstrates the use of non-standard nucleotides and unnatural base pairs along with standard nucleotide bases. This combination aims in enhancing the efficiency of the encoding scheme much better than the predefined encoding model where the proposed scheme is compared with the existing encoding models.
{"title":"Storing Digital Data in Nucleic Acid Memory with Extended Genetic Alphabet","authors":"S. Biswas, Subhrapratim Nath, J. Sing, S. Sarkar","doi":"10.1109/DEVIC.2019.8783912","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783912","url":null,"abstract":"The rapid improvement of semiconductor technologies have led to a digital revolution globally which accelerated the rate of generation of data exponentially. When researchers are working hard to develop better compression algorithms, they came up with the idea of Nucleic Acid Memory (NAM). Various papers have been studied with their respective merits and demerits. This paper proposes a new scheme of encoding digital data into genetic nucleotide sequence which demonstrates the use of non-standard nucleotides and unnatural base pairs along with standard nucleotide bases. This combination aims in enhancing the efficiency of the encoding scheme much better than the predefined encoding model where the proposed scheme is compared with the existing encoding models.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125664487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783357
Avtar Singh, C. Pandey, S. Chaudhury, C. Sarkar
In this work we have studied the impact of variation of k dielectric constant on Silicon Nano Tube FET for low power and high speed applications. The Silicon Nano tubular structure offers better immunity towards short channel effects (SCE‘s) because of the better control of channel region due to the double gate all around. By cause of gate engineered structure high K value structures possess high value of electron velocity as compare to low k dielectric structure, which helps in improving the efficiency of carrier transport. In this work we have considered a Silicon Di-oxide(SiO2), Silicon Nitride(Si3N4), Hafnium Oxide(HfO2), Hafnium Silicate (HfSiO4), Tin oxide (SnO2) and Titanium Oxide (TO2) as a gate dielectric. It has been found that when the high k is replaced with SiO2 then the switching performance of the device is enhanced which makes it suitable for the SOC applications. From the analysis it has been found that HFO2 in SINTFET will be a superior alternative for future tubular FET devices
{"title":"Comparative Study of High K in Silicon Nano Tube FET for Switching Applications","authors":"Avtar Singh, C. Pandey, S. Chaudhury, C. Sarkar","doi":"10.1109/DEVIC.2019.8783357","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783357","url":null,"abstract":"In this work we have studied the impact of variation of k dielectric constant on Silicon Nano Tube FET for low power and high speed applications. The Silicon Nano tubular structure offers better immunity towards short channel effects (SCE‘s) because of the better control of channel region due to the double gate all around. By cause of gate engineered structure high K value structures possess high value of electron velocity as compare to low k dielectric structure, which helps in improving the efficiency of carrier transport. In this work we have considered a Silicon Di-oxide(SiO2), Silicon Nitride(Si3N4), Hafnium Oxide(HfO2), Hafnium Silicate (HfSiO4), Tin oxide (SnO2) and Titanium Oxide (TO2) as a gate dielectric. It has been found that when the high k is replaced with SiO2 then the switching performance of the device is enhanced which makes it suitable for the SOC applications. From the analysis it has been found that HFO2 in SINTFET will be a superior alternative for future tubular FET devices","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130550317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Volumetric changes in the microvascular tissue can be studied by using an optically obtained plethysmogram; a photoplethysmogram (PPG). This has gained much intrigue in the modelling of PPG signal using appropriate Synthesis techniques. The obtained circuit is used to reconstruct PPG waveform. The current work is a proposal of a method for the development of an equivalent circuit to simulate the PPG waveform. Based on the amount of energy, the PPG signal was segregated into ‘complex’ and ‘plain’ zones. To construct that, the individual waves were modelled using Fourier analysis method by MATLAB Curve Fitting Tool Box. Then, after generating the Fourier series coefficients from MATLAB, we obtained the sine and cosine components of the data along with the DC component. The sine and cosine components along with the DC component are added via an adder circuit, followed by an inverter, which generates the final PPG waveform using PSPICE. The building blocks of the Simulink model have been developed using sine and cos function generator blocks, and adder blocks thereby generating an appropriate waveform. The errors between the actual normal PPG waveform and reconstructed PPG waveform using PSPICE for one cycle have been computed, which results in deviations within acceptable ranges of deviation.
{"title":"Synthesis of PPG Waveform Using PSPICE and Simulink Model","authors":"Ankita Mukherjea, Parshati Chaudhury, Alvin Karkun, Soumalya Ghosh, Subhajit Bhowmick","doi":"10.1109/DEVIC.2019.8783684","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783684","url":null,"abstract":"Volumetric changes in the microvascular tissue can be studied by using an optically obtained plethysmogram; a photoplethysmogram (PPG). This has gained much intrigue in the modelling of PPG signal using appropriate Synthesis techniques. The obtained circuit is used to reconstruct PPG waveform. The current work is a proposal of a method for the development of an equivalent circuit to simulate the PPG waveform. Based on the amount of energy, the PPG signal was segregated into ‘complex’ and ‘plain’ zones. To construct that, the individual waves were modelled using Fourier analysis method by MATLAB Curve Fitting Tool Box. Then, after generating the Fourier series coefficients from MATLAB, we obtained the sine and cosine components of the data along with the DC component. The sine and cosine components along with the DC component are added via an adder circuit, followed by an inverter, which generates the final PPG waveform using PSPICE. The building blocks of the Simulink model have been developed using sine and cos function generator blocks, and adder blocks thereby generating an appropriate waveform. The errors between the actual normal PPG waveform and reconstructed PPG waveform using PSPICE for one cycle have been computed, which results in deviations within acceptable ranges of deviation.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"580 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115851796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783210
Sayan Paramanik, K. Sarker, B. Mahanty, Avijit Chakraborty, D. Chatterjee, S. Goswami
Electric power is essential in modern life. Due to limitation of the present grid, wired household distribution system facing unpredictable technical challenges. Recently, micro grid & wireless power transfer (WPT) offers a brand new energy acquisition for increasing the reliability and decreasing power losses as well as overall cost of the system & power security. This present paper elaborates an overview of micro grid system & focused on WPT with mathematical calculation & hardware implementation. The proposed transmitter & receiver have a sensitivity of −91 dbm and bandwidth of the signal is 320 KHz to −320 KHz and device range is 7 meter. The proposed system has two phases for power transfer first is key exchange between the transmitter to the receiver and the second is encrypting the energy to allow for secure energy transmission. This paper also emphasizes on the latest technologies, and economical aspects.
{"title":"Smart Wireless Distribution for Micro Grid System","authors":"Sayan Paramanik, K. Sarker, B. Mahanty, Avijit Chakraborty, D. Chatterjee, S. Goswami","doi":"10.1109/DEVIC.2019.8783210","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783210","url":null,"abstract":"Electric power is essential in modern life. Due to limitation of the present grid, wired household distribution system facing unpredictable technical challenges. Recently, micro grid & wireless power transfer (WPT) offers a brand new energy acquisition for increasing the reliability and decreasing power losses as well as overall cost of the system & power security. This present paper elaborates an overview of micro grid system & focused on WPT with mathematical calculation & hardware implementation. The proposed transmitter & receiver have a sensitivity of −91 dbm and bandwidth of the signal is 320 KHz to −320 KHz and device range is 7 meter. The proposed system has two phases for power transfer first is key exchange between the transmitter to the receiver and the second is encrypting the energy to allow for secure energy transmission. This paper also emphasizes on the latest technologies, and economical aspects.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124938865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783400
Nidhi Taxak, Sachin Singhal
Image Fusion is a method, in which two relevant Image get combine and generate a new Image. The generated image has excellent clarity as compared to the previous input image. Image Fusion Technique is improving the performance of the images and increase the application of Image Fusion. In the Base paper, they present Image Fusion for Two-Dimensional Multiresolution 2-D image. The applications of the Image fusion is using various fields like multi - Focus Images, CT, Multi-Sensor Satellite image and MR of the Human Brain. In this Paper, working for improve PSNR(Peak Signal to Noise Ratio) and Reduce to MSE (Mean Square Error). For improve the performance of Image fusion using Weighted Average Brovery Transform. In the base paper, PSNR and MSE are comparing by use PCA, DWT, DWT-PCA, DCT-PCA, DWT-DCT-PCA methods. Proposed Weighted Average Brovery Transform method is showing better results as compare to base paper results.
{"title":"High PSNR based Image Fusion by Weighted Average Brovery Transform Method","authors":"Nidhi Taxak, Sachin Singhal","doi":"10.1109/DEVIC.2019.8783400","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783400","url":null,"abstract":"Image Fusion is a method, in which two relevant Image get combine and generate a new Image. The generated image has excellent clarity as compared to the previous input image. Image Fusion Technique is improving the performance of the images and increase the application of Image Fusion. In the Base paper, they present Image Fusion for Two-Dimensional Multiresolution 2-D image. The applications of the Image fusion is using various fields like multi - Focus Images, CT, Multi-Sensor Satellite image and MR of the Human Brain. In this Paper, working for improve PSNR(Peak Signal to Noise Ratio) and Reduce to MSE (Mean Square Error). For improve the performance of Image fusion using Weighted Average Brovery Transform. In the base paper, PSNR and MSE are comparing by use PCA, DWT, DWT-PCA, DCT-PCA, DWT-DCT-PCA methods. Proposed Weighted Average Brovery Transform method is showing better results as compare to base paper results.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122691676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783415
Muktasha Maji, Gaurav Saini
In this paper, the use of laterally graded doping and hetero gate high dielectric with high-k spacers which were positioned on both sides of the gate have been proposed to improve the performance of Junctionless Transistors (JLT). Further recessed gate structure is also used to compare its performance with conventional JLTs. 2-D TCAD simulations have been used to observe that the Drain-Induced Barrier Lowering (DIBL) and Sub Threshold Swing (SS) were reduced by 26% and 61% respectively. Further the current ratio improved by 108 times in the final structure. Our analysis focuses on the ability of the proposed design for a reduced leakage current leading to higher current ratio and also lower short channel effects (SCEs) like SS and DIBL.
{"title":"Performance Enhancement of Non-uniformly Doped Junctionless Transistors by Gate and Dielectric engineering","authors":"Muktasha Maji, Gaurav Saini","doi":"10.1109/DEVIC.2019.8783415","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783415","url":null,"abstract":"In this paper, the use of laterally graded doping and hetero gate high dielectric with high-k spacers which were positioned on both sides of the gate have been proposed to improve the performance of Junctionless Transistors (JLT). Further recessed gate structure is also used to compare its performance with conventional JLTs. 2-D TCAD simulations have been used to observe that the Drain-Induced Barrier Lowering (DIBL) and Sub Threshold Swing (SS) were reduced by 26% and 61% respectively. Further the current ratio improved by 108 times in the final structure. Our analysis focuses on the ability of the proposed design for a reduced leakage current leading to higher current ratio and also lower short channel effects (SCEs) like SS and DIBL.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131210847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783667
Hasanujjaman, U. Biswas, M. Naskar
Fractal image compression is a comparatively new and less explored technique in the domain of image processing. The main problem is it's very high image compression time due to the huge number of ‘range’ - ‘domain’ comparisons it has to undergo. If efficiently utilised, fractal image compression gives the best compression ratio which is highest among other contemporary techniques. In this paper we have proposed efficient hardware of a decoder for the fractal image compression. Controlled parallelism has been incorporated to speed up the decoding process. The whole design has been simulated and synthesized using verilog HDL.
{"title":"Hardware Architecture of a Decoder for Fractal Image Compression","authors":"Hasanujjaman, U. Biswas, M. Naskar","doi":"10.1109/DEVIC.2019.8783667","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783667","url":null,"abstract":"Fractal image compression is a comparatively new and less explored technique in the domain of image processing. The main problem is it's very high image compression time due to the huge number of ‘range’ - ‘domain’ comparisons it has to undergo. If efficiently utilised, fractal image compression gives the best compression ratio which is highest among other contemporary techniques. In this paper we have proposed efficient hardware of a decoder for the fractal image compression. Controlled parallelism has been incorporated to speed up the decoding process. The whole design has been simulated and synthesized using verilog HDL.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131418682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783702
A. Singh, A. Dikshit, Brahmdutta Dixit, V.V. Kharche, Kamal, J. Rana, P. Chakrabarti, A. Pandey
A Zinc oxide (ZnO)-based thin film transistor (TFT) has been proposed to be built using a high-k $mathbf{La}_{mathbf{x}}mathbf{Ta}_{1-mathbf{x}}mathbf{O}_{mathbf{y}}$ as an insulator to enhance their effectuation for backplane display technology. The device has been scrutinized on Silvaco ATLAS™ 2D simulator to examine the switching performance of the device for possible application in display driver circuits. To improvise the working of the TFT for the targeted application the atomic compositions of La and Ta in $mathbf{La}_{mathbf{x}}mathbf{Ta}_{1-mathbf{x}}mathbf{O}_{mathbf{y}}$ have been converted to attune the dielectric constant of the insulator. The study reveals that the high-k insulator-based ZnO TFT can be modified to obtain high on/off current ratio of the order of 108 to ensure the high-speed operation with low sub-threshold swing 0.49 V/dec which is desirable for low power applications. It has been demonstrated that high-k dielectric insulator-based ZnO TFT has great potential for the development of cost-effective large-area display systems.
{"title":"A Proposed High-k Dielectric Based Thin Film Transistor for Next Generation Backplane Display Technology","authors":"A. Singh, A. Dikshit, Brahmdutta Dixit, V.V. Kharche, Kamal, J. Rana, P. Chakrabarti, A. Pandey","doi":"10.1109/DEVIC.2019.8783702","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783702","url":null,"abstract":"A Zinc oxide (ZnO)-based thin film transistor (TFT) has been proposed to be built using a high-k $mathbf{La}_{mathbf{x}}mathbf{Ta}_{1-mathbf{x}}mathbf{O}_{mathbf{y}}$ as an insulator to enhance their effectuation for backplane display technology. The device has been scrutinized on Silvaco ATLAS™ 2D simulator to examine the switching performance of the device for possible application in display driver circuits. To improvise the working of the TFT for the targeted application the atomic compositions of La and Ta in $mathbf{La}_{mathbf{x}}mathbf{Ta}_{1-mathbf{x}}mathbf{O}_{mathbf{y}}$ have been converted to attune the dielectric constant of the insulator. The study reveals that the high-k insulator-based ZnO TFT can be modified to obtain high on/off current ratio of the order of 108 to ensure the high-speed operation with low sub-threshold swing 0.49 V/dec which is desirable for low power applications. It has been demonstrated that high-k dielectric insulator-based ZnO TFT has great potential for the development of cost-effective large-area display systems.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132790433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783644
D. Nayak, U. Nanda, P. Rout, S. Biswal, Dhananjaya Tripthy, S. Swain, Biswajit Baral, S. K. Das
The modern electronics gadget has influenced tremendously every aspects of life. The demand to add more and more functionality has forced to increase the performance of the processor. To ensure a robust data supply to the processor a high performance, stable and low power SRAM is also of utmost necessity. An indirect read SRAM cell is proposed here which eliminates the read noise insertion to increase the data stability. It also consumes 41% less energy compared to the conventional SRAM cell. The SRAM cell is designed to be written single ended using only one write access transistor. The cell reduces the energy consumption by reducing the short circuit current and also reducing the number of leakage path. The cell also has a high write speed since the storage data node is a floating node and not connected to the ground.
{"title":"A Novel Driver less SRAM with Indirect Read for Low Energy Consumption and Read Noise Elimination","authors":"D. Nayak, U. Nanda, P. Rout, S. Biswal, Dhananjaya Tripthy, S. Swain, Biswajit Baral, S. K. Das","doi":"10.1109/DEVIC.2019.8783644","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783644","url":null,"abstract":"The modern electronics gadget has influenced tremendously every aspects of life. The demand to add more and more functionality has forced to increase the performance of the processor. To ensure a robust data supply to the processor a high performance, stable and low power SRAM is also of utmost necessity. An indirect read SRAM cell is proposed here which eliminates the read noise insertion to increase the data stability. It also consumes 41% less energy compared to the conventional SRAM cell. The SRAM cell is designed to be written single ended using only one write access transistor. The cell reduces the energy consumption by reducing the short circuit current and also reducing the number of leakage path. The cell also has a high write speed since the storage data node is a floating node and not connected to the ground.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133262489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：