Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783775
Anirudh Aggarwal, R. Goswami, Kavindra Kandpal
This paper presents a study on the performance of a bottom gate ZnO thin film transistor (TFT) model through 2-D TCAD device simulations and proposes a surface potential analytical model for the same. The simulation has been calibrated with a fabricated ZnO TFT. The analytical model is found to be in good agreement with the simulated measurements. Through further analyses on TCAD tool, the electrical characteristics of ZnO TFT have been investigated to comprehensively deduce the effect of ZnO active layer thickness, the dielectric material and the drain voltage. To obtain a significant ratio of on and off currents, and a positive gate voltage switching, gate workfunction engineering has been demonstrated.
{"title":"Empirical Model of Surface Potential and Simulation Analyses for ZnO TFTs","authors":"Anirudh Aggarwal, R. Goswami, Kavindra Kandpal","doi":"10.1109/DEVIC.2019.8783775","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783775","url":null,"abstract":"This paper presents a study on the performance of a bottom gate ZnO thin film transistor (TFT) model through 2-D TCAD device simulations and proposes a surface potential analytical model for the same. The simulation has been calibrated with a fabricated ZnO TFT. The analytical model is found to be in good agreement with the simulated measurements. Through further analyses on TCAD tool, the electrical characteristics of ZnO TFT have been investigated to comprehensively deduce the effect of ZnO active layer thickness, the dielectric material and the drain voltage. To obtain a significant ratio of on and off currents, and a positive gate voltage switching, gate workfunction engineering has been demonstrated.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124781211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783399
A. Mukhopadhyay, A. Sengupta, H. Rahaman
We investigate the effects of uniaxial tensile and compressive strain on the material and transport properties of semiconducting Carbon Nanotube and the device properties of Blue-Phosphorene-CNT heterojunction devices. We see that the material and transport properties of the semiconducting CNT can be tuned through the application of uniaxial strain. The device properties of the heterojunction can also be modulated by strain. The variation in the current is significant in tensile strain zone.
{"title":"Effect of Uniaxial Strain on Properties of Blue Phosphorene-CNT Heterojunction","authors":"A. Mukhopadhyay, A. Sengupta, H. Rahaman","doi":"10.1109/DEVIC.2019.8783399","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783399","url":null,"abstract":"We investigate the effects of uniaxial tensile and compressive strain on the material and transport properties of semiconducting Carbon Nanotube and the device properties of Blue-Phosphorene-CNT heterojunction devices. We see that the material and transport properties of the semiconducting CNT can be tuned through the application of uniaxial strain. The device properties of the heterojunction can also be modulated by strain. The variation in the current is significant in tensile strain zone.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123033505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783322
I. Hussain, C. Pandey, S. Chaudhury
Multiplier is of the most important blocks of many VLSI application. So, it is required to design high performance multiplier to boost up the performance of those circuits and systems. In this work, a high performing Multiplier has been designed by using Wallace tree algorithm. The multiplier has been designed in three modules. Initially partial products are generated followed by partial products processing. Finally, final addition is computed in the 3rd module. Partial products have been generated by using AND gates. Partial products are computed by using Wallace tree logarithm. Final addition has been done by fast adder. The performance of the proposed multiplier circuit is evaluated by using 90nm CMOS technology at the Synopsys tool. The performance of the same is compared conventional multiplier circuits. The performance of the proposed adder has been found to be satisfactory.
{"title":"Design and Analysis of High Performance Multiplier Circuit","authors":"I. Hussain, C. Pandey, S. Chaudhury","doi":"10.1109/DEVIC.2019.8783322","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783322","url":null,"abstract":"Multiplier is of the most important blocks of many VLSI application. So, it is required to design high performance multiplier to boost up the performance of those circuits and systems. In this work, a high performing Multiplier has been designed by using Wallace tree algorithm. The multiplier has been designed in three modules. Initially partial products are generated followed by partial products processing. Finally, final addition is computed in the 3rd module. Partial products have been generated by using AND gates. Partial products are computed by using Wallace tree logarithm. Final addition has been done by fast adder. The performance of the proposed multiplier circuit is evaluated by using 90nm CMOS technology at the Synopsys tool. The performance of the same is compared conventional multiplier circuits. The performance of the proposed adder has been found to be satisfactory.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132396200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783538
Savio Jay Sengupta, Dipanjan Sen, Subhashis Roy, Sudhabindu Ray, S. Sarkar
This work presents the analysis of a charge pump circuit for UHF RFID tag design using 22nm CMOS technology. A charge pump circuit is basically a DC to DC converter. This circuit can be used in many systems for its high performance and low power consumption. Hence, this voltage charge pump circuit can be used in low voltage applications such as in RFID tag's EEPROM. This charge pump circuit has been used as a part of the power supply unit of a fully integrated RFID transponder IC. This modified circuit can generate a stable output voltage with low power dissipation and higher gain for RFID applications. Measured output of this circuit at 433MHz frequency with 1pF of pumping capacitor value, is 3.48V which is more than the value of the industry standardized voltage 3.3V. The extensive simulations are done by using T-spice simulator.
{"title":"Analysis of Four-Stage Charge Pump Circuit for UHF RFID Tag Design","authors":"Savio Jay Sengupta, Dipanjan Sen, Subhashis Roy, Sudhabindu Ray, S. Sarkar","doi":"10.1109/DEVIC.2019.8783538","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783538","url":null,"abstract":"This work presents the analysis of a charge pump circuit for UHF RFID tag design using 22nm CMOS technology. A charge pump circuit is basically a DC to DC converter. This circuit can be used in many systems for its high performance and low power consumption. Hence, this voltage charge pump circuit can be used in low voltage applications such as in RFID tag's EEPROM. This charge pump circuit has been used as a part of the power supply unit of a fully integrated RFID transponder IC. This modified circuit can generate a stable output voltage with low power dissipation and higher gain for RFID applications. Measured output of this circuit at 433MHz frequency with 1pF of pumping capacitor value, is 3.48V which is more than the value of the industry standardized voltage 3.3V. The extensive simulations are done by using T-spice simulator.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134401488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783940
Prashant Kumar, Ashis Kumar Das, S. Halder
Heart rate variability (HRV) analysis of electrocardiogram (ECG) signal is used to examine the health condition of the sportsperson. For the present work, a total of 22 numbers of data were taken from eleven participants in two different physical conditions who are under regular sporting activity. One set of data were taken just after playing badminton and 400–600 m run and another set of ECG data were taken in the normal i.e., relaxed condition. Acquired ECG signal is pre-processed for removal of powerline frequency, baseline wander (BW) removal, removal of low-frequency noise. The smoothening filter is also used for removal of high-frequency noise for smoothing of the wave. The filtered signals are used for HRV analysis. HRV is associated with average heart rate (HR) tachycardia and bradycardia. Main HRV parameters like mean heart rate, mean RR-interval, SDNN, RMSSD, NN50, pNN50 are analyzed in two different conditions namely post exercise and relaxed condition. In addition to HRV, the complexity analysis of the signal is also being done in the contest of sample entropy, approximate entropy etc.
{"title":"Comparative HRV Analysis of ECG Signal in the Context of Sportsperson under Post-Exercise and Relaxed Condition","authors":"Prashant Kumar, Ashis Kumar Das, S. Halder","doi":"10.1109/DEVIC.2019.8783940","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783940","url":null,"abstract":"Heart rate variability (HRV) analysis of electrocardiogram (ECG) signal is used to examine the health condition of the sportsperson. For the present work, a total of 22 numbers of data were taken from eleven participants in two different physical conditions who are under regular sporting activity. One set of data were taken just after playing badminton and 400–600 m run and another set of ECG data were taken in the normal i.e., relaxed condition. Acquired ECG signal is pre-processed for removal of powerline frequency, baseline wander (BW) removal, removal of low-frequency noise. The smoothening filter is also used for removal of high-frequency noise for smoothing of the wave. The filtered signals are used for HRV analysis. HRV is associated with average heart rate (HR) tachycardia and bradycardia. Main HRV parameters like mean heart rate, mean RR-interval, SDNN, RMSSD, NN50, pNN50 are analyzed in two different conditions namely post exercise and relaxed condition. In addition to HRV, the complexity analysis of the signal is also being done in the contest of sample entropy, approximate entropy etc.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133093065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783694
A. Ghosal, Subham Ghosh, Ayan Saha, N. Bhattacharjee, Srijan Kr. Bhar, Indranath Sarkar
Fuel economy is an important factor while buying an automobile. For automobile buyers, it has an impact on the running expenses of the vehicle. By definition fuel economy is the number of kilometers of distance that can be covered per liter or gallon worth of fuel. Automotive Research Association of India conducts fuel economy tests based on the Indian Driving Cycle. However, in practically driving conditions, one can expect to get −10% to −20% (less) of the ARAI certified values. This paper aims at designing a mileage meter along with a vehicle tracking provision. The users will have a better option to examine the vehicle's performance before and after purchasing it can also be attached in an existing vehicle.
{"title":"Scholastic Approach towards Economic Digital Mileage Meter with GPS","authors":"A. Ghosal, Subham Ghosh, Ayan Saha, N. Bhattacharjee, Srijan Kr. Bhar, Indranath Sarkar","doi":"10.1109/DEVIC.2019.8783694","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783694","url":null,"abstract":"Fuel economy is an important factor while buying an automobile. For automobile buyers, it has an impact on the running expenses of the vehicle. By definition fuel economy is the number of kilometers of distance that can be covered per liter or gallon worth of fuel. Automotive Research Association of India conducts fuel economy tests based on the Indian Driving Cycle. However, in practically driving conditions, one can expect to get −10% to −20% (less) of the ARAI certified values. This paper aims at designing a mileage meter along with a vehicle tracking provision. The users will have a better option to examine the vehicle's performance before and after purchasing it can also be attached in an existing vehicle.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123344128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783891
S. Tripathi, Shekhar Verma, Namrata Dhanda
The Tunnel FET has substantial potential to overcome limitations imposed due the scaling in low voltage region because of its steep subthreshold slope relative to its corresponding junction based MOSFET counterpart. Use of Si0.7Ge0.3 material as pocket region (0.5nm) enhances band-to-band tunneling by decreasing tunneling distance. The proposed pocket ultra small pocket Si0.7Ge0.3 Junction-less TFET(JLTFET) exploits advantage junction-less regions and p-type pocket region to improve device performance in subthreshold region showing improvement in subthreshold slope and better ON and OFF-state drain current ratio as compared to other similar TFET structures. Proposed ultra small pocket JLTFET shows high value $mathbf{I}_{mathbf{ON}}/mathbf{I}_{mathbf{OFF}}$ ratio and good subthreshold behaviour even with 2nm gate length and body thickness 0.5nm. All the designs proposed for n JLTFETs are designed on visual TCAD 2D/3D device simulator.
{"title":"Characterisation of Ultra-Small Pocket Si0.7Ge0.3 Junction-less Tunnel FET with SOI","authors":"S. Tripathi, Shekhar Verma, Namrata Dhanda","doi":"10.1109/DEVIC.2019.8783891","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783891","url":null,"abstract":"The Tunnel FET has substantial potential to overcome limitations imposed due the scaling in low voltage region because of its steep subthreshold slope relative to its corresponding junction based MOSFET counterpart. Use of Si0.7Ge0.3 material as pocket region (0.5nm) enhances band-to-band tunneling by decreasing tunneling distance. The proposed pocket ultra small pocket Si0.7Ge0.3 Junction-less TFET(JLTFET) exploits advantage junction-less regions and p-type pocket region to improve device performance in subthreshold region showing improvement in subthreshold slope and better ON and OFF-state drain current ratio as compared to other similar TFET structures. Proposed ultra small pocket JLTFET shows high value $mathbf{I}_{mathbf{ON}}/mathbf{I}_{mathbf{OFF}}$ ratio and good subthreshold behaviour even with 2nm gate length and body thickness 0.5nm. All the designs proposed for n JLTFETs are designed on visual TCAD 2D/3D device simulator.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121550468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783704
Sayan Paramanik, K. Sarker, D. Chatterjee, S. Goswami
The Smart Grid (SG) system typically deals with different issues involving security and Power Quality (PQ) improvement. With frequent usage of power electronic devices and nonlinear load, harmonics are inserted into the system. The well-known Flexible AC Transmission System (FACTS) devices like Unified Power Quality Conditioners (UPQC) are usually employed to resolve the issues related to voltage sag, swell, flicker, PQ, and neutral current reduction of distribution systems. An UPQC itself inserts harmonics into the system that affects the system stability for sensitive loads. This paper describes biogeography based optimization (BBO) with harmonics elimination techniques for modified UPQC connected with SG. Lower order harmonics are eliminated by proper selection of switching angles and at the same time the higher order harmonics are suppressed by injecting same order harmonics with equal magnitude but opposite in phase from the other converter. The excitation of Modified UPQC converters are obtained from PV (Photo-Voltaic) panel. The firing angles of series-shunt converter are obtained in real-time from the already stored angles in the microcontroller memory.
{"title":"Smart Grid Power Quality Improvement Using Modified UPQC","authors":"Sayan Paramanik, K. Sarker, D. Chatterjee, S. Goswami","doi":"10.1109/DEVIC.2019.8783704","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783704","url":null,"abstract":"The Smart Grid (SG) system typically deals with different issues involving security and Power Quality (PQ) improvement. With frequent usage of power electronic devices and nonlinear load, harmonics are inserted into the system. The well-known Flexible AC Transmission System (FACTS) devices like Unified Power Quality Conditioners (UPQC) are usually employed to resolve the issues related to voltage sag, swell, flicker, PQ, and neutral current reduction of distribution systems. An UPQC itself inserts harmonics into the system that affects the system stability for sensitive loads. This paper describes biogeography based optimization (BBO) with harmonics elimination techniques for modified UPQC connected with SG. Lower order harmonics are eliminated by proper selection of switching angles and at the same time the higher order harmonics are suppressed by injecting same order harmonics with equal magnitude but opposite in phase from the other converter. The excitation of Modified UPQC converters are obtained from PV (Photo-Voltaic) panel. The firing angles of series-shunt converter are obtained in real-time from the already stored angles in the microcontroller memory.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121788337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783765
Alekhya Yalla, U. Nanda
Low voltage operation and low power consumption is of paramount need in integrated circuits which are employed in portable devices. Floating gate MOS (FGMOS) transistor is an analog technique to achieve low power while maintaining performance in various applications such as neural networks, PLL, D/A and A/D converters and memory circuits. This paper deals with various FGMOS techniques with supply voltage $mathrm{V_{DD}}=220mathrm{mV}$ operating in sub-threshold region which is very crucial for lowering power dissipation and achieves higher speed compared to CMOS circuits. The proposed work is validated through inverter circuits using TSMC $mathbf{0.18mu{m}}$ technology in mentor graphics tool.
{"title":"Quasi FGMOS Inverter: A Strategy for low power applications","authors":"Alekhya Yalla, U. Nanda","doi":"10.1109/DEVIC.2019.8783765","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783765","url":null,"abstract":"Low voltage operation and low power consumption is of paramount need in integrated circuits which are employed in portable devices. Floating gate MOS (FGMOS) transistor is an analog technique to achieve low power while maintaining performance in various applications such as neural networks, PLL, D/A and A/D converters and memory circuits. This paper deals with various FGMOS techniques with supply voltage $mathrm{V_{DD}}=220mathrm{mV}$ operating in sub-threshold region which is very crucial for lowering power dissipation and achieves higher speed compared to CMOS circuits. The proposed work is validated through inverter circuits using TSMC $mathbf{0.18mu{m}}$ technology in mentor graphics tool.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122056188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783330
Dipanjan Sen, Savio Jay Sengupta, Subhashis Roy, Sudhabindu Ray, S. Sarkar
In this proposed article, a realization of RFID memory cell has been performed using Dual Material Double Gate Stack-Oxide Junction-Less MOSFET for high speed and low power application [1] in Sub-threshold regime. SNM, Power and Delay of the Memory Cell or SRAM circuit in different operating modes have been analyzed in depth. Dual Material Double Gate Oxide-Stack Junction-Less MOSFET (DMDGS-JLT) shows promising $mathrm{I}_mathrm{ON}/mathrm{I}_mathrm{OFF}$ ratio, less subthreshold swing and less Drain Induced Barrier Lowering or DIBL, in comparison with Double Gate Junction-Less MOSFET. So, proposed SRAM cell would be efficacious to offer less power dissipation and higher speed and a better Static Noise Margin. The impact of DMDGS-JLT in realizing RFID memory cell or SRAM has been studied in sub-threshold regime for ultra-low power tag design. Extensive simulations are performed using SILVACO ATLAS platform to validate the analyzed models. Besides, an optimum supply voltage range has been chosen to get an ultra-low power and higher speed of operation. DMDGS-JLT can be an alternative for ultra-low power Passive-RFID tag design, which results into greater time-span of the battery.
{"title":"Impact Analysis of Dual Material Double Gate Oxide-Stack Junction-Less MOSFET in RFID Memory Cell Realisation","authors":"Dipanjan Sen, Savio Jay Sengupta, Subhashis Roy, Sudhabindu Ray, S. Sarkar","doi":"10.1109/DEVIC.2019.8783330","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783330","url":null,"abstract":"In this proposed article, a realization of RFID memory cell has been performed using Dual Material Double Gate Stack-Oxide Junction-Less MOSFET for high speed and low power application [1] in Sub-threshold regime. SNM, Power and Delay of the Memory Cell or SRAM circuit in different operating modes have been analyzed in depth. Dual Material Double Gate Oxide-Stack Junction-Less MOSFET (DMDGS-JLT) shows promising $mathrm{I}_mathrm{ON}/mathrm{I}_mathrm{OFF}$ ratio, less subthreshold swing and less Drain Induced Barrier Lowering or DIBL, in comparison with Double Gate Junction-Less MOSFET. So, proposed SRAM cell would be efficacious to offer less power dissipation and higher speed and a better Static Noise Margin. The impact of DMDGS-JLT in realizing RFID memory cell or SRAM has been studied in sub-threshold regime for ultra-low power tag design. Extensive simulations are performed using SILVACO ATLAS platform to validate the analyzed models. Besides, an optimum supply voltage range has been chosen to get an ultra-low power and higher speed of operation. DMDGS-JLT can be an alternative for ultra-low power Passive-RFID tag design, which results into greater time-span of the battery.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129163122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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