Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783474
C. Singh, Anisha Pathania, K. Sharma, Jaya Madan, Rajnish Sharma
Transimpedance amplifier (TIA) has become an integral part of front-end electronics required for current sensing applications. In this paper, an integrator-differentiator block as an integral part of TIA has been reported using $pmb{0.18} mathbf{mu m}$ technology in standard CMOS N-well process. A tunable pseudo-resistor has been deployed in the proposed TIA architecture to obtain a variable gain and bandwidth of interest. The reported work also discusses the problem of saturation and clock feed-through present in the integrator block. The simulated gain and noise plots for the integrator-differentiator blocks are also presented in this work. Research effort put forth in this way in implementing the TIA may be helpful for efficient current recording and detection.
{"title":"Design of an Integrator-Differentiator Block For a Transimpedance Amplifier Using $0.18mu mathrm{m}$ Technology","authors":"C. Singh, Anisha Pathania, K. Sharma, Jaya Madan, Rajnish Sharma","doi":"10.1109/DEVIC.2019.8783474","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783474","url":null,"abstract":"Transimpedance amplifier (TIA) has become an integral part of front-end electronics required for current sensing applications. In this paper, an integrator-differentiator block as an integral part of TIA has been reported using $pmb{0.18} mathbf{mu m}$ technology in standard CMOS N-well process. A tunable pseudo-resistor has been deployed in the proposed TIA architecture to obtain a variable gain and bandwidth of interest. The reported work also discusses the problem of saturation and clock feed-through present in the integrator block. The simulated gain and noise plots for the integrator-differentiator blocks are also presented in this work. Research effort put forth in this way in implementing the TIA may be helpful for efficient current recording and detection.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134436957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783813
S. Biswal, S. Swain, Biswajit Baral, D. Nayak, U. Nanda, S. K. Das, Dhananjaya Tripthy
This paper presents the performance of SRG Tunnel FET biosensor. Here the different device parameters are deliberate to meet the requirement of the technological development. Focus is made on how TFET can be a substitute ahead of CMOS characteristics for biosensor mean and to more enhance the low power design policy to facilitate it for IOT purpose. There is a experimentally demonstration has been done for nanogap cavity A nanogap cavity region. Investigation of the staggered gap hetero junction SRG TFET was done. The results are obtained using Silvaco software.
{"title":"Performance Analysis of Staggered Heterojunction based SRG TFET biosensor for health IoT application","authors":"S. Biswal, S. Swain, Biswajit Baral, D. Nayak, U. Nanda, S. K. Das, Dhananjaya Tripthy","doi":"10.1109/DEVIC.2019.8783813","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783813","url":null,"abstract":"This paper presents the performance of SRG Tunnel FET biosensor. Here the different device parameters are deliberate to meet the requirement of the technological development. Focus is made on how TFET can be a substitute ahead of CMOS characteristics for biosensor mean and to more enhance the low power design policy to facilitate it for IOT purpose. There is a experimentally demonstration has been done for nanogap cavity A nanogap cavity region. Investigation of the staggered gap hetero junction SRG TFET was done. The results are obtained using Silvaco software.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122808421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783943
S. Sahoo, S. Dash, G. P. Mishra
In this paper a simulated device configuration is introduced for doping less charge plasma tunnel FET (CP-TFET) to improving the drain current and ambipolar nature. To achieve these improvements, we have proposed drain electrode work-function modulation engineering along with hetero dielectric in CP-TFET. The use of varied work-function modulation technique in drain region significantly reduces the ambipolar current by modifying the tunneling barrier width at the proximity of drain junction. However, the combined effect of hetero dielectric with drain electrode work-function modulation results in improved ON-current $(mathrm{I}_mathrm{ON})$ and reduced ambipolar-current (IAMB). The paper presents a comparative DC analysis of drain work-function modulated hetero gate charge plasma TFET (DWM-HCP-TFET) with that of conventional charge plasma TFET (CP-TFET). Analysis is done to prove the superiority of DWM-HCP-TFET over the conventional model.
{"title":"Work-function modulated hetero gate charge plasma TFET to enhance the device performance","authors":"S. Sahoo, S. Dash, G. P. Mishra","doi":"10.1109/DEVIC.2019.8783943","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783943","url":null,"abstract":"In this paper a simulated device configuration is introduced for doping less charge plasma tunnel FET (CP-TFET) to improving the drain current and ambipolar nature. To achieve these improvements, we have proposed drain electrode work-function modulation engineering along with hetero dielectric in CP-TFET. The use of varied work-function modulation technique in drain region significantly reduces the ambipolar current by modifying the tunneling barrier width at the proximity of drain junction. However, the combined effect of hetero dielectric with drain electrode work-function modulation results in improved ON-current $(mathrm{I}_mathrm{ON})$ and reduced ambipolar-current (IAMB). The paper presents a comparative DC analysis of drain work-function modulated hetero gate charge plasma TFET (DWM-HCP-TFET) with that of conventional charge plasma TFET (CP-TFET). Analysis is done to prove the superiority of DWM-HCP-TFET over the conventional model.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116010662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783302
Susmita Das, Dalia Nandi Das, B. Neogi
In the present research work, the analysis and design aspect of artificial ankle for facility creation of transtibial amputated person is carried out. Artificial system development has achieved the most powerful impact to reproduce the presentation and functionality of amputated body parts or body organs. Ergonomics and human factors related research work is taken in this paper for the development of physically challenged people. These systems are initiated to energize the damaged limbs, in order to make the total living system operative in conjunction with the concerned artificial limb. A living body maintains the overall control of various parts of the system through sensory organs. The artificial limb is required to be properly attached to the concerned system with direct connection to the limb of the amputee patient. The artificial limb which normally needs to be controlled by motor movement is related with the electromyography signal. The EMG (Electro Myography) in this context is driving the limb through the motor providing the appropriate output signal which finally performs the required movement or operation of ankle joint.
{"title":"Design Approach for Artificial Human Ankle Movement","authors":"Susmita Das, Dalia Nandi Das, B. Neogi","doi":"10.1109/DEVIC.2019.8783302","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783302","url":null,"abstract":"In the present research work, the analysis and design aspect of artificial ankle for facility creation of transtibial amputated person is carried out. Artificial system development has achieved the most powerful impact to reproduce the presentation and functionality of amputated body parts or body organs. Ergonomics and human factors related research work is taken in this paper for the development of physically challenged people. These systems are initiated to energize the damaged limbs, in order to make the total living system operative in conjunction with the concerned artificial limb. A living body maintains the overall control of various parts of the system through sensory organs. The artificial limb is required to be properly attached to the concerned system with direct connection to the limb of the amputee patient. The artificial limb which normally needs to be controlled by motor movement is related with the electromyography signal. The EMG (Electro Myography) in this context is driving the limb through the motor providing the appropriate output signal which finally performs the required movement or operation of ankle joint.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128724747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783790
R. Majumdar, P. Gayen, S. Mondal, A. Sadhukhan, P. K. Das, I. Kushary
In this paper, development of cyber communication package in the application of grid connected solar system has been presented. Here, implemented communication methodology supports communication process with reduced latency, high security arrangement with various degrees of freedom. Faithful transferring of various electrical data for the purpose of measurement, monitoring and controlling actions depend on the bidirectional communication strategy. Thus, real-time communication of data through cyber network has been emphasized in this paper. The C# language based coding is done to develop the communication program. The notable features of proposed communication process are reduction of latency during data exchange by usage of advanced encryption standard (AES) algorithm, tightening of cyber security arrangement by implementing secured socket layer (SSL) and Rivest, Shamir and Adleman (RSA) algorithms. Various real-time experiments using internet connected computers have been done to verify the usability of the proposed communication concept along with its notable features in the application.
{"title":"A Cyber Communication Package in the Application of Grid Tied Solar System","authors":"R. Majumdar, P. Gayen, S. Mondal, A. Sadhukhan, P. K. Das, I. Kushary","doi":"10.1109/DEVIC.2019.8783790","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783790","url":null,"abstract":"In this paper, development of cyber communication package in the application of grid connected solar system has been presented. Here, implemented communication methodology supports communication process with reduced latency, high security arrangement with various degrees of freedom. Faithful transferring of various electrical data for the purpose of measurement, monitoring and controlling actions depend on the bidirectional communication strategy. Thus, real-time communication of data through cyber network has been emphasized in this paper. The C# language based coding is done to develop the communication program. The notable features of proposed communication process are reduction of latency during data exchange by usage of advanced encryption standard (AES) algorithm, tightening of cyber security arrangement by implementing secured socket layer (SSL) and Rivest, Shamir and Adleman (RSA) algorithms. Various real-time experiments using internet connected computers have been done to verify the usability of the proposed communication concept along with its notable features in the application.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126367117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783383
Sarosij Adak, Nisarga Chand, S. Swain, A. Sarkar
This paper reports the effect of AlGaN back barrier on the performance of lattice matched In0.17Al0.83N/AlN/GaN Recess Gate E HEMT Device. The use of AlGaN back barrier on this device relaxes the GaN channel, which in turn limits the SCEs. Moreover reduced the leakage current through gate (Ig) and simultaneously improves carrier confinement and off state breakdown voltage. The numerical modeling are carried out with the help of 2D Sentaurus TCAD simulator using Hydrodynamic model, which is standardized with respect to already published fabricated results. Different performance parameters are studied using the simulations and a wide comparison was done with and without considering AlGaN back barrier (BB). Addition of AlGaN BB has added benefits in performance parameters w.r.t without BB i.e. threshold voltage raised to 0.93 volt with respect to 0.75 volt, drop in DIBL from 100mv/V to 36mv/V and substantial reduction in gate leakage current. These results reveal that use of AlGaN BB in such devices can be an alternative solution for high power and high frequency switching applications.
{"title":"Effect of AlGaN Back Barrier on InAlN/AlN/GaN E-Mode HEMTs","authors":"Sarosij Adak, Nisarga Chand, S. Swain, A. Sarkar","doi":"10.1109/DEVIC.2019.8783383","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783383","url":null,"abstract":"This paper reports the effect of AlGaN back barrier on the performance of lattice matched In0.17Al0.83N/AlN/GaN Recess Gate E HEMT Device. The use of AlGaN back barrier on this device relaxes the GaN channel, which in turn limits the SCEs. Moreover reduced the leakage current through gate (Ig) and simultaneously improves carrier confinement and off state breakdown voltage. The numerical modeling are carried out with the help of 2D Sentaurus TCAD simulator using Hydrodynamic model, which is standardized with respect to already published fabricated results. Different performance parameters are studied using the simulations and a wide comparison was done with and without considering AlGaN back barrier (BB). Addition of AlGaN BB has added benefits in performance parameters w.r.t without BB i.e. threshold voltage raised to 0.93 volt with respect to 0.75 volt, drop in DIBL from 100mv/V to 36mv/V and substantial reduction in gate leakage current. These results reveal that use of AlGaN BB in such devices can be an alternative solution for high power and high frequency switching applications.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115722544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783978
G. Sahoo, G. P. Mishra
Maximum use of solar spectrum is possible through the selection of suitable band gap material in a solar cell. Single junction hetero structure solar cell provides a better opportunity by opting different materials with different band gap in the preparation of such device. But the problem arises with the large lattice mismatch and band discontinuity among these materials, which drastically reduces the open circuit voltage $(mathrm{V}_{mathrm{oc}})$ as well as the fill factor of the cell. In this work, band alignment engineering has been introduced for such type of problems. The device is simulated and verified using Silvaco TCAD suite. An extensive study is carried out in terms of SRH, radiative recombination and its effect on $mathrm{V}_{mathrm{oc}}$ of the cell for different band offset values. It is found that the reduction in band discontinuity improves the $mathrm{V}_{mathrm{oc}}$ of the device.
{"title":"Extensive analysis of band alignment engineering on the open circuit voltage performance of a GaAs/GaSb hetero structure solar cell","authors":"G. Sahoo, G. P. Mishra","doi":"10.1109/DEVIC.2019.8783978","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783978","url":null,"abstract":"Maximum use of solar spectrum is possible through the selection of suitable band gap material in a solar cell. Single junction hetero structure solar cell provides a better opportunity by opting different materials with different band gap in the preparation of such device. But the problem arises with the large lattice mismatch and band discontinuity among these materials, which drastically reduces the open circuit voltage $(mathrm{V}_{mathrm{oc}})$ as well as the fill factor of the cell. In this work, band alignment engineering has been introduced for such type of problems. The device is simulated and verified using Silvaco TCAD suite. An extensive study is carried out in terms of SRH, radiative recombination and its effect on $mathrm{V}_{mathrm{oc}}$ of the cell for different band offset values. It is found that the reduction in band discontinuity improves the $mathrm{V}_{mathrm{oc}}$ of the device.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129138168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783327
A. Basak, A. Sarkar
In this paper, we present a 2D analytical modeling of UTBB SOI MOSFET by introducing a gap in the gate for which this new structure behaves like a dual gate MOSFET and compared the result with TCAD simulation. A 2D Poisson's equation is used for solving surface potential profile, electric field distribution, threshold voltage, DIBL and drain current of UTBB SOI MOSFET structure through parabolic approximation method. A comparative study for increasing negative voltage on control gate of this structure has been carried out. Here we observe surface potential profile, electric field distributions, threshold voltage, DIBL and drain current through applying negative voltage on the right gate of the proposed structure. Result reveals that this structure have higher efficacy to reduce short channel effect (SCE) due to the existence of step change in the surface potential distribution and for increasing negative control gate voltage this structure provides better performance for suppression short channel effect.
在本文中，我们提出了UTBB SOI MOSFET的二维解析建模，通过在栅极中引入一个间隙，这种新结构的行为类似于双栅极MOSFET，并将结果与TCAD仿真进行了比较。利用二维泊松方程，采用抛物线近似法求解了UTBB SOI MOSFET结构的表面电位分布、电场分布、阈值电压、DIBL和漏极电流。并对该结构的控制栅极增加负电压进行了对比研究。通过对该结构的右栅极施加负电压，我们观察了表面电位分布、电场分布、阈值电压、DIBL和漏极电流。结果表明，由于表面电位分布存在阶跃变化，该结构具有较高的抑制短通道效应(SCE)的效果，并且在提高负控制栅电压方面具有较好的抑制短通道效应的性能。
{"title":"Analytical Drain Current Model of UTBB SOI MOSFET with lateral dual gates to Suppress Short Channel Effect","authors":"A. Basak, A. Sarkar","doi":"10.1109/DEVIC.2019.8783327","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783327","url":null,"abstract":"In this paper, we present a 2D analytical modeling of UTBB SOI MOSFET by introducing a gap in the gate for which this new structure behaves like a dual gate MOSFET and compared the result with TCAD simulation. A 2D Poisson's equation is used for solving surface potential profile, electric field distribution, threshold voltage, DIBL and drain current of UTBB SOI MOSFET structure through parabolic approximation method. A comparative study for increasing negative voltage on control gate of this structure has been carried out. Here we observe surface potential profile, electric field distributions, threshold voltage, DIBL and drain current through applying negative voltage on the right gate of the proposed structure. Result reveals that this structure have higher efficacy to reduce short channel effect (SCE) due to the existence of step change in the surface potential distribution and for increasing negative control gate voltage this structure provides better performance for suppression short channel effect.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115558439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-23DOI: 10.1109/DEVIC.2019.8783954
Mehebub Alam, S. Kundu, S. S. Thakur, Sumit Banerjee
This paper presents a novel algorithm for estimation of line outages using phasor angle measurements. In this algorithm, phasor angles obtained from load flow simulation for various outage cases and thereby simulated bus power mismatches (SBPM) are to be stored. On occurrence of actual outage, bus power mismatches are to be computed using PMU provided post outage as well as pre outage phasors. Thereafter comparison between simulated bus power mismatches and computed bus power mismatches (CBPM) is done through least square norm minimization approach to find out the actual outage case. Moreover, random Gaussian noise with zero mean and standard deviation from 1% to 5% is introduced in the proposed model to check the feasibility in real power system. Performance of the algorithm is tested on IEEE 5bus, 14 bus and 30 bus system. The simulation results show the efficiency and viability of the proposed algorithm.
{"title":"A new algorithm for single line outage estimation","authors":"Mehebub Alam, S. Kundu, S. S. Thakur, Sumit Banerjee","doi":"10.1109/DEVIC.2019.8783954","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783954","url":null,"abstract":"This paper presents a novel algorithm for estimation of line outages using phasor angle measurements. In this algorithm, phasor angles obtained from load flow simulation for various outage cases and thereby simulated bus power mismatches (SBPM) are to be stored. On occurrence of actual outage, bus power mismatches are to be computed using PMU provided post outage as well as pre outage phasors. Thereafter comparison between simulated bus power mismatches and computed bus power mismatches (CBPM) is done through least square norm minimization approach to find out the actual outage case. Moreover, random Gaussian noise with zero mean and standard deviation from 1% to 5% is introduced in the proposed model to check the feasibility in real power system. Performance of the algorithm is tested on IEEE 5bus, 14 bus and 30 bus system. The simulation results show the efficiency and viability of the proposed algorithm.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131321812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/DEVIC.2019.8783297
Somak Karan, C. Dey
A process having any pole at origin is said to be integrating in nature. In practice, it is difficult to obtain the desired output from such integrating processes with significant time delay. Pure integrating processes have inherent non self-regulating feature and hence if they are disturbed from their equilibrium condition, process output continuously fluctuates over a considerable period of time. In practice a number of industrial processes like combustion chamber, distillation column, chemical reactors are well-known integrating processes with considerable time delay. Smith predictor based control technique is an established methodology for controlling such processes with considerable dead time. But, this technique fails to perform satisfactorily for pure integrating processes with considerable time delay. Modified Smith predictor method by Majhi and Atherton may be considered to be a good alternative. However, its performance is not found to be quite satisfactory due to undesired overshoot and sluggish recovery. In addition, complexity lies with the tuning of three controllers involved in multi-loop structure. To overcome this limitation, a simple tuning methodology is proposed here for modified Smith predictor with two controllers only. Efficacy of the proposed mechanism is substantiated through performance evaluation of pure integrating processes with significant time delay in comparison with well-known modified Smith predictor tuning reported by Majhi and Atherton.
{"title":"Set point weighted modified Smith predictor for delay dominated integrating processes","authors":"Somak Karan, C. Dey","doi":"10.1109/DEVIC.2019.8783297","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783297","url":null,"abstract":"A process having any pole at origin is said to be integrating in nature. In practice, it is difficult to obtain the desired output from such integrating processes with significant time delay. Pure integrating processes have inherent non self-regulating feature and hence if they are disturbed from their equilibrium condition, process output continuously fluctuates over a considerable period of time. In practice a number of industrial processes like combustion chamber, distillation column, chemical reactors are well-known integrating processes with considerable time delay. Smith predictor based control technique is an established methodology for controlling such processes with considerable dead time. But, this technique fails to perform satisfactorily for pure integrating processes with considerable time delay. Modified Smith predictor method by Majhi and Atherton may be considered to be a good alternative. However, its performance is not found to be quite satisfactory due to undesired overshoot and sluggish recovery. In addition, complexity lies with the tuning of three controllers involved in multi-loop structure. To overcome this limitation, a simple tuning methodology is proposed here for modified Smith predictor with two controllers only. Efficacy of the proposed mechanism is substantiated through performance evaluation of pure integrating processes with significant time delay in comparison with well-known modified Smith predictor tuning reported by Majhi and Atherton.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115506478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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