Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941456
X. Ma, Y. Qian, F. Liu, F. Yoshida
Reliability of solder joints is essential to electronic packaging since they provide both the mechanical and electrical connections at PCB level assembly. Several efforts have been made to improve the mechanical properties of traditional Sn60-Pb40 solder alloys by adding small amounts of alloy elements, such as Ag, Sb, Cu, Pd, etc. (Vaynman et al., 1998; Takemoto et al., 1997; Devore, 1982). Although the provided experimental data illustrated the effect of improvements, the corresponding modification mechanism had been little discussed. In this work, a small amount of rare earth element La was added to Sn60-Pb40 solder in order to improve the reliability of solder joints without increasing the melting point. High temperature tensile tests of solder alloys and thermal fatigue tests of solder joints were conducted to validate the improvement. SEM observation further clarified the corresponding microstructure modification. Finally, the effect of adding small amount of La was deeply studied based upon thermodynamic models and eutectic growth kinetics.
焊点的可靠性对电子封装至关重要，因为它们在PCB级组装中提供机械和电气连接。通过添加少量的合金元素，如Ag、Sb、Cu、Pd等，已经做出了一些努力来改善传统Sn60-Pb40钎料合金的机械性能(Vaynman et al.， 1998;Takemoto等人，1997;德沃尔,1982)。虽然提供的实验数据说明了改进的效果，但对相应的改性机理却很少讨论。在Sn60-Pb40焊料中加入少量稀土元素La，在不提高焊点熔点的情况下提高焊点的可靠性。通过对钎料合金的高温拉伸试验和焊点的热疲劳试验验证了改进的有效性。SEM观察进一步明确了相应的显微组织改性。最后，基于热力学模型和共晶生长动力学，深入研究了添加少量La的影响。
{"title":"High reliable solder joints using Sn-Pb-La solder alloy","authors":"X. Ma, Y. Qian, F. Liu, F. Yoshida","doi":"10.1109/IPFA.2001.941456","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941456","url":null,"abstract":"Reliability of solder joints is essential to electronic packaging since they provide both the mechanical and electrical connections at PCB level assembly. Several efforts have been made to improve the mechanical properties of traditional Sn60-Pb40 solder alloys by adding small amounts of alloy elements, such as Ag, Sb, Cu, Pd, etc. (Vaynman et al., 1998; Takemoto et al., 1997; Devore, 1982). Although the provided experimental data illustrated the effect of improvements, the corresponding modification mechanism had been little discussed. In this work, a small amount of rare earth element La was added to Sn60-Pb40 solder in order to improve the reliability of solder joints without increasing the melting point. High temperature tensile tests of solder alloys and thermal fatigue tests of solder joints were conducted to validate the improvement. SEM observation further clarified the corresponding microstructure modification. Finally, the effect of adding small amount of La was deeply studied based upon thermodynamic models and eutectic growth kinetics.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"528 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124500736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941466
C. C. Ooi, K. H. Siek, K. Sim
The focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects after electrical fault isolation. In the highly competitive and challenging environment prevalent at present, failure analysis throughput time is of utmost important. Therefore, a quick, efficient and reliable physical failure analysis technique is needed. This paper discusses the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.
{"title":"Application of focused ion beam system as a defect localization and root cause analysis tool","authors":"C. C. Ooi, K. H. Siek, K. Sim","doi":"10.1109/IPFA.2001.941466","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941466","url":null,"abstract":"The focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects after electrical fault isolation. In the highly competitive and challenging environment prevalent at present, failure analysis throughput time is of utmost important. Therefore, a quick, efficient and reliable physical failure analysis technique is needed. This paper discusses the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130719101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941451
Larry Wagner
Semiconductor trends as embodied in the International Technology Roadmap for Semiconductors (ITRS) provides a guide for the challenges facing the failure analysis community. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are driven primarily by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The likely industry paths for addressing these challenges are discussed. The International Sematech Product Analysis Forum (Joseph et al, 2000) has identified ten primary challenges for the future of the failure analysis in the semiconductor industry: localization and electrical characterization; deprocessing techniques for new materials; system-on-a-chip; imaging of small defects and structures; detection and characterization of nonvisual defects; verification and test; globally dispersed entities as virtual factory; fault isolation and simulation software; cost of failure analysis; complexity and volume of data. These challenges have been correlated to the Technology Working Group Difficult Challenge table in the ITRS.
{"title":"Failure analysis challenges","authors":"Larry Wagner","doi":"10.1109/IPFA.2001.941451","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941451","url":null,"abstract":"Semiconductor trends as embodied in the International Technology Roadmap for Semiconductors (ITRS) provides a guide for the challenges facing the failure analysis community. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are driven primarily by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The likely industry paths for addressing these challenges are discussed. The International Sematech Product Analysis Forum (Joseph et al, 2000) has identified ten primary challenges for the future of the failure analysis in the semiconductor industry: localization and electrical characterization; deprocessing techniques for new materials; system-on-a-chip; imaging of small defects and structures; detection and characterization of nonvisual defects; verification and test; globally dispersed entities as virtual factory; fault isolation and simulation software; cost of failure analysis; complexity and volume of data. These challenges have been correlated to the Technology Working Group Difficult Challenge table in the ITRS.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115538146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941457
Xiaowu Zhang, C. Lee, W. Hua, M. Iyer, Teo Poi Siong, D. Pinjala, S. Srinivasamurthy
This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the 2nd level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. Firstly, the effect of the positioning of four silicon dice within the MCM package on the package warpage was studied. Secondly, the effect of package dimensions (the heat spreader thickness, structural adhesive thickness and substrate thickness) on the maximum residual stress and warpage of the package were performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of the solder joints is estimated by Darveaux's approach. A series of parametric studies is performed by changing the package dimensions. The results obtained from the modeling are useful for the design of multichip packages.
{"title":"Thermo-mechanical analysis for a multi chip build up substrate based package","authors":"Xiaowu Zhang, C. Lee, W. Hua, M. Iyer, Teo Poi Siong, D. Pinjala, S. Srinivasamurthy","doi":"10.1109/IPFA.2001.941457","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941457","url":null,"abstract":"This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the 2nd level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. Firstly, the effect of the positioning of four silicon dice within the MCM package on the package warpage was studied. Secondly, the effect of package dimensions (the heat spreader thickness, structural adhesive thickness and substrate thickness) on the maximum residual stress and warpage of the package were performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of the solder joints is estimated by Darveaux's approach. A series of parametric studies is performed by changing the package dimensions. The results obtained from the modeling are useful for the design of multichip packages.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127102895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941485
L. Béchou, Y. Ousten, Y. Danto
Scanning acoustic microscopy (SAM) is now a common detection method which produces high resolution images with focused ultrasonic waves ranging from 10 to 500 MHz. In this paper, first we propose improved methodologies in order to measure time-of-flight (TOF) with high accuracy and so localize defects in depth by digital signal processing used for the study of nonstationary signals as acoustic echoes. Secondly, we compare imaging mode capabilities associated with conventional acoustic focused probe propagation for SAM. Then, we apply these methods for localization of defects and failure analysis of ceramic capacitors, die-attach assembly and solder joint evaluation in a CBGA technology by C-SCAN analysis.
{"title":"New methods for scanning ultrasonic microscopy applications for failure analysis of microassembling technologies","authors":"L. Béchou, Y. Ousten, Y. Danto","doi":"10.1109/IPFA.2001.941485","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941485","url":null,"abstract":"Scanning acoustic microscopy (SAM) is now a common detection method which produces high resolution images with focused ultrasonic waves ranging from 10 to 500 MHz. In this paper, first we propose improved methodologies in order to measure time-of-flight (TOF) with high accuracy and so localize defects in depth by digital signal processing used for the study of nonstationary signals as acoustic echoes. Secondly, we compare imaging mode capabilities associated with conventional acoustic focused probe propagation for SAM. Then, we apply these methods for localization of defects and failure analysis of ceramic capacitors, die-attach assembly and solder joint evaluation in a CBGA technology by C-SCAN analysis.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125179633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941455
W. Loh, B. Cho, M. Li
The quasi-breakdown mechanism (QB) of thin gate oxides is investigated under bipolar constant current stressing. It was observed that there exist two distinct stages in quasi-breakdown (QB), characterized by their electrical recoverability. In the first or recoverable stage, leakage current after QB could be recovered to the SILC level by applying proper reverse bias. In the second or unrecoverable stage, however, no electrical recovery is observed. Conduction mechanisms at QB were also studied using carrier separation and DCIV techniques.
{"title":"Bipolar current stressing and electrical recovery of quasi-breakdown in thin gate oxides","authors":"W. Loh, B. Cho, M. Li","doi":"10.1109/IPFA.2001.941455","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941455","url":null,"abstract":"The quasi-breakdown mechanism (QB) of thin gate oxides is investigated under bipolar constant current stressing. It was observed that there exist two distinct stages in quasi-breakdown (QB), characterized by their electrical recoverability. In the first or recoverable stage, leakage current after QB could be recovered to the SILC level by applying proper reverse bias. In the second or unrecoverable stage, however, no electrical recovery is observed. Conduction mechanisms at QB were also studied using carrier separation and DCIV techniques.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"325 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133407018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941461
M. Ker, Che-Hao Chuang
ESD robustness of CMOS devices used in the I/O pad is a major reliability issue as the diffusion junction depth is reduced and LDD (lightly-doped drain)/salicide structures are generally used in sub-quarter-micron CMOS technology. In order to enhance ESD robustness, some ESD implantations have been reported for inclusion into the process flow to modify the device structures for ESD protection (Lee, 1997; Hsue and Ko, 1994; Lowrey and Chance, 1996; Yang, 2000). In this paper, the effectiveness of different ESD implantation solutions on NMOS and diode devices for ESD protection is investigated in a 0.18 /spl mu/m salicided bulk CMOS process. The second breakdown current (It2) of the fabricated devices is measured by the transmission line pulse generator (TLPG). The human-body-model (HBM) and the machine-model (MM) ESD levels of these devices are also measured and compared. The layout dependence of NMOS devices and diodes with different ESD implantations are also investigated.
随着扩散结深度的降低和LDD(轻掺杂漏极)/盐化物结构通常用于亚四分之一微米CMOS技术，用于I/O焊片的CMOS器件的ESD稳稳性是一个主要的可靠性问题。为了增强ESD的稳健性，一些ESD植入物已经被报道纳入到工艺流程中，以修改ESD保护的器件结构(Lee, 1997;Hsue and Ko, 1994;Lowrey and Chance, 1996;杨,2000)。本文在0.18 /spl mu/m的盐化体CMOS工艺中，研究了不同的ESD注入溶液对NMOS和二极管器件的ESD保护效果。利用传输线脉冲发生器(TLPG)测量器件的二次击穿电流(It2)。测量并比较了这些器件的人体模型(HBM)和机器模型(MM) ESD水平。研究了不同ESD植入方式对NMOS器件和二极管布局的影响。
{"title":"ESD implantations in 0.18-/spl mu/m salicided CMOS technology for on-chip ESD protection with layout consideration","authors":"M. Ker, Che-Hao Chuang","doi":"10.1109/IPFA.2001.941461","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941461","url":null,"abstract":"ESD robustness of CMOS devices used in the I/O pad is a major reliability issue as the diffusion junction depth is reduced and LDD (lightly-doped drain)/salicide structures are generally used in sub-quarter-micron CMOS technology. In order to enhance ESD robustness, some ESD implantations have been reported for inclusion into the process flow to modify the device structures for ESD protection (Lee, 1997; Hsue and Ko, 1994; Lowrey and Chance, 1996; Yang, 2000). In this paper, the effectiveness of different ESD implantation solutions on NMOS and diode devices for ESD protection is investigated in a 0.18 /spl mu/m salicided bulk CMOS process. The second breakdown current (It2) of the fabricated devices is measured by the transmission line pulse generator (TLPG). The human-body-model (HBM) and the machine-model (MM) ESD levels of these devices are also measured and compared. The layout dependence of NMOS devices and diodes with different ESD implantations are also investigated.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121247837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941478
D. Kim, J. Kim, B. Hwang, D. Cho, K. Kim, S.B. Kim, J. Hong, J. Park, M.Y. Lee
For the downscaling of CMOS device design rules with high device performance, the reduced active area forces formation of a borderless contact in local interconnects. As the contact area is decreased with downscaling, it induces failure of device electrical characteristics and reliability. The ultra-shallow junction structures used as basic technology for sub-0.15 /spl mu/m CMOS devices and the junction leakage induced by borderless contact leakage at the shallow trench edge are serious problems for CMOS devices with low standby power dissipation. Recently, several borderless contact structures have been reported (Gallagher et al., 1995; Subbanna et al., 1993; Wen-Chau Liu et al., 2000). In this paper, we estimate the electrical characteristics of borderless contact and demonstrate the borderless contact leakage induced standby failure on a sub-0.15 /spl mu/m 6-Tr SRAM device.
对于具有高性能的CMOS器件设计规则的降尺度，减小的有源面积迫使在局部互连中形成无边界接触。随着接触面积的减小，器件的电气特性和可靠性将受到影响。作为低于0.15 /spl mu/m的CMOS器件基础技术的超浅结结构和沟槽浅边无边界接触漏电引起的结漏是低待机功耗CMOS器件面临的严重问题。最近，一些无边界接触结构被报道(Gallagher et al.， 1995;Subbanna et al.， 1993;刘文洲等，2000)。在本文中，我们估计了无边界触点的电气特性，并演示了在低于0.15 /spl mu/m的6-Tr SRAM器件上无边界触点泄漏引起的待机故障。
{"title":"Borderless contact leakage induced standby current failure on sub-0.15 /spl mu/m CMOS device","authors":"D. Kim, J. Kim, B. Hwang, D. Cho, K. Kim, S.B. Kim, J. Hong, J. Park, M.Y. Lee","doi":"10.1109/IPFA.2001.941478","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941478","url":null,"abstract":"For the downscaling of CMOS device design rules with high device performance, the reduced active area forces formation of a borderless contact in local interconnects. As the contact area is decreased with downscaling, it induces failure of device electrical characteristics and reliability. The ultra-shallow junction structures used as basic technology for sub-0.15 /spl mu/m CMOS devices and the junction leakage induced by borderless contact leakage at the shallow trench edge are serious problems for CMOS devices with low standby power dissipation. Recently, several borderless contact structures have been reported (Gallagher et al., 1995; Subbanna et al., 1993; Wen-Chau Liu et al., 2000). In this paper, we estimate the electrical characteristics of borderless contact and demonstrate the borderless contact leakage induced standby failure on a sub-0.15 /spl mu/m 6-Tr SRAM device.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131109863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941460
S. Voldman, L. Lanzerotti, R. Johnson
With the growth of the high-speed data rate transmission, optical interconnect, and wireless marketplaces, heterojunction devices will play a central role in these communication systems. Heterojunction base-emitter design, bandgap engineering and technology scaling will each play a key role in the ability to achieve faster devices for the wired and wireless markets. As these structures are scaled, the sensitivity of these devices to electrostatic overstress (EOS), electrostatic discharge (ESD) and electromagnetic emissions (EMI) becomes a concern. Emitter-base design influences the ESD sensitivity and device performance of heterojunction bipolar transistor (HBT) devices. In this paper, the ESD sensitivity of the emitter-base junction of a SiGe HBT device is discussed. The evaluation of process variations and device design spacings on ESD robustness is evaluated for both positive and negative stress conditions as a function of the salicide location, emitter-base spacing, and collector opening.
{"title":"Emitter base junction ESD reliability of an epitaxial base silicon germanium heterojunction bipolar transistor","authors":"S. Voldman, L. Lanzerotti, R. Johnson","doi":"10.1109/IPFA.2001.941460","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941460","url":null,"abstract":"With the growth of the high-speed data rate transmission, optical interconnect, and wireless marketplaces, heterojunction devices will play a central role in these communication systems. Heterojunction base-emitter design, bandgap engineering and technology scaling will each play a key role in the ability to achieve faster devices for the wired and wireless markets. As these structures are scaled, the sensitivity of these devices to electrostatic overstress (EOS), electrostatic discharge (ESD) and electromagnetic emissions (EMI) becomes a concern. Emitter-base design influences the ESD sensitivity and device performance of heterojunction bipolar transistor (HBT) devices. In this paper, the ESD sensitivity of the emitter-base junction of a SiGe HBT device is discussed. The evaluation of process variations and device design spacings on ESD robustness is evaluated for both positive and negative stress conditions as a function of the salicide location, emitter-base spacing, and collector opening.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126214977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941486
Z. Mai, M. Palaniappan, J. Chin, C. E. Soh, L.A. Knauss, E. Fleet
Scanning superconducting quantum interference device (SQUID) microscopy, along with real time X-ray (RTX) microscopy and scanning acoustic microscopy (SAM), was used as a fault isolation tool for IC short circuit failure analysis. Fault isolation was carried out before physical analysis. Experimental procedures and results for both fault isolation and physical analysis are given in detail.
{"title":"Short failure analysis under fault isolation","authors":"Z. Mai, M. Palaniappan, J. Chin, C. E. Soh, L.A. Knauss, E. Fleet","doi":"10.1109/IPFA.2001.941486","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941486","url":null,"abstract":"Scanning superconducting quantum interference device (SQUID) microscopy, along with real time X-ray (RTX) microscopy and scanning acoustic microscopy (SAM), was used as a fault isolation tool for IC short circuit failure analysis. Fault isolation was carried out before physical analysis. Experimental procedures and results for both fault isolation and physical analysis are given in detail.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116771691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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