Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941480
Jeung-Woo Kim, Won-sang Song, Sam-Young Kim, Hyan-Soo Kim, Hyungoo Jeon, Chae-Bog Lim
With low electrical resistivity and superb electromigration properties relative to Al, Cu is considered an exemplary candidate for metallization in logic devices. The electromigration characteristics, however, are highly contingent upon the test criteria, which in turn vary with the test structure and/or materials, e.g. inter/intra-metal dielectrics. The thermal mismatch stress existing between low-k SiOF and Cu, for instance, degrades the metal adhesion and curtails the device lifetime (Riedel, 1997). Such deleterious stress may also induce an extrusion mode failure, resulting in an unstable EM data with high sigma (Ennis, 2000) and an improper estimation of via lifetime. In this study, we identify a few pertinent factors involved in the formation of Cu extrusion mode failures in a Cu-SiOF dual damascene structure, and propose a possible underlying mechanism. Extrusion-free specimens, i.e. once the problem is eliminated, show an activation energy of about 0.81 eV, and the EM failures are limited to the via regions.
{"title":"Characterization of Cu extrusion failure mode in dual-damascene Cu/low-k interconnects under electromigration reliability test","authors":"Jeung-Woo Kim, Won-sang Song, Sam-Young Kim, Hyan-Soo Kim, Hyungoo Jeon, Chae-Bog Lim","doi":"10.1109/IPFA.2001.941480","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941480","url":null,"abstract":"With low electrical resistivity and superb electromigration properties relative to Al, Cu is considered an exemplary candidate for metallization in logic devices. The electromigration characteristics, however, are highly contingent upon the test criteria, which in turn vary with the test structure and/or materials, e.g. inter/intra-metal dielectrics. The thermal mismatch stress existing between low-k SiOF and Cu, for instance, degrades the metal adhesion and curtails the device lifetime (Riedel, 1997). Such deleterious stress may also induce an extrusion mode failure, resulting in an unstable EM data with high sigma (Ennis, 2000) and an improper estimation of via lifetime. In this study, we identify a few pertinent factors involved in the formation of Cu extrusion mode failures in a Cu-SiOF dual damascene structure, and propose a possible underlying mechanism. Extrusion-free specimens, i.e. once the problem is eliminated, show an activation energy of about 0.81 eV, and the EM failures are limited to the via regions.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129522936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941458
L. B. Yew, C. Francis, S. Mohamed, Tang Wye Mun, L. Ki
This paper details failure analysis techniques developed to analyze failures of two types of substrate widely used in chip scale packages (CSPs): (a) tape CSP substrate with polyimide (PI) tape, and (b) laminate CSP substrate with bismaleimide-triazine (BT) resin. The structure of both tape and laminate CSP substrates are discussed in detail to aid in understanding the failure analysis techniques of both these materials.
{"title":"Development and optimization of substrate failure analysis techniques for chip scale packages","authors":"L. B. Yew, C. Francis, S. Mohamed, Tang Wye Mun, L. Ki","doi":"10.1109/IPFA.2001.941458","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941458","url":null,"abstract":"This paper details failure analysis techniques developed to analyze failures of two types of substrate widely used in chip scale packages (CSPs): (a) tape CSP substrate with polyimide (PI) tape, and (b) laminate CSP substrate with bismaleimide-triazine (BT) resin. The structure of both tape and laminate CSP substrates are discussed in detail to aid in understanding the failure analysis techniques of both these materials.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123377361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941492
Y. Tan, W. Chim, P. Lim
Stress-induced leakage current (SILC) decreases when the time-between-pulses (T/sub bp/) of an AC-pulse waveform is increased. The amount of SILC reduction generally decreases for the same increase in T/sub bp/, with increasing stress voltage magnitude and stress pulse width. A model developed to describe the trap generation and relaxation processes occurring during transient high-field stress from unipolar and bipolar pulse waveforms is presented in this paper.
{"title":"Stress-induced leakage current in thin oxides under high-field impulse stressing","authors":"Y. Tan, W. Chim, P. Lim","doi":"10.1109/IPFA.2001.941492","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941492","url":null,"abstract":"Stress-induced leakage current (SILC) decreases when the time-between-pulses (T/sub bp/) of an AC-pulse waveform is increased. The amount of SILC reduction generally decreases for the same increase in T/sub bp/, with increasing stress voltage magnitude and stress pulse width. A model developed to describe the trap generation and relaxation processes occurring during transient high-field stress from unipolar and bipolar pulse waveforms is presented in this paper.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124473024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941476
X. Gagnard, O. Bonnaud
Previous works (Gagnard and Bonnaud, Microelectron. Reliability vol. 39, pp. 75-763, 1999, and Proc. SPIE vol. 4182, pp. 142-50, 2000) demonstrated the possibility of realization of the gate oxide lifetime by a unique measurement based on leakage current. This indicator, easy to implement and able to decrease the test time, can be included in the routine of parametric tests. This work confirms the validity of this indicator and presents case studies related to BCD technology.
以前的作品(Gagnard和Bonnaud，微电子。可靠性vol. 39, pp. 75-763, 1999，和Proc. SPIE vol. 4182, pp. 142- 50,2000)证明了通过基于泄漏电流的独特测量实现栅极氧化物寿命的可能性。该指标易于实现，可缩短试验时间，可纳入参数试验的常规中。这项工作证实了这一指标的有效性，并提出了与BCD技术相关的案例研究。
{"title":"Unique measurement to monitor the gate oxide lifetime indicator, case studies","authors":"X. Gagnard, O. Bonnaud","doi":"10.1109/IPFA.2001.941476","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941476","url":null,"abstract":"Previous works (Gagnard and Bonnaud, Microelectron. Reliability vol. 39, pp. 75-763, 1999, and Proc. SPIE vol. 4182, pp. 142-50, 2000) demonstrated the possibility of realization of the gate oxide lifetime by a unique measurement based on leakage current. This indicator, easy to implement and able to decrease the test time, can be included in the routine of parametric tests. This work confirms the validity of this indicator and presents case studies related to BCD technology.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124194382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941487
Luo Ping, Neo Soh Ping
Normally, it is difficult to isolate and identify the root cause for sort failures, especially for functional failures. This problem is worst for the wafer foundry because of the limited information on the product from customer. Sort test failures are generally analysed by either a correlation study between yield and electrical test (ET) data on the ET structure in a scribe line or a fault isolation technique. The yield correlation method is not as efficient because of the complicated sort test, the limited electrical data (usually only a few sites for production wafers), and the variation of yield patterns and ET behaviour among wafers and lots. The fault isolation techniques may not be able to capture the failure defect, especially for functional failures. One of the major limitations for yield analysis is the irregular yield pattern and its variation among wafers and lots. An irregular yield pattern means a correspondingly similar irregular ET data pattern for those failure-related parameters. In other words, those failure-related ET parameters should have higher correlation with the yield map than the rest of parameters. Thus, based on the quantitative calculation of the correlation between the maps of failure bins and the ET parameters, those ET parameters with high correlation can be identified and reasonably believed to be failure-related. In this paper, the pattern correlation method is introduced and applied for a true case of functional failure with via issue.
{"title":"The application of pattern correlation method between maps of failure bins and electrical parameters in fault isolation","authors":"Luo Ping, Neo Soh Ping","doi":"10.1109/IPFA.2001.941487","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941487","url":null,"abstract":"Normally, it is difficult to isolate and identify the root cause for sort failures, especially for functional failures. This problem is worst for the wafer foundry because of the limited information on the product from customer. Sort test failures are generally analysed by either a correlation study between yield and electrical test (ET) data on the ET structure in a scribe line or a fault isolation technique. The yield correlation method is not as efficient because of the complicated sort test, the limited electrical data (usually only a few sites for production wafers), and the variation of yield patterns and ET behaviour among wafers and lots. The fault isolation techniques may not be able to capture the failure defect, especially for functional failures. One of the major limitations for yield analysis is the irregular yield pattern and its variation among wafers and lots. An irregular yield pattern means a correspondingly similar irregular ET data pattern for those failure-related parameters. In other words, those failure-related ET parameters should have higher correlation with the yield map than the rest of parameters. Thus, based on the quantitative calculation of the correlation between the maps of failure bins and the ET parameters, those ET parameters with high correlation can be identified and reasonably believed to be failure-related. In this paper, the pattern correlation method is introduced and applied for a true case of functional failure with via issue.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122641801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941481
S. Tan, S. H. Ong
Copper migration which exhibits dendrite short-circuits in conductor-insulator-conductor structures may result in failure and reliability problems in microcircuits. Earlier works (Harsanyi, 1995; Adema et al., 1990 and 1993; Rudra and Jennings, 1994; Nieman, 1994; Harsanyi, 1999) have shown this mechanism in moist conditions. This is known as wet migration. In this investigation, we have observed copper dendrite growth during burn-in stress in adhesive tape which was used for leadframes to maintain the coplanarity and stability of individual lead pins during semiconductor manufacturing. A special parallel lapping technique revealed the dendrite growth under the tape. It is believed that chemical interaction has taken place, especially due to polyamic acid, which apparently reacts with copper. Further evaluations with higher temperature and voltage simulation confirm this mechanism.
铜迁移在导体-绝缘体-导体结构中表现为枝晶短路，可能导致微电路的失效和可靠性问题。早期作品(Harsanyi, 1995;Adema等，1990年和1993年;Rudra and Jennings, 1994;尼曼,1994;Harsanyi, 1999)在潮湿条件下显示了这种机制。这就是所谓的湿迁移。在这项研究中，我们观察到在半导体制造过程中，用于引线架的胶带在烧蚀应力下铜枝晶的生长，以保持单个引脚的共面性和稳定性。一种特殊的平行研磨技术揭示了带子下的枝晶生长。人们认为发生了化学相互作用，特别是由于聚酰胺酸，它显然与铜发生了反应。在更高的温度和电压下进行的进一步评估证实了这一机制。
{"title":"A dry migration? Copper dendrite growth in adhesive tape during burn-in","authors":"S. Tan, S. H. Ong","doi":"10.1109/IPFA.2001.941481","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941481","url":null,"abstract":"Copper migration which exhibits dendrite short-circuits in conductor-insulator-conductor structures may result in failure and reliability problems in microcircuits. Earlier works (Harsanyi, 1995; Adema et al., 1990 and 1993; Rudra and Jennings, 1994; Nieman, 1994; Harsanyi, 1999) have shown this mechanism in moist conditions. This is known as wet migration. In this investigation, we have observed copper dendrite growth during burn-in stress in adhesive tape which was used for leadframes to maintain the coplanarity and stability of individual lead pins during semiconductor manufacturing. A special parallel lapping technique revealed the dendrite growth under the tape. It is believed that chemical interaction has taken place, especially due to polyamic acid, which apparently reacts with copper. Further evaluations with higher temperature and voltage simulation confirm this mechanism.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"7 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121006656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941479
H. Nguyen, C. Salm, T. Mouthaan, F. Kuper
Electromigration behaviour in W-plug/metal stripe structures is different from conventional metal-strip structures because there is a blocking boundary formed by the immobile W-plug in the contact/via. Electromigration failures occur more readily close to the W-plug than in metal-strip structures because metal ions are forced away from the contacts/vias by electric current, blocking the contacts/vias area. Several works have reported electromigration lifetime of multiple level interconnects to be influenced by the presence of a reservoir around the contacts/vias. Reservoirs are metal parts that are not or are hardly conducting current that act as a source to provide atoms for the area around the blocking boundary where the atoms migrate away due to the electric current. Interconnect lifetime can be prolonged by using the reservoirs, called the "reservoir effect". 2D simulation of the effects of reservoirs has been performed. The stress build-up during electromigration in the contact area can be simulated for several configurations, separating the effects of overlap, total reservoir area, the reservoir layout directions (vertical and horizontal), number of contacts/vias and contact/via placement. It is very useful for IC design rules to estimate which parameters are important for IC reliability. In this study, we considered the critical stress that the metal line can sustain before void formation as failure criterion. The failure time is determined by the time to reach the critical stress.
W-plug/ 金属条纹结构中的电迁移行为不同于传统的金属条纹结构，因为在触点/通孔中存在一个由固定不动的 W-plug 形成的阻挡边界。与金属条状结构相比，电迁移故障更容易发生在靠近 W 形插头的地方，因为金属离子会被电流逼离接触点/通孔，从而阻塞接触点/通孔区域。一些研究报告指出，多层互连的电迁移寿命受触点/通孔周围储层的影响。储层是不导电或几乎不导电的金属部件，可作为源为阻塞边界周围的区域提供原子，原子会因电流而迁移。利用储层可以延长互连寿命，这被称为 "储层效应"。我们对储层效应进行了二维模拟。可以针对多种配置模拟接触区电迁移过程中的应力积累，并将重叠、总蓄水池面积、蓄水池布局方向（垂直和水平）、触点/通孔数量以及触点/通孔位置的影响分开。对于集成电路设计规则来说，估计哪些参数对集成电路可靠性非常重要非常有用。在本研究中，我们将金属线在空洞形成之前可承受的临界应力作为失效标准。失效时间由达到临界应力的时间决定。
{"title":"Modelling of the reservoir effect on electromigration lifetime","authors":"H. Nguyen, C. Salm, T. Mouthaan, F. Kuper","doi":"10.1109/IPFA.2001.941479","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941479","url":null,"abstract":"Electromigration behaviour in W-plug/metal stripe structures is different from conventional metal-strip structures because there is a blocking boundary formed by the immobile W-plug in the contact/via. Electromigration failures occur more readily close to the W-plug than in metal-strip structures because metal ions are forced away from the contacts/vias by electric current, blocking the contacts/vias area. Several works have reported electromigration lifetime of multiple level interconnects to be influenced by the presence of a reservoir around the contacts/vias. Reservoirs are metal parts that are not or are hardly conducting current that act as a source to provide atoms for the area around the blocking boundary where the atoms migrate away due to the electric current. Interconnect lifetime can be prolonged by using the reservoirs, called the \"reservoir effect\". 2D simulation of the effects of reservoirs has been performed. The stress build-up during electromigration in the contact area can be simulated for several configurations, separating the effects of overlap, total reservoir area, the reservoir layout directions (vertical and horizontal), number of contacts/vias and contact/via placement. It is very useful for IC design rules to estimate which parameters are important for IC reliability. In this study, we considered the critical stress that the metal line can sustain before void formation as failure criterion. The failure time is determined by the time to reach the critical stress.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129572898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941474
T. Moore, D. Vanderstraeten, P. Forssell
The equipment and software for X-ray laminography has advanced rapidly in recent years. The latest systems can distinguish features as small as 5 /spl mu/m in diameter and identify their locations to within 10 /spl mu/m in three dimensions within an IC package. Details of complex closely spaced structures can be extracted readily with recently developed microlaminographs. At this resolution, the method is termed microlaminography. In this paper, the technology, methodology and results from a microlaminography system developed for failure analysis in IC packaging are presented. The copper traces in the built up layers of a BGA substrate were extracted and analysed individually. Bond-wire shorts in the plane of the solder resist in a lot of BGA assemblies were located and identified with subsequent verification by destructive physical analysis (DPA). 3D reconstructions of individual solder balls within an assembly were created and examined for defects. These analyses could not have been done by normal 2D X-ray; formerly only DPA could extract such information.
{"title":"Determination of BGA structural defects and solder joint defects by 3D X-ray laminography","authors":"T. Moore, D. Vanderstraeten, P. Forssell","doi":"10.1109/IPFA.2001.941474","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941474","url":null,"abstract":"The equipment and software for X-ray laminography has advanced rapidly in recent years. The latest systems can distinguish features as small as 5 /spl mu/m in diameter and identify their locations to within 10 /spl mu/m in three dimensions within an IC package. Details of complex closely spaced structures can be extracted readily with recently developed microlaminographs. At this resolution, the method is termed microlaminography. In this paper, the technology, methodology and results from a microlaminography system developed for failure analysis in IC packaging are presented. The copper traces in the built up layers of a BGA substrate were extracted and analysed individually. Bond-wire shorts in the plane of the solder resist in a lot of BGA assemblies were located and identified with subsequent verification by destructive physical analysis (DPA). 3D reconstructions of individual solder balls within an assembly were created and examined for defects. These analyses could not have been done by normal 2D X-ray; formerly only DPA could extract such information.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130748659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941472
X. He, X. Ma, Y. Zhang
MCM-C technology is based on the use of a multilayer ceramic substrate as the carrier for the various chip devices. Low temperature co-fired ceramic (LTCC), with the advantage of higher wiring density and lower dielectric constant, is widely used as the multilayer substrate for high density electronic packaging, such as MCM-C. The low firing temperature enables the use of precious metals in the conducting layers. With the development of MCM technology, the LTCC substrate is larger and has many more layers to satisfy the increasing assembly performance requirements. However, with the enlargement of substrate area, the firing shrinkage mismatch between the metal conductor and the ceramic matrix leads to the more serious problem of open failures (Imanaka et al., 1992; Miura et al., 1994; Itagaki et al., 1993). In this work, the open failure between via holes and traces in LTCC substrates was studied. The effect of compacting temperature, ceramic particle size, softening point, stack process and firing profile was reported. Finally, by means of coherent shrinkage, the open failure between via holes and traces in LTCC was eliminated effectively.
MCM-C技术是基于使用多层陶瓷衬底作为各种芯片器件的载体。低温共烧陶瓷(LTCC)具有较高的布线密度和较低的介电常数等优点，被广泛用作高密度电子封装的多层衬底，如MCM-C。较低的烧成温度使得在导电层中使用贵金属成为可能。随着MCM技术的发展，LTCC基板尺寸越来越大，层数越来越多，以满足日益增长的组装性能要求。然而，随着衬底面积的扩大，金属导体与陶瓷基体之间的烧成收缩失配会导致更严重的开路失效问题(Imanaka etal .， 1992;Miura et al.， 1994;Itagaki et al.， 1993)。在这项工作中，研究了LTCC衬底中通孔和迹线之间的开放失效。研究了压实温度、陶瓷粒度、软化点、堆积工艺和烧成型态等因素对烧结效果的影响。最后，采用相干收缩的方法，有效地消除了LTCC中通孔和迹线之间的开放破坏。
{"title":"Elimination of opens failure between via holes and traces in LTCC multilayer substrate by coherent shrinkage","authors":"X. He, X. Ma, Y. Zhang","doi":"10.1109/IPFA.2001.941472","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941472","url":null,"abstract":"MCM-C technology is based on the use of a multilayer ceramic substrate as the carrier for the various chip devices. Low temperature co-fired ceramic (LTCC), with the advantage of higher wiring density and lower dielectric constant, is widely used as the multilayer substrate for high density electronic packaging, such as MCM-C. The low firing temperature enables the use of precious metals in the conducting layers. With the development of MCM technology, the LTCC substrate is larger and has many more layers to satisfy the increasing assembly performance requirements. However, with the enlargement of substrate area, the firing shrinkage mismatch between the metal conductor and the ceramic matrix leads to the more serious problem of open failures (Imanaka et al., 1992; Miura et al., 1994; Itagaki et al., 1993). In this work, the open failure between via holes and traces in LTCC substrates was studied. The effect of compacting temperature, ceramic particle size, softening point, stack process and firing profile was reported. Finally, by means of coherent shrinkage, the open failure between via holes and traces in LTCC was eliminated effectively.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124468116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941464
Z.G. Song, G. Qian, J. Y. Dai, Z.R. Guo, S. K. Loh, C. Teh, S. Redkar
The demand for improvement of device speed and reduction of power consumption has driven semiconductor devices to be miniaturized continuously. To develop new process generations, static random access memory (SRAM) is often chosen as the process qualification vehicle because the quality and performance of SRAMs are direct reflections of high density and small feature size, and they are very sensitive to process variation. Therefore, analysis of SRAM failure is a critical time-to market path for process development. During sub-quarter micron process development, the integrity of high aspect ratio contacts was found to be a major concern. For contact defect analysis, focus ion beam (FIB) cross-sectioning is the best method. However, the problem remains of how to identify the defective contact. E-beam testing and optical beam-induced current (OBIC) techniques have been reported as tools for detecting defective contacts. However, few FA labs have such equipment. In this study, a novel technique of contact-level ion-beam induced passive voltage contrast was developed to identify defective contacts employing a FIB station, and its application was demonstrated by SRAM failure analysis.
{"title":"Application of contact-level ion-beam induced passive voltage contrast in failure analysis of static random access memory","authors":"Z.G. Song, G. Qian, J. Y. Dai, Z.R. Guo, S. K. Loh, C. Teh, S. Redkar","doi":"10.1109/IPFA.2001.941464","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941464","url":null,"abstract":"The demand for improvement of device speed and reduction of power consumption has driven semiconductor devices to be miniaturized continuously. To develop new process generations, static random access memory (SRAM) is often chosen as the process qualification vehicle because the quality and performance of SRAMs are direct reflections of high density and small feature size, and they are very sensitive to process variation. Therefore, analysis of SRAM failure is a critical time-to market path for process development. During sub-quarter micron process development, the integrity of high aspect ratio contacts was found to be a major concern. For contact defect analysis, focus ion beam (FIB) cross-sectioning is the best method. However, the problem remains of how to identify the defective contact. E-beam testing and optical beam-induced current (OBIC) techniques have been reported as tools for detecting defective contacts. However, few FA labs have such equipment. In this study, a novel technique of contact-level ion-beam induced passive voltage contrast was developed to identify defective contacts employing a FIB station, and its application was demonstrated by SRAM failure analysis.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116305286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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