Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941450
H. Iwai
Recently, information technology (IT) such as Internet, i-mode, cellular phones, and car navigation has spread very rapidly all over the world. It is expected to dramatically raise the efficiency of our society and greatly improve the quality of life. It should be noted that the progress of IT is entirely owed to that of semiconductor technology, especially silicon LSIs. Silicon LSIs provide high speed/frequency operation of a tremendous number of functions with low cost, low power, small size, small weight, and high reliability. In the last 30 years, MOSFET gate length has reduced by 100 times, DRAM density has increased 500,000 times, and MPU clock frequency has increased 2,500 times. Without such marvellous progress in LSI technologies, current successes in information technology would not be realized at all. In this paper, silicon technology from past to future is reviewed for advanced CMOS LSIs.
{"title":"Direction of silicon technology from past to future","authors":"H. Iwai","doi":"10.1109/IPFA.2001.941450","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941450","url":null,"abstract":"Recently, information technology (IT) such as Internet, i-mode, cellular phones, and car navigation has spread very rapidly all over the world. It is expected to dramatically raise the efficiency of our society and greatly improve the quality of life. It should be noted that the progress of IT is entirely owed to that of semiconductor technology, especially silicon LSIs. Silicon LSIs provide high speed/frequency operation of a tremendous number of functions with low cost, low power, small size, small weight, and high reliability. In the last 30 years, MOSFET gate length has reduced by 100 times, DRAM density has increased 500,000 times, and MPU clock frequency has increased 2,500 times. Without such marvellous progress in LSI technologies, current successes in information technology would not be realized at all. In this paper, silicon technology from past to future is reviewed for advanced CMOS LSIs.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130754340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941484
S. Liebert
Reproducible back side sample preparation and failure analysis methods becomes increasingly important due to the increasing number of metal levels within semiconductor devices and the ongoing transition to new packages like flip-chip or lead-on-chip. Defects are often located in the lowest chip levels, which make front side electrical defect localization very difficult. Otherwise electrical defect localization in flip-chip and lead-on-chip devices is only possible from the die back side. We developed a failure analysis flow for these die types which contains back side and front side failure analysis methods, consisting of back side photoemission microscopy after bulk Si thinning and electrical recontacting of the die for electrical defect localization. From the type of stress test, test results and fault location, the defect type can often be deduced. With junction leakage, latch up or Al spiking, the die should be prepared for front side analysis, since during further back side preparation, the whole die active area is removed. Gate oxide defects, particles and interrupted conductive interconnects can be analyzed from both the front and back sides of the die. Due to die fragility after bulk Si thinning for electrical defect localization, defect preparation becomes much easier from the back side. After bulk Si removal, optical inspection is possible. Particles or, for example, damage caused by electrostatic overstress might be visible. Gate oxide defects are analyzable by SEM and interrupted conductive interconnects are detectable using passive voltage contrast or electrical probing with AFM.
{"title":"Failure analysis from the back side of a die","authors":"S. Liebert","doi":"10.1109/IPFA.2001.941484","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941484","url":null,"abstract":"Reproducible back side sample preparation and failure analysis methods becomes increasingly important due to the increasing number of metal levels within semiconductor devices and the ongoing transition to new packages like flip-chip or lead-on-chip. Defects are often located in the lowest chip levels, which make front side electrical defect localization very difficult. Otherwise electrical defect localization in flip-chip and lead-on-chip devices is only possible from the die back side. We developed a failure analysis flow for these die types which contains back side and front side failure analysis methods, consisting of back side photoemission microscopy after bulk Si thinning and electrical recontacting of the die for electrical defect localization. From the type of stress test, test results and fault location, the defect type can often be deduced. With junction leakage, latch up or Al spiking, the die should be prepared for front side analysis, since during further back side preparation, the whole die active area is removed. Gate oxide defects, particles and interrupted conductive interconnects can be analyzed from both the front and back sides of the die. Due to die fragility after bulk Si thinning for electrical defect localization, defect preparation becomes much easier from the back side. After bulk Si removal, optical inspection is possible. Particles or, for example, damage caused by electrostatic overstress might be visible. Gate oxide defects are analyzable by SEM and interrupted conductive interconnects are detectable using passive voltage contrast or electrical probing with AFM.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125827512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941463
L. W. Chu, W. Chim, K. Pey, A. See
A novel technique of combining 1/f noise and resistance measurements for characterising electrostatic discharge (ESD) induced voiding damage in aluminium interconnects is reported. The ESD stress was performed using the transmission line pulsing (TLP) technique. Samples of different line widths, with and without an overlying passivation, were studied.
{"title":"Effect of transmission line pulsing of interconnects investigated using combined low-frequency noise and resistance measurements","authors":"L. W. Chu, W. Chim, K. Pey, A. See","doi":"10.1109/IPFA.2001.941463","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941463","url":null,"abstract":"A novel technique of combining 1/f noise and resistance measurements for characterising electrostatic discharge (ESD) induced voiding damage in aluminium interconnects is reported. The ESD stress was performed using the transmission line pulsing (TLP) technique. Samples of different line widths, with and without an overlying passivation, were studied.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121546019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-01DOI: 10.1109/IPFA.2001.941459
J. Reiner, T. Keller, H. Jaggi, S. Mira
The impact of ESD-induced soft drain junction damage on product lifetime was investigated. Several thousand input-output (I/O) pads of a 0.35 /spl mu/m CMOS IC were stressed by ESD (electrostatic discharge) and subsequently subjected to bakes, ESD re-stress and high temperature operating life tests. While the ESD-induced soft drain junction damage appears to be stable versus temperature stress and ESD re-stress, it results in early failures during accelerated operating life tests. These life test failures are caused by breakdown of the gate oxide which was left unbroken during the ESD stress that caused the ESD-induced soft drain junction damage. Thus, ESD-induced soft drain junction damage might cause a reliability risk (latent ESD failure). Consequently, it needs to be avoided by assuring sufficient robustness of the IC against this ESD damage mechanism. A leakage current criterion of 1 /spl mu/A is rather large to detect this kind of damage after ESD stress.
{"title":"Impact of ESD-induced soft drain junction damage on CMOS product lifetime","authors":"J. Reiner, T. Keller, H. Jaggi, S. Mira","doi":"10.1109/IPFA.2001.941459","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941459","url":null,"abstract":"The impact of ESD-induced soft drain junction damage on product lifetime was investigated. Several thousand input-output (I/O) pads of a 0.35 /spl mu/m CMOS IC were stressed by ESD (electrostatic discharge) and subsequently subjected to bakes, ESD re-stress and high temperature operating life tests. While the ESD-induced soft drain junction damage appears to be stable versus temperature stress and ESD re-stress, it results in early failures during accelerated operating life tests. These life test failures are caused by breakdown of the gate oxide which was left unbroken during the ESD stress that caused the ESD-induced soft drain junction damage. Thus, ESD-induced soft drain junction damage might cause a reliability risk (latent ESD failure). Consequently, it needs to be avoided by assuring sufficient robustness of the IC against this ESD damage mechanism. A leakage current criterion of 1 /spl mu/A is rather large to detect this kind of damage after ESD stress.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129635300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IPFA.2001.941453
J.F. Zhang, H. K. Sii, G. Groeseneken, R. Degraeve
Oxide breakdown is a potential showstopper for future CMOS technology. Defect generation is responsible for the breakdown. Previous work (Degraeve et al., 2000; Stathis and DiMaria, 1999; Zhang et al, 1992) was focused on electron trap generation, while little information is available on hole trap generation. This paper unambiguously shows that a significant amount of hole traps can be created.
氧化物击穿是未来CMOS技术的潜在亮点。缺陷的产生是造成故障的原因。以前的工作(Degraeve et al.， 2000;Stathis and DiMaria, 1999;Zhang et al .， 1992)的研究重点是电子陷阱的产生，而空穴陷阱的产生信息较少。这篇论文明确地表明，大量的空穴陷阱是可以被创造出来的。
{"title":"Generation of hole traps in silicon dioxides","authors":"J.F. Zhang, H. K. Sii, G. Groeseneken, R. Degraeve","doi":"10.1109/IPFA.2001.941453","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941453","url":null,"abstract":"Oxide breakdown is a potential showstopper for future CMOS technology. Defect generation is responsible for the breakdown. Previous work (Degraeve et al., 2000; Stathis and DiMaria, 1999; Zhang et al, 1992) was focused on electron trap generation, while little information is available on hole trap generation. This paper unambiguously shows that a significant amount of hole traps can be created.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"622 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130845740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IPFA.2001.941496
M. Lau, C.T. Hsu, Y. Yeow
The DC gated-diode current measurement has been used extensively to study hot-carrier induced degradation in MOSFETs. This technique relies on the property of interface states acting as effective recombination centres to detect their presence. According to Shockley-Read-Hall recombination theory (Muller and Kamins, 1986), gated-diode generation/recombination current is mainly contributed by states close to the midgap. This paper presents a study of the small-signal characteristics of the drain-to-substrate junction of an n-channel MOSFET configured as a gated diode to study hot-carrier induced degradation. This small-signal admittance consists of the small-signal drain-to-substrate capacitance and conductance (C/sub db/ and G/sub db/). Similar to DC gated diode characterisation, the small signal admittance uses the change in the space charge region of the gated-diode to detect the presence and the spatial distribution of hot-carrier induced interface and trapped charges. G/sub db/ is sensitive to change in midgap interface states acting as recombination centres as well as any change in bulk recombination due to change in the volume of the spatial charge region. It corresponds to the slope of the DC diode I-V characteristics of the junction. Change in C/sub db/ reflects the width of the diode space charge region. Therefore, the information obtained from the analysis of C/sub db/ and G/sub db/ before and after electrical stressing are complementary to each other. We compare experimental results for C/sub db/ and G/sub db/ to show the applicability of this method to characterize hot carrier stress response of submicron MOSFETs.
{"title":"Investigation of hot-carrier induced interface damages via small-signal characteristics of drain-to-substrate gated-diode","authors":"M. Lau, C.T. Hsu, Y. Yeow","doi":"10.1109/IPFA.2001.941496","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941496","url":null,"abstract":"The DC gated-diode current measurement has been used extensively to study hot-carrier induced degradation in MOSFETs. This technique relies on the property of interface states acting as effective recombination centres to detect their presence. According to Shockley-Read-Hall recombination theory (Muller and Kamins, 1986), gated-diode generation/recombination current is mainly contributed by states close to the midgap. This paper presents a study of the small-signal characteristics of the drain-to-substrate junction of an n-channel MOSFET configured as a gated diode to study hot-carrier induced degradation. This small-signal admittance consists of the small-signal drain-to-substrate capacitance and conductance (C/sub db/ and G/sub db/). Similar to DC gated diode characterisation, the small signal admittance uses the change in the space charge region of the gated-diode to detect the presence and the spatial distribution of hot-carrier induced interface and trapped charges. G/sub db/ is sensitive to change in midgap interface states acting as recombination centres as well as any change in bulk recombination due to change in the volume of the spatial charge region. It corresponds to the slope of the DC diode I-V characteristics of the junction. Change in C/sub db/ reflects the width of the diode space charge region. Therefore, the information obtained from the analysis of C/sub db/ and G/sub db/ before and after electrical stressing are complementary to each other. We compare experimental results for C/sub db/ and G/sub db/ to show the applicability of this method to characterize hot carrier stress response of submicron MOSFETs.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116718643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IPFA.2001.941482
J. Y. Dai, S. K. Loh, S. F. Tee, C. L. Tay, S. Ansari, E. Er, S. Redkar
In submicron multilevel metallization CMOS devices, high resistance vias and open via contacts are a common issue that can cause low yield and reliability problems (Islamraja et al., 1992). Via failure modes such as contaminated via, delaminated via and blown via contacts have been well documented (Hamanaka et al., 1994; Chen et al., 1995). Compared to the open via contact, a high resistance via due to insufficient process margin is more difficult to isolate and physically characterize. It has been reported that F contamination induces resistance variations and leads to timing issues in the SRAM (Perungulam et al., 2000). However, understanding of the F diffusion mechanism through the Ti-TiN barrier metal layer and the correlation with the barrier metal properties and thus the failure mechanism during reliability testing is still limited. In this paper, the failure mechanism of high via resistance caused by F diffusion was studied by transmission electron microscopy (TEM) at different process split steps. Properties of different barrier metal layers by different processes are also discussed.
在亚微米多层金属化CMOS器件中，高电阻过孔和开孔触点是一个常见的问题，可能导致低产量和可靠性问题(Islamraja等人，1992)。经孔失效模式，如污染经孔、分层经孔和吹过的经孔触点已被详细记录(Hamanaka等人，1994;Chen et al.， 1995)。与开孔接触相比，由于工艺裕度不足而导致的高电阻通孔更难隔离和物理表征。据报道，F污染会引起SRAM的阻力变化并导致定时问题(Perungulam et al.， 2000)。然而，对于F通过Ti-TiN势垒金属层的扩散机制以及与势垒金属性能的关系以及可靠性测试中的失效机制的理解仍然有限。本文利用透射电镜研究了不同工艺分离步骤下F扩散引起的高通孔电阻失效机理。讨论了不同工艺制备的不同阻挡层的性能。
{"title":"High resistance via induced by marginal barrier metal step coverage and F diffusion","authors":"J. Y. Dai, S. K. Loh, S. F. Tee, C. L. Tay, S. Ansari, E. Er, S. Redkar","doi":"10.1109/IPFA.2001.941482","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941482","url":null,"abstract":"In submicron multilevel metallization CMOS devices, high resistance vias and open via contacts are a common issue that can cause low yield and reliability problems (Islamraja et al., 1992). Via failure modes such as contaminated via, delaminated via and blown via contacts have been well documented (Hamanaka et al., 1994; Chen et al., 1995). Compared to the open via contact, a high resistance via due to insufficient process margin is more difficult to isolate and physically characterize. It has been reported that F contamination induces resistance variations and leads to timing issues in the SRAM (Perungulam et al., 2000). However, understanding of the F diffusion mechanism through the Ti-TiN barrier metal layer and the correlation with the barrier metal properties and thus the failure mechanism during reliability testing is still limited. In this paper, the failure mechanism of high via resistance caused by F diffusion was studied by transmission electron microscopy (TEM) at different process split steps. Properties of different barrier metal layers by different processes are also discussed.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129323190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IPFA.2001.941462
M. Ker, Kei-Kang Hung, H. Tang, S. Huang, S.-S. Chen, M. Wang
Due to the low thermal conductivity of the buried oxide underneath the thin-film silicon layer and the shallow-trench-isolation (STI) structure on the insulating layer, electrostatic discharge (ESD) robustness of CMOS devices in silicon-on-insulator (SOI) CMOS technology has become a major reliability challenge (Chan et al., 1994; Raha et al., 1999; Smith, 1998). As SOI technology continues to be scaled down, the thickness of the top layer silicon film is decreased, and the junction area for ESD protection devices to discharge ESD current becomes smaller. Therefore, the ability to dissipate the heat generated by ESD events in SOI CMOS ICs is seriously degraded. In this paper, two novel diode structures with effective larger p-n junction area for better heat dissipation in partially-depleted SOI CMOS technology are proposed. The I-V characteristics and ESD robustness of these new diodes are investigated and compared to that of the Lubistor diode (Voldman et al., 1996).
由于薄膜硅层下埋藏氧化物的低导热性和绝缘层上的浅沟隔离(STI)结构，在绝缘体上硅(SOI) CMOS技术中CMOS器件的静电放电(ESD)稳健性已成为主要的可靠性挑战(Chan et al.， 1994;Raha et al.， 1999;史密斯,1998)。随着SOI技术的不断缩小，顶层硅膜的厚度减小，用于ESD保护器件放电ESD电流的结面积变小。因此，SOI CMOS ic中由ESD事件产生的热量的散热能力严重下降。在部分耗尽SOI CMOS技术中，提出了两种具有更大p-n结面积的新型二极管结构，以获得更好的散热效果。对这些新型二极管的I-V特性和ESD稳健性进行了研究，并与Lubistor二极管进行了比较(Voldman et al.， 1996)。
{"title":"Novel diode structures and ESD protection circuits in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicided CMOS process","authors":"M. Ker, Kei-Kang Hung, H. Tang, S. Huang, S.-S. Chen, M. Wang","doi":"10.1109/IPFA.2001.941462","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941462","url":null,"abstract":"Due to the low thermal conductivity of the buried oxide underneath the thin-film silicon layer and the shallow-trench-isolation (STI) structure on the insulating layer, electrostatic discharge (ESD) robustness of CMOS devices in silicon-on-insulator (SOI) CMOS technology has become a major reliability challenge (Chan et al., 1994; Raha et al., 1999; Smith, 1998). As SOI technology continues to be scaled down, the thickness of the top layer silicon film is decreased, and the junction area for ESD protection devices to discharge ESD current becomes smaller. Therefore, the ability to dissipate the heat generated by ESD events in SOI CMOS ICs is seriously degraded. In this paper, two novel diode structures with effective larger p-n junction area for better heat dissipation in partially-depleted SOI CMOS technology are proposed. The I-V characteristics and ESD robustness of these new diodes are investigated and compared to that of the Lubistor diode (Voldman et al., 1996).","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129282733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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