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Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)最新文献

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Influence of impact ionization stresses on AlGaAs-InGaAs HEMT performances 冲击电离应力对AlGaAs-InGaAs HEMT性能的影响
B. Lambert, N. Malbert, Labat, A. Touboul, P. Huguet
Pseudomorphic HEMTs are widely used in medium power applications. Users are concerned by the reliability of PHEMT-based technologies submitted to RF overdrive. In particular, III-V FETs may suffer from impact ionization effect and surface related mechanisms. The small-signal response of interface states at passivated III-V semiconductor surfaces has been measured over a wide frequency range from 1 Hz to microwave frequencies (Iizuka et al, 1997). During RF operation, impact ionization mechanisms often occur in the channel and their influence on the reliability of devices is not well known. In this work, the effect of life-tests performed on PHEMTs biased in the impact ionization regime with or without thermal stress has been analyzed by monitoring the evolution of DC electrical characteristics and their temperature dependence. The reverse gate current is measured as a function of temperature to observe the behavior of surface traps located at the drain edge of the gate in access regions. Correlation between drain current transients, temperature dependence of the reverse gate current and the on-state breakdown loci is discussed to evaluate both the influence of surface traps on electrical parameters and their evolution after aging.
伪晶hemt广泛应用于中功率领域。用户关心的是基于phemt的技术提交给RF超速驱动的可靠性。特别是III-V型场效应管可能受到冲击电离效应和表面相关机制的影响。钝化III-V半导体表面的界面状态的小信号响应已经在从1hz到微波频率的宽频率范围内进行了测量(Iizuka et al, 1997)。在射频工作过程中,通道中经常发生冲击电离机制,其对器件可靠性的影响尚不清楚。在这项工作中,通过监测直流电气特性的演变及其温度依赖性,分析了在有或没有热应力的冲击电离状态下对phemt进行的寿命测试的影响。测量反向栅极电流作为温度的函数,以观察位于栅极漏极边缘的表面陷阱在通道区域的行为。讨论了漏极电流瞬态、反栅极电流的温度依赖性和导通击穿位点之间的关系,以评估表面陷阱对电学参数的影响及其老化后的演变。
{"title":"Influence of impact ionization stresses on AlGaAs-InGaAs HEMT performances","authors":"B. Lambert, N. Malbert, Labat, A. Touboul, P. Huguet","doi":"10.1109/IPFA.2001.941494","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941494","url":null,"abstract":"Pseudomorphic HEMTs are widely used in medium power applications. Users are concerned by the reliability of PHEMT-based technologies submitted to RF overdrive. In particular, III-V FETs may suffer from impact ionization effect and surface related mechanisms. The small-signal response of interface states at passivated III-V semiconductor surfaces has been measured over a wide frequency range from 1 Hz to microwave frequencies (Iizuka et al, 1997). During RF operation, impact ionization mechanisms often occur in the channel and their influence on the reliability of devices is not well known. In this work, the effect of life-tests performed on PHEMTs biased in the impact ionization regime with or without thermal stress has been analyzed by monitoring the evolution of DC electrical characteristics and their temperature dependence. The reverse gate current is measured as a function of temperature to observe the behavior of surface traps located at the drain edge of the gate in access regions. Correlation between drain current transients, temperature dependence of the reverse gate current and the on-state breakdown loci is discussed to evaluate both the influence of surface traps on electrical parameters and their evolution after aging.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128816571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plasma process-induced latent damage on gate oxide-demonstrated by single-layer and multi-layer antenna structures 等离子体过程对栅极氧化物的潜在损伤——由单层和多层天线结构证明
Zhichun Wang, J. Ackaert, C. Salm, F. Kuper
In this paper, by using both single-layer (SL) and multi-layer (ML) or stacked antenna structures, a simple experimental method is proposed to directly demonstrate the pure plasma process-induced latent damage on gate oxide without any impact of additional defects generated by normal constant current stress (CCS) revealing technique. The presented results show that this method is effective for study of the latent damage.
本文提出了一种简单的实验方法,通过单层(SL)和多层(ML)或堆叠天线结构,直接证明纯等离子体过程引起的栅极氧化物潜在损伤,而不影响常规恒流应力(CCS)揭示技术产生的附加缺陷。结果表明,该方法对潜在损伤的研究是有效的。
{"title":"Plasma process-induced latent damage on gate oxide-demonstrated by single-layer and multi-layer antenna structures","authors":"Zhichun Wang, J. Ackaert, C. Salm, F. Kuper","doi":"10.1109/IPFA.2001.941490","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941490","url":null,"abstract":"In this paper, by using both single-layer (SL) and multi-layer (ML) or stacked antenna structures, a simple experimental method is proposed to directly demonstrate the pure plasma process-induced latent damage on gate oxide without any impact of additional defects generated by normal constant current stress (CCS) revealing technique. The presented results show that this method is effective for study of the latent damage.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122954392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plasma damage in floating metal-insulator-metal capacitors 浮式金属-绝缘体-金属电容器的等离子体损伤
J. Ackaert, Zhichun Wang, E. De Backer, P. Coppens
In this paper, charging induced damage (CID) to metal-insulator-metal capacitors (MIMCs), is reported. CID does not necessarily lead to direct yield loss, but may also induce latent damage leading to reliability losses. The damage is caused by the build up of a voltage potential difference between the two plates of the capacitor. A simple logarithmic relation is discovered between the damage by this voltage potential and the ratio of the area of the exposed antennas connected to the plates of the MIMC. This function allows anticipation of damage in MIMCs with long interconnects.
本文报道了金属-绝缘体-金属电容器(mimc)的充电诱发损伤(CID)。CID不一定会导致直接的产量损失,但也可能引起潜在的损坏,从而导致可靠性损失。损坏是由电容器的两个极板之间电压电位差的累积引起的。在这个电压电位造成的损伤和连接到MIMC板上的暴露天线的面积之比之间发现了一个简单的对数关系。该功能允许在具有长互连的mimc中预测损坏。
{"title":"Plasma damage in floating metal-insulator-metal capacitors","authors":"J. Ackaert, Zhichun Wang, E. De Backer, P. Coppens","doi":"10.1109/IPFA.2001.941491","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941491","url":null,"abstract":"In this paper, charging induced damage (CID) to metal-insulator-metal capacitors (MIMCs), is reported. CID does not necessarily lead to direct yield loss, but may also induce latent damage leading to reliability losses. The damage is caused by the build up of a voltage potential difference between the two plates of the capacitor. A simple logarithmic relation is discovered between the damage by this voltage potential and the ratio of the area of the exposed antennas connected to the plates of the MIMC. This function allows anticipation of damage in MIMCs with long interconnects.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122529962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Solder joint fatigue and reliability of chip scale packages: a failure analysis strategy 芯片规模封装的焊点疲劳与可靠性:失效分析策略
S. Mohamed, C. Francis, L. B. Yew, Tang Wye Mun, L. Ki
This paper outlines an optimal approach for board level chip scale package (CSP) failure analysis, where the chip and printed circuit board (PCB) are analyzed as a single unit. A technique using a combination of cross-section and parallel polishing is described in detail. This technique was specifically developed to inspect key aspects of solder joint fatigue, which are solder joint height, pad dimensions on both package and PCB, substrate warpage, heating profiles/reflow, intermetallic compound (IMC) thickness and solder joint voids.
本文概述了电路板级芯片规模封装(CSP)失效分析的最佳方法,其中芯片和印刷电路板(PCB)作为单个单元进行分析。详细介绍了一种采用横截面与平行抛光相结合的技术。该技术专门用于检查焊点疲劳的关键方面,包括焊点高度、封装和PCB上的焊盘尺寸、基板翘曲、加热轮廓/回流、金属间化合物(IMC)厚度和焊点空隙。
{"title":"Solder joint fatigue and reliability of chip scale packages: a failure analysis strategy","authors":"S. Mohamed, C. Francis, L. B. Yew, Tang Wye Mun, L. Ki","doi":"10.1109/IPFA.2001.941473","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941473","url":null,"abstract":"This paper outlines an optimal approach for board level chip scale package (CSP) failure analysis, where the chip and printed circuit board (PCB) are analyzed as a single unit. A technique using a combination of cross-section and parallel polishing is described in detail. This technique was specifically developed to inspect key aspects of solder joint fatigue, which are solder joint height, pad dimensions on both package and PCB, substrate warpage, heating profiles/reflow, intermetallic compound (IMC) thickness and solder joint voids.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123200422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Poly-residue-induced contact failures in 0.18 /spl mu/m technology 在0.18 /spl mu/m技术中,聚残渣引起的接触失效
C. Teh, Z. Song, J. Y. Dai, Z.R. Guo, S. Redkar
During the qualification of a 0.18 /spl mu/m SRAM process technology, severe yield loss due to random single bit and dual bit failures were encountered. This occurred not only at wafer sort, as failures of these types had also manifested themselves as time-dependent since some of these failures emerged only after certain kinds of reliability tests. Though bit mapping using the MOSAID tester always identified the bit location, the failure analysis was still difficult due to the increasing susceptibility of 0.18-micron devices to the fluctuation of device parameters and process related defects. Moreover, the increasing complexity and multiple metal layers with stacked via structures have also made FA even tougher. Usually a combination of several FA techniques must be used to identify the defect. With no exception in this case, an open contact in the SRAM cell that had led to single and dual-bit failures was isolated by the effective passive voltage contrast (PVC) technique.
在0.18 /spl mu/m SRAM工艺技术的鉴定过程中,遇到了由于随机单比特和双比特故障导致的严重良率损失。这种情况不仅发生在晶圆类型上,因为这些类型的故障也表现为时间依赖性,因为其中一些故障仅在某些类型的可靠性测试之后才出现。尽管使用MOSAID测试仪的位映射总是能识别出位的位置,但由于0.18微米器件对器件参数波动和工艺相关缺陷的敏感性增加,失效分析仍然很困难。此外,不断增加的复杂性和多层金属层与堆叠的通孔结构也使FA更加困难。通常必须结合使用几种FA技术来识别缺陷。在这种情况下,SRAM单元中导致单位和双位故障的开触点被有效的无源电压对比(PVC)技术隔离。
{"title":"Poly-residue-induced contact failures in 0.18 /spl mu/m technology","authors":"C. Teh, Z. Song, J. Y. Dai, Z.R. Guo, S. Redkar","doi":"10.1109/IPFA.2001.941467","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941467","url":null,"abstract":"During the qualification of a 0.18 /spl mu/m SRAM process technology, severe yield loss due to random single bit and dual bit failures were encountered. This occurred not only at wafer sort, as failures of these types had also manifested themselves as time-dependent since some of these failures emerged only after certain kinds of reliability tests. Though bit mapping using the MOSAID tester always identified the bit location, the failure analysis was still difficult due to the increasing susceptibility of 0.18-micron devices to the fluctuation of device parameters and process related defects. Moreover, the increasing complexity and multiple metal layers with stacked via structures have also made FA even tougher. Usually a combination of several FA techniques must be used to identify the defect. With no exception in this case, an open contact in the SRAM cell that had led to single and dual-bit failures was isolated by the effective passive voltage contrast (PVC) technique.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132380763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Suppression of metal contamination by gettering 用捕集剂抑制金属污染
J.W.Y. Teo, H. Lim, Y. Jin, J.H. Huang, W.C. Chew, C.K. Leong, F. Gn, M.F. Li, G. Su
Starting-material-related defects and line processes are often blamed for high reliability failure rates of gate oxides. Polished wafers are first observed to have higher gate oxide reliability failure rates compared to epitaxial wafers, leading to the initial presumption that this difference in failure rate is attributed to starting material issues. Further investigations revealed that it is not silicon surface imperfections that are the cause of the high gate oxide reliability failures. Instead, results pinpoint metal contamination as the culprit for high reliability failures. However, metal contamination due to processing of epitaxial wafers is suppressed by the gettering effect of oxygen precipitates inside the silicon substrate.
与起始材料相关的缺陷和生产线工艺通常被归咎于栅氧化物的高可靠性故障率。首先观察到抛光晶圆与外延晶圆相比具有更高的栅极氧化物可靠性故障率,导致初步假设这种故障率差异归因于起始材料问题。进一步的研究表明,硅表面缺陷并不是导致高栅氧化可靠性失效的原因。相反,结果指出金属污染是高可靠性故障的罪魁祸首。然而,由于外延片加工造成的金属污染被硅衬底内氧沉淀的吸污作用所抑制。
{"title":"Suppression of metal contamination by gettering","authors":"J.W.Y. Teo, H. Lim, Y. Jin, J.H. Huang, W.C. Chew, C.K. Leong, F. Gn, M.F. Li, G. Su","doi":"10.1109/IPFA.2001.941489","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941489","url":null,"abstract":"Starting-material-related defects and line processes are often blamed for high reliability failure rates of gate oxides. Polished wafers are first observed to have higher gate oxide reliability failure rates compared to epitaxial wafers, leading to the initial presumption that this difference in failure rate is attributed to starting material issues. Further investigations revealed that it is not silicon surface imperfections that are the cause of the high gate oxide reliability failures. Instead, results pinpoint metal contamination as the culprit for high reliability failures. However, metal contamination due to processing of epitaxial wafers is suppressed by the gettering effect of oxygen precipitates inside the silicon substrate.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131934789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Current leakage fault localization using backside OBIRCH 基于后置birch的电流泄漏故障定位
F. Beaudoin, G. Imbert, P. Perdu, C. Trocque
Localization of current leakage faults in modern ICs is a major challenge in failure analysis. To deal with this issue, several techniques such as liquid crystal thermography and emission microscopy can be used. However, traditional front-side failure analysis techniques are unable to localize faults obscured by several metal layers. This trend, as well as the appearance of new packaging technologies, has driven alternative approaches from the backside of the die. Of the infrared light optical techniques, the optical beam induced resistance change (OBIRCH) technique has shown to be very promising for locating current leakage type faults (Barton et al, 1999; Nikawa et al, 1999). In this paper, a backside failure analysis case study on four-level interconnection BICMOS ICs is presented. Different front side defect localization approaches such as liquid crystal were tried, but none worked since interconnection layers obscured the fault. Backside emission microscopy also failed due to the resistive nature of the defect. Only the OBIRCH technique could quickly and precisely localize the defect causing current leakage from the backside of the die.
现代集成电路中漏电流故障的定位是故障分析的主要挑战。为了解决这个问题,可以使用液晶热成像和发射显微镜等几种技术。然而,传统的前端故障分析技术无法对被多层金属层遮挡的故障进行定位。这一趋势,以及新的包装技术的出现,已经从模具的背面驱动替代方法。在红外光光学技术中,光束感应电阻变化(OBIRCH)技术在定位漏电流型故障方面非常有前途(Barton等,1999;Nikawa et al, 1999)。本文介绍了四层互连BICMOS集成电路的背面失效分析实例。由于互连层遮挡了故障,采用了液晶等不同的正面缺陷定位方法,但均不成功。由于缺陷的电阻性,背面发射显微镜也失败了。只有OBIRCH技术才能快速准确地定位导致模具背面漏电流的缺陷。
{"title":"Current leakage fault localization using backside OBIRCH","authors":"F. Beaudoin, G. Imbert, P. Perdu, C. Trocque","doi":"10.1109/IPFA.2001.941468","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941468","url":null,"abstract":"Localization of current leakage faults in modern ICs is a major challenge in failure analysis. To deal with this issue, several techniques such as liquid crystal thermography and emission microscopy can be used. However, traditional front-side failure analysis techniques are unable to localize faults obscured by several metal layers. This trend, as well as the appearance of new packaging technologies, has driven alternative approaches from the backside of the die. Of the infrared light optical techniques, the optical beam induced resistance change (OBIRCH) technique has shown to be very promising for locating current leakage type faults (Barton et al, 1999; Nikawa et al, 1999). In this paper, a backside failure analysis case study on four-level interconnection BICMOS ICs is presented. Different front side defect localization approaches such as liquid crystal were tried, but none worked since interconnection layers obscured the fault. Backside emission microscopy also failed due to the resistive nature of the defect. Only the OBIRCH technique could quickly and precisely localize the defect causing current leakage from the backside of the die.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"3 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121256987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
The reactive ion etcher as a physical and failure analysis tool for FC-PGA packages 反应离子蚀刻仪作为FC-PGA封装的物理和失效分析工具
Ng Sea Chooi
Failure analysis of integrated circuit packages often requires the selective removal of material such as solder resists, ink swap and more importantly package substrate material. Although mechanical sample preparation has been useful in some cases, it lacks the selectivity needed to precisely control the degree of removal. Reactive ion etching (RIE) has been used during the organic land grid array (OLGA) FA activities for removing package substrate. However, during the development stage of flip chip pin grid array (FCPGA) packaging, the use of RIE faced some difficulty. Further development reveals that package differences such as the addition of pins and larger form factor has caused the proliferation of the usage of RIE from OLGA to FCPGA to be slightly complicated.
集成电路封装的失效分析通常需要选择性地去除材料,如阻焊剂,油墨交换,更重要的是封装衬底材料。虽然机械样品制备在某些情况下是有用的,但它缺乏精确控制去除程度所需的选择性。反应离子蚀刻(RIE)在有机栅极阵列(OLGA) FA活性中用于去除封装衬底。然而,在倒装引脚网格阵列(FCPGA)封装的发展阶段,RIE的使用面临一些困难。进一步的开发表明,封装差异(例如增加引脚和更大的外形尺寸)导致RIE从OLGA到FCPGA的使用扩散略微复杂。
{"title":"The reactive ion etcher as a physical and failure analysis tool for FC-PGA packages","authors":"Ng Sea Chooi","doi":"10.1109/IPFA.2001.941475","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941475","url":null,"abstract":"Failure analysis of integrated circuit packages often requires the selective removal of material such as solder resists, ink swap and more importantly package substrate material. Although mechanical sample preparation has been useful in some cases, it lacks the selectivity needed to precisely control the degree of removal. Reactive ion etching (RIE) has been used during the organic land grid array (OLGA) FA activities for removing package substrate. However, during the development stage of flip chip pin grid array (FCPGA) packaging, the use of RIE faced some difficulty. Further development reveals that package differences such as the addition of pins and larger form factor has caused the proliferation of the usage of RIE from OLGA to FCPGA to be slightly complicated.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128771896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of electron-beam lithography on thin gate oxide reliability 电子束光刻对薄栅氧化物可靠性的影响
Pei Fen Chong, B. Cho, E. Chor, M. Joo
In view of the rapid downscaling of design rules in CMOS technologies, current optical lithography tools are expected to be replaced with shorter wavelength lithography tools in the near future. One of the strong candidates for the next generation lithography tools is electron-beam (e-beam) lithography, in order to achieve the required fine geometry definition. However, e-beam irradiation of MOS structures can induce radiation damage, especially to the thin gate oxide. In this paper, the effects of e-beam lithography on thin gate oxide reliability are studied.
鉴于CMOS技术中设计规则的快速缩小,目前的光学光刻工具有望在不久的将来被更短波长的光刻工具所取代。下一代光刻工具的有力候选之一是电子束(电子束)光刻,以实现所需的精细几何定义。然而,电子束辐照MOS结构会引起辐射损伤,特别是对薄栅氧化物。本文研究了电子束光刻技术对薄栅氧化物可靠性的影响。
{"title":"Effects of electron-beam lithography on thin gate oxide reliability","authors":"Pei Fen Chong, B. Cho, E. Chor, M. Joo","doi":"10.1109/IPFA.2001.941454","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941454","url":null,"abstract":"In view of the rapid downscaling of design rules in CMOS technologies, current optical lithography tools are expected to be replaced with shorter wavelength lithography tools in the near future. One of the strong candidates for the next generation lithography tools is electron-beam (e-beam) lithography, in order to achieve the required fine geometry definition. However, e-beam irradiation of MOS structures can induce radiation damage, especially to the thin gate oxide. In this paper, the effects of e-beam lithography on thin gate oxide reliability are studied.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127059330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Imprint model based on thermionic field emission mechanism considering energy distribution of trap levels 考虑阱能级能量分布的基于热离子场发射机制的压印模型
M. Tajiri, H. Nozawa
In recent years, nonvolatile memories with use of new materials have attracted considerable attention. In particular, ferroelectric RAMs (FeRAMs) (Scott and Araujo, 1989) were realized recently and are expected to take the place of DRAMs and other ROMs. The ferroelectric material used for FeRAMs has perovskite crystal structure with bistable states, each of which corresponds to logic states, "0" and "1". However, to use FeRAMs as main memories of computers, we have to overcome a few reliability issues: (a) retention, a decrease in polarization charge after long-term storage (Gruveman and Tanaka, 2000; Nakao et al, 1998), and relaxation, the decrease in polarization charge immediately after applying voltage; (b) imprint, the shift in specific polarized direction in the hysteresis curve (Hase et al, 1998; Nagasawa and Nozawa, 1999; Al-Sharif et al, 1996; Lee and Ramesh, 1995); (c) fatigue, the decrease in polarizability by repeat writing (Mihara et al, 1994; Lee et al, 2000). SBT thin films are currently investigated because of their high fatigue endurance. However, there are other issues, such as imprint. In this paper, we investigated the characteristics of imprint in SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) and Pb(Zr,Ti)O/sub 3/ (PZT) thin films.
近年来,使用新材料的非易失性存储器引起了人们的广泛关注。特别是,铁电ram (FeRAMs) (Scott和Araujo, 1989)是最近才实现的,有望取代dram和其他rom。用于feram的铁电材料具有具有双稳态的钙钛矿晶体结构,每个双稳态对应于逻辑态“0”和“1”。然而,要使用feram作为计算机的主存储器,我们必须克服几个可靠性问题:(a)保留,长期存储后极化电荷的减少(Gruveman和Tanaka, 2000;Nakao et al, 1998),弛豫,施加电压后立即极化电荷的减少;(b)印记,迟滞曲线中特定极化方向的偏移(Hase et al, 1998;Nagasawa and Nozawa, 1999;al - sharif等人,1996;Lee and Ramesh, 1995);(c)疲劳,重复书写导致极化性降低(Mihara et al ., 1994;Lee et al ., 2000)。SBT薄膜由于具有较高的疲劳耐久性而受到广泛的研究。然而,还有其他问题,如印记。本文研究了SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)薄膜和Pb(Zr,Ti)O/sub 3/ (PZT)薄膜的压印特性。
{"title":"Imprint model based on thermionic field emission mechanism considering energy distribution of trap levels","authors":"M. Tajiri, H. Nozawa","doi":"10.1109/IPFA.2001.941493","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941493","url":null,"abstract":"In recent years, nonvolatile memories with use of new materials have attracted considerable attention. In particular, ferroelectric RAMs (FeRAMs) (Scott and Araujo, 1989) were realized recently and are expected to take the place of DRAMs and other ROMs. The ferroelectric material used for FeRAMs has perovskite crystal structure with bistable states, each of which corresponds to logic states, \"0\" and \"1\". However, to use FeRAMs as main memories of computers, we have to overcome a few reliability issues: (a) retention, a decrease in polarization charge after long-term storage (Gruveman and Tanaka, 2000; Nakao et al, 1998), and relaxation, the decrease in polarization charge immediately after applying voltage; (b) imprint, the shift in specific polarized direction in the hysteresis curve (Hase et al, 1998; Nagasawa and Nozawa, 1999; Al-Sharif et al, 1996; Lee and Ramesh, 1995); (c) fatigue, the decrease in polarizability by repeat writing (Mihara et al, 1994; Lee et al, 2000). SBT thin films are currently investigated because of their high fatigue endurance. However, there are other issues, such as imprint. In this paper, we investigated the characteristics of imprint in SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) and Pb(Zr,Ti)O/sub 3/ (PZT) thin films.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"90 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131894765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
期刊
Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)
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